/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_graphics_nobundle_h__ #define __ga102_dev_graphics_nobundle_h__ /* This file is autogenerated. Do not edit */ #define NV_PGRAPH 0x005fffff:0x00400000 /* RW--D */ #define NV_PGRAPH_DEBUG_0 0x00400080 /* RWE4R */ #define NV_PGRAPH_DEBUG_0_BROADCAST_ALL_BUNDLES 0:0 /* RWEVF */ #define NV_PGRAPH_DEBUG_0_BROADCAST_ALL_BUNDLES_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_DEBUG_0_BROADCAST_ALL_BUNDLES_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_0_DATAHIGH 1:1 /* RWEVF */ #define NV_PGRAPH_DEBUG_0_DATAHIGH_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_0_DATAHIGH_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_0_ILLEGAL_METHOD_CHECKS 4:4 /* RWEVF */ #define NV_PGRAPH_DEBUG_0_ILLEGAL_METHOD_CHECKS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_0_ILLEGAL_METHOD_CHECKS_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_0_LAUNCH_CHECKS 6:6 /* RWEVF */ #define NV_PGRAPH_DEBUG_0_LAUNCH_CHECKS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_0_LAUNCH_CHECKS_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_0_METHOD_CHECKS 7:7 /* RWEVF */ #define NV_PGRAPH_DEBUG_0_METHOD_CHECKS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_0_METHOD_CHECKS_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_0_ZEROBIT_CHECKS 8:8 /* RWEVF */ #define NV_PGRAPH_DEBUG_0_ZEROBIT_CHECKS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_0_ZEROBIT_CHECKS_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_0_FE_EMITTER 9:9 /* RWEVF */ #define NV_PGRAPH_DEBUG_0_FE_EMITTER_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_0_FE_EMITTER_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_0_SCG_FORCE_SLOW_DRAIN_TPC 11:11 /* RWEVF */ #define NV_PGRAPH_DEBUG_0_SCG_FORCE_SLOW_DRAIN_TPC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_DEBUG_0_SCG_FORCE_SLOW_DRAIN_TPC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_0_SCG_SCHEDULING_MODE_ALWAYS_MIXED 12:12 /* RWEVF */ #define NV_PGRAPH_DEBUG_0_SCG_SCHEDULING_MODE_ALWAYS_MIXED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_DEBUG_0_SCG_SCHEDULING_MODE_ALWAYS_MIXED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_0_ZERO_TIMESTAMPS 14:14 /* RWEVF */ #define NV_PGRAPH_DEBUG_0_ZERO_TIMESTAMPS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_DEBUG_0_ZERO_TIMESTAMPS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_0_SCG_STALL_CWD_WHEN_DRAIN_FIFO_FULL 15:15 /* RWEVF */ #define NV_PGRAPH_DEBUG_0_SCG_STALL_CWD_WHEN_DRAIN_FIFO_FULL_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_DEBUG_0_SCG_STALL_CWD_WHEN_DRAIN_FIFO_FULL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_0_STATUS_SETTLE 31:16 /* RWEVF */ #define NV_PGRAPH_DEBUG_0_STATUS_SETTLE_INIT 0x0018 /* RWE-V */ #define NV_PGRAPH_DEBUG_0_STATUS_SETTLE__PROD 0x0030 /* RW--V */ #define NV_PGRAPH_DEBUG_0_STATUS_SETTLE_MIN 0x0010 /* RW--V */ #define NV_PGRAPH_DEBUG_1 0x00400084 /* RWE4R */ #define NV_PGRAPH_DEBUG_1_PM 5:5 /* RWEVF */ #define NV_PGRAPH_DEBUG_1_PM_IGNORE 0x0 /* R-E-V */ #define NV_PGRAPH_DEBUG_1_PM_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_DEBUG_1_PM_STOP 8:8 /* RWEVF */ #define NV_PGRAPH_DEBUG_1_PM_STOP_IGNORE 0x0 /* R-E-V */ #define NV_PGRAPH_DEBUG_1_PM_STOP_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_DEBUG_2 0x00400088 /* RWE4R */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_WRITE 0:0 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_WRITE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_WRITE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_WRITE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_AWAKEN 1:1 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_AWAKEN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_AWAKEN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_AWAKEN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_BROADCAST_GO_IDLE 2:2 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_BROADCAST_GO_IDLE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_BROADCAST_GO_IDLE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_BROADCAST_GO_IDLE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_BROADCAST_COMPUTE_GO_IDLE 3:3 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_BROADCAST_COMPUTE_GO_IDLE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_BROADCAST_COMPUTE_GO_IDLE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_BROADCAST_COMPUTE_GO_IDLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_HOLD_STATUS_UNTIL_PIPE_ACTIVE 4:4 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_HOLD_STATUS_UNTIL_PIPE_ACTIVE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_HOLD_STATUS_UNTIL_PIPE_ACTIVE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_HOLD_STATUS_UNTIL_PIPE_ACTIVE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_SEMAPHORE_AWAKEN 5:5 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_SEMAPHORE_AWAKEN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_SEMAPHORE_AWAKEN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_SEMAPHORE_AWAKEN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_MEMFMT_AWAKEN 6:6 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_MEMFMT_AWAKEN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_MEMFMT_AWAKEN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_MEMFMT_AWAKEN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_NO_RMW_REQUIRED 7:7 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_NO_RMW_REQUIRED_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_NO_RMW_REQUIRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_NO_RMW_REQUIRED_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_WFI_CONDITIONAL 8:8 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_WFI_CONDITIONAL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_WFI_CONDITIONAL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_WFI_CONDITIONAL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_FLUSH_DISABLE_FLAG 9:9 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_FLUSH_DISABLE_FLAG_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_DISABLE_FLAG_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_DISABLE_FLAG_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_THREED_SUBCHANNEL 10:10 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_THREED_SUBCHANNEL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_THREED_SUBCHANNEL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_THREED_SUBCHANNEL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_TWOD_SUBCHANNEL 11:11 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_TWOD_SUBCHANNEL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_TWOD_SUBCHANNEL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_TWOD_SUBCHANNEL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_M2M_SUBCHANNEL 12:12 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_M2M_SUBCHANNEL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_M2M_SUBCHANNEL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_M2M_SUBCHANNEL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_COMPUTE_SUBCHANNEL 13:13 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_COMPUTE_SUBCHANNEL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_COMPUTE_SUBCHANNEL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_COMPUTE_SUBCHANNEL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_HOST_SUBCHANNEL 15:15 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_HOST_SUBCHANNEL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_HOST_SUBCHANNEL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_HOST_SUBCHANNEL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_GRAPHICS_AUTO_GO_IDLE 17:17 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_GRAPHICS_AUTO_GO_IDLE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_GRAPHICS_AUTO_GO_IDLE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_COMPUTE_AUTO_GO_IDLE 18:18 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_COMPUTE_AUTO_GO_IDLE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_COMPUTE_AUTO_GO_IDLE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_AUTO_GO_IDLE_HWW 19:19 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_AUTO_GO_IDLE_HWW_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_AUTO_GO_IDLE_HWW_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_AUTO_GO_IDLE_HWW_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_NO_WFI_AFTER_ILLEGAL_METHOD_INTERRUPT 22:22 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_NO_WFI_AFTER_ILLEGAL_METHOD_INTERRUPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_NO_WFI_AFTER_ILLEGAL_METHOD_INTERRUPT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_NO_WFI_AFTER_ILLEGAL_METHOD_INTERRUPT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_GFXP_WFI_ALWAYS_INJECTS_WFI 23:23 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_GFXP_WFI_ALWAYS_INJECTS_WFI_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_GFXP_WFI_ALWAYS_INJECTS_WFI_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_GFXP_WFI_ALWAYS_INJECTS_WFI_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_GO_IDLE 25:24 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_GO_IDLE_NONE 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_GO_IDLE_ASYNC 0x2 /* RW--V */ #define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_GO_IDLE_BOTH 0x3 /* RW--V */ #define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_GO_IDLE_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_PREEMPT 26:26 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_PREEMPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_PREEMPT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_PREEMPT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_GFXP_WFI_TIMEOUT_UNIT 27:27 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_GFXP_WFI_TIMEOUT_UNIT_USEC 0x0 /* RW--V */ #define NV_PGRAPH_DEBUG_2_GFXP_WFI_TIMEOUT_UNIT_SYSCLK 0x1 /* RW--V */ #define NV_PGRAPH_DEBUG_2_GFXP_WFI_TIMEOUT_UNIT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_DEBUG_2_CYA_SPARE 31:28 /* RWEVF */ #define NV_PGRAPH_DEBUG_2_CYA_SPARE_INIT 0xf /* RWE-V */ #define NV_PGRAPH_DEBUG_3 0x0040008c /* RWE4R */ #define NV_PGRAPH_DEBUG_3_HOSTWFI_ACK_SETTLE 15:11 /* RWEVF */ #define NV_PGRAPH_DEBUG_3_HOSTWFI_ACK_SETTLE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_DEBUG_3_ENGINE_STATUS_SETTLE 31:16 /* RWEVF */ #define NV_PGRAPH_DEBUG_3_ENGINE_STATUS_SETTLE_INIT 0x0006 /* RWE-V */ #define NV_PGRAPH_DEBUG_4 0x00400090 /* RWE4R */ #define NV_PGRAPH_DEBUG_4_PM_STALL 15:0 /* RWEVF */ #define NV_PGRAPH_DEBUG_4_PM_STALL_INIT 0x0040 /* RWE-V */ #define NV_PGRAPH_DEBUG_5 0x00400094 /* RWE4R */ #define NV_PGRAPH_DEBUG_5_PM_BOOKMARK 31:0 /* RWEVF */ #define NV_PGRAPH_DEBUG_5_PM_BOOKMARK_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_INTR 0x00400100 /* RWE4R */ #define NV_PGRAPH_INTR_NOTIFY 0:0 /* RWEVF */ #define NV_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_INTR_NOTIFY_PENDING 0x1 /* R---V */ #define NV_PGRAPH_INTR_NOTIFY_RESET 0x1 /* -W--T */ #define NV_PGRAPH_INTR_SEMAPHORE 1:1 /* RWEVF */ #define NV_PGRAPH_INTR_SEMAPHORE_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_INTR_SEMAPHORE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_INTR_SEMAPHORE_RESET 0x1 /* -W--T */ #define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 /* RWEVF */ #define NV_PGRAPH_INTR_ILLEGAL_METHOD_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_INTR_ILLEGAL_METHOD_PENDING 0x1 /* R---V */ #define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 0x1 /* -W--T */ #define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 /* RWEVF */ #define NV_PGRAPH_INTR_ILLEGAL_CLASS_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_INTR_ILLEGAL_CLASS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 0x1 /* -W--T */ #define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 /* RWEVF */ #define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_PENDING 0x1 /* R---V */ #define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 0x1 /* -W--T */ #define NV_PGRAPH_INTR_DEBUG_METHOD 7:7 /* RWEVF */ #define NV_PGRAPH_INTR_DEBUG_METHOD_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_INTR_DEBUG_METHOD_PENDING 0x1 /* R---V */ #define NV_PGRAPH_INTR_DEBUG_METHOD_RESET 0x1 /* -W--T */ #define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 /* RWEVF */ #define NV_PGRAPH_INTR_FIRMWARE_METHOD_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_INTR_FIRMWARE_METHOD_PENDING 0x1 /* R---V */ #define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 0x1 /* -W--T */ #define NV_PGRAPH_INTR_BUFFER_NOTIFY 16:16 /* RWEVF */ #define NV_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x1 /* R---V */ #define NV_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x1 /* -W--T */ #define NV_PGRAPH_INTR_FECS_ERROR 19:19 /* RWEVF */ #define NV_PGRAPH_INTR_FECS_ERROR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_INTR_FECS_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_INTR_FECS_ERROR_RESET 0x1 /* -W--T */ #define NV_PGRAPH_INTR_CLASS_ERROR 20:20 /* RWEVF */ #define NV_PGRAPH_INTR_CLASS_ERROR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_INTR_CLASS_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_INTR_CLASS_ERROR_RESET 0x1 /* -W--T */ #define NV_PGRAPH_INTR_EXCEPTION 21:21 /* RWEVF */ #define NV_PGRAPH_INTR_EXCEPTION_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_INTR_EXCEPTION_PENDING 0x1 /* R---V */ #define NV_PGRAPH_INTR_EXCEPTION_RESET 0x1 /* -W--T */ #define NV_PGRAPH_INTR_FE_DEBUG_INTR 22:22 /* RWEVF */ #define NV_PGRAPH_INTR_FE_DEBUG_INTR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_INTR_FE_DEBUG_INTR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_INTR_FE_DEBUG_INTR_RESET 0x1 /* -W--T */ #define NV_PGRAPH_INTR_EN 0x0040013c /* RWE4R */ #define NV_PGRAPH_INTR_EN_NOTIFY 0:0 /* RWEVF */ #define NV_PGRAPH_INTR_EN_NOTIFY_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_NOTIFY__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_SEMAPHORE 1:1 /* RWEVF */ #define NV_PGRAPH_INTR_EN_SEMAPHORE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_EN_SEMAPHORE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_SEMAPHORE__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_ILLEGAL_METHOD 4:4 /* RWEVF */ #define NV_PGRAPH_INTR_EN_ILLEGAL_METHOD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_EN_ILLEGAL_METHOD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_ILLEGAL_METHOD__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_ILLEGAL_CLASS 5:5 /* RWEVF */ #define NV_PGRAPH_INTR_EN_ILLEGAL_CLASS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_EN_ILLEGAL_CLASS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_ILLEGAL_CLASS__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_ILLEGAL_NOTIFY 6:6 /* RWEVF */ #define NV_PGRAPH_INTR_EN_ILLEGAL_NOTIFY_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_EN_ILLEGAL_NOTIFY_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_ILLEGAL_NOTIFY__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_DEBUG_METHOD 7:7 /* RWEVF */ #define NV_PGRAPH_INTR_EN_DEBUG_METHOD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_EN_DEBUG_METHOD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_DEBUG_METHOD__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_FIRMWARE_METHOD 8:8 /* RWEVF */ #define NV_PGRAPH_INTR_EN_FIRMWARE_METHOD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_EN_FIRMWARE_METHOD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_FIRMWARE_METHOD__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY 16:16 /* RWEVF */ #define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_FECS_ERROR 19:19 /* RWEVF */ #define NV_PGRAPH_INTR_EN_FECS_ERROR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_EN_FECS_ERROR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_FECS_ERROR__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_CLASS_ERROR 20:20 /* RWEVF */ #define NV_PGRAPH_INTR_EN_CLASS_ERROR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_EN_CLASS_ERROR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_CLASS_ERROR__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_EXCEPTION 21:21 /* RWEVF */ #define NV_PGRAPH_INTR_EN_EXCEPTION_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_EN_EXCEPTION_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_EXCEPTION__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_FE_DEBUG_INTR 22:22 /* RWEVF */ #define NV_PGRAPH_INTR_EN_FE_DEBUG_INTR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_EN_FE_DEBUG_INTR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_INTR_EN_FE_DEBUG_INTR__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_ROUTE 0x00400140 /* RWE4R */ #define NV_PGRAPH_INTR_ROUTE_ILLEGAL_METHOD 4:4 /* RWEVF */ #define NV_PGRAPH_INTR_ROUTE_ILLEGAL_METHOD_HOST 0x0 /* RWE-V */ #define NV_PGRAPH_INTR_ROUTE_ILLEGAL_METHOD_FECS 0x1 /* RW--V */ #define NV_PGRAPH_INTR_ROUTE_FIRMWARE_METHOD 8:8 /* RWEVF */ #define NV_PGRAPH_INTR_ROUTE_FIRMWARE_METHOD_HOST 0x0 /* RW--V */ #define NV_PGRAPH_INTR_ROUTE_FIRMWARE_METHOD_FECS 0x1 /* RWE-V */ #define NV_PGRAPH_FECS_INTR 0x00400144 /* RWE4R */ #define NV_PGRAPH_FECS_INTR_ILLEGAL_METHOD 4:4 /* RWEVF */ #define NV_PGRAPH_FECS_INTR_ILLEGAL_METHOD_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_FECS_INTR_ILLEGAL_METHOD_PENDING 0x1 /* R---V */ #define NV_PGRAPH_FECS_INTR_ILLEGAL_METHOD_RESET 0x1 /* -W--T */ #define NV_PGRAPH_FECS_INTR_FIRMWARE_METHOD 8:8 /* RWEVF */ #define NV_PGRAPH_FECS_INTR_FIRMWARE_METHOD_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_FECS_INTR_FIRMWARE_METHOD_PENDING 0x1 /* R---V */ #define NV_PGRAPH_FECS_INTR_FIRMWARE_METHOD_RESET 0x1 /* -W--T */ #define NV_PGRAPH_FECS_INTR_EN 0x00400148 /* RWE4R */ #define NV_PGRAPH_FECS_INTR_EN_ILLEGAL_METHOD 4:4 /* RWEVF */ #define NV_PGRAPH_FECS_INTR_EN_ILLEGAL_METHOD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_FECS_INTR_EN_ILLEGAL_METHOD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_FECS_INTR_EN_ILLEGAL_METHOD__PROD 0x1 /* RW--V */ #define NV_PGRAPH_FECS_INTR_EN_FIRMWARE_METHOD 8:8 /* RWEVF */ #define NV_PGRAPH_FECS_INTR_EN_FIRMWARE_METHOD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_FECS_INTR_EN_FIRMWARE_METHOD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_FECS_INTR_EN_FIRMWARE_METHOD__PROD 0x1 /* RW--V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK 0x0040014c /* RWE4R */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK 0x00400150 /* RWE4R */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_INTR_CTRL 0x00400154 /* RW-4R */ #define NV_PGRAPH_INTR_CTRL__PRIV_LEVEL_MASK 0x0040014c /* */ #define NV_PGRAPH_INTR_CTRL_VECTOR 11:0 /* RWXUF */ #define NV_PGRAPH_INTR_CTRL_GFID 25:20 /* RWXUF */ #define NV_PGRAPH_INTR_CTRL_GSP 30:30 /* RWXUF */ #define NV_PGRAPH_INTR_CTRL_GSP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_INTR_CTRL_GSP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_INTR_CTRL_CPU 31:31 /* RWXUF */ #define NV_PGRAPH_INTR_CTRL_CPU_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_INTR_CTRL_CPU_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_INTR_RETRIGGER 0x00400158 /* -W-4R */ #define NV_PGRAPH_INTR_RETRIGGER__PRIV_LEVEL_MASK 0x00400150 /* */ #define NV_PGRAPH_INTR_RETRIGGER_TRIGGER 0:0 /* -WXUF */ #define NV_PGRAPH_INTR_RETRIGGER_TRIGGER_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK 0x0040015c /* RWE4R */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL 0x00400160 /* RW-4R */ #define NV_PGRAPH_INTR_NOTIFY_CTRL__PRIV_LEVEL_MASK 0x0040015c /* */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_VECTOR 11:0 /* RWXUF */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_GFID 25:20 /* RWXUF */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_GSP 30:30 /* RWXUF */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_GSP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_GSP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_CPU 31:31 /* RWXUF */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_CPU_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_INTR_NOTIFY_CTRL_CPU_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_EXCEPTION 0x00400108 /* R--4R */ #define NV_PGRAPH_EXCEPTION_FE 0:0 /* R-EVF */ #define NV_PGRAPH_EXCEPTION_FE_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_EXCEPTION_FE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 /* R-EVF */ #define NV_PGRAPH_EXCEPTION_MEMFMT_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_EXCEPTION_MEMFMT_PENDING 0x1 /* R---V */ #define NV_PGRAPH_EXCEPTION_PD 2:2 /* R-EVF */ #define NV_PGRAPH_EXCEPTION_PD_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_EXCEPTION_PD_PENDING 0x1 /* R---V */ #define NV_PGRAPH_EXCEPTION_SCC 3:3 /* R-EVF */ #define NV_PGRAPH_EXCEPTION_SCC_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_EXCEPTION_SCC_PENDING 0x1 /* R---V */ #define NV_PGRAPH_EXCEPTION_DS 4:4 /* R-EVF */ #define NV_PGRAPH_EXCEPTION_DS_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_EXCEPTION_DS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_EXCEPTION_SSYNC 5:5 /* R-EVF */ #define NV_PGRAPH_EXCEPTION_SSYNC_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_EXCEPTION_SSYNC_PENDING 0x1 /* R---V */ #define NV_PGRAPH_EXCEPTION_MME 7:7 /* R-EVF */ #define NV_PGRAPH_EXCEPTION_MME_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_EXCEPTION_MME_PENDING 0x1 /* R---V */ #define NV_PGRAPH_EXCEPTION_SKED 8:8 /* R-EVF */ #define NV_PGRAPH_EXCEPTION_SKED_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_EXCEPTION_SKED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_EXCEPTION_MME_FE1 9:9 /* R-EVF */ #define NV_PGRAPH_EXCEPTION_MME_FE1_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_EXCEPTION_MME_FE1_PENDING 0x1 /* R---V */ #define NV_PGRAPH_EXCEPTION_GPC 24:24 /* R-EVF */ #define NV_PGRAPH_EXCEPTION_GPC_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_EXCEPTION_GPC_PENDING 0x1 /* R---V */ #define NV_PGRAPH_EXCEPTION1 0x00400118 /* R--4R */ #define NV_PGRAPH_EXCEPTION1_GPC 31:0 /* R-EVF */ #define NV_PGRAPH_EXCEPTION1_GPC_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGRAPH_EXCEPTION1_GPC_0_NOT_PENDING 0x00000000 /* R---V */ #define NV_PGRAPH_EXCEPTION1_GPC_0_PENDING 0x00000001 /* R---V */ #define NV_PGRAPH_EXCEPTION_EN 0x00400138 /* RWE4R */ #define NV_PGRAPH_EXCEPTION_EN_FE 0:0 /* RWEVF */ #define NV_PGRAPH_EXCEPTION_EN_FE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_EXCEPTION_EN_FE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_EXCEPTION_EN_MEMFMT 1:1 /* RWEVF */ #define NV_PGRAPH_EXCEPTION_EN_MEMFMT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_EXCEPTION_EN_MEMFMT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_EXCEPTION_EN_PD 2:2 /* RWEVF */ #define NV_PGRAPH_EXCEPTION_EN_PD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_EXCEPTION_EN_PD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_EXCEPTION_EN_SCC 3:3 /* RWEVF */ #define NV_PGRAPH_EXCEPTION_EN_SCC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_EXCEPTION_EN_SCC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_EXCEPTION_EN_DS 4:4 /* RWEVF */ #define NV_PGRAPH_EXCEPTION_EN_DS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_EXCEPTION_EN_DS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_EXCEPTION_EN_SSYNC 5:5 /* RWEVF */ #define NV_PGRAPH_EXCEPTION_EN_SSYNC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_EXCEPTION_EN_SSYNC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_EXCEPTION_EN_MME 7:7 /* RWEVF */ #define NV_PGRAPH_EXCEPTION_EN_MME_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_EXCEPTION_EN_MME_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_EXCEPTION_EN_SKED 8:8 /* RWEVF */ #define NV_PGRAPH_EXCEPTION_EN_SKED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_EXCEPTION_EN_SKED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_EXCEPTION_EN_MME_FE1 9:9 /* RWEVF */ #define NV_PGRAPH_EXCEPTION_EN_MME_FE1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_EXCEPTION_EN_MME_FE1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_EXCEPTION_EN_GPC 24:24 /* RWEVF */ #define NV_PGRAPH_EXCEPTION_EN_GPC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_EXCEPTION_EN_GPC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_EXCEPTION1_EN 0x00400130 /* RWE4R */ #define NV_PGRAPH_EXCEPTION1_EN_GPC 31:0 /* RWEVF */ #define NV_PGRAPH_EXCEPTION1_EN_GPC_DISABLED 0x00000000 /* RWE-V */ #define NV_PGRAPH_EXCEPTION1_EN_GPC_0_DISABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_EXCEPTION1_EN_GPC_0_ENABLED 0x00000001 /* RW--V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK 0x00400128 /* RWE4R */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_FE_DEBUG_INTR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_FE_DEBUG_INTR 0x0040012c /* -W-4R */ #define NV_PGRAPH_FE_DEBUG_INTR__PRIV_LEVEL_MASK 0x00400128 /* */ #define NV_PGRAPH_FE_DEBUG_INTR_STALL 0:0 /* -WXUF */ #define NV_PGRAPH_FE_DEBUG_INTR_STALL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_FE_DEBUG_INTR_NONSTALL 1:1 /* -WXUF */ #define NV_PGRAPH_FE_DEBUG_INTR_NONSTALL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_CLASS_ERROR 0x00400110 /* R--4R */ #define NV_PGRAPH_CLASS_ERROR_CODE 15:0 /* R-EVF */ #define NV_PGRAPH_CLASS_ERROR_CODE_NOERROR 0x0000 /* R-E-V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_OPERATION 0x0003 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_VALUE 0x0004 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_ENUM 0x0005 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_METHOD 0x0006 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_ARGUMENT 0x0007 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_OBJECT_CLASS 0x0008 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_ACCESS_TYPE 0x0009 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_REGION_TYPE 0x000a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_ALIGNMENT 0x000b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_UNUSED_FIELD 0x000c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_METHOD_IN_BEGIN_END 0x000d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZCULL_SUBREGION_LIMBO 0x000e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_WIDTH 0x000f /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_HEIGHT 0x0010 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_TARGET_FORMAT 0x0013 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_VCAA_SETTING 0x0016 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_ALIGNMENT 0x001a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SAMPLER_SLOT 0x001b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_HEADER_SLOT 0x001c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_CONSTANT_OFFSET 0x001d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_OUTPUT_COUNT_TOO_SMALL 0x0020 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_LAYER_EXCEEDS_DEPTH 0x0021 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHARED_MEMORY_SIZE32_K_B 0x0022 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_I2M_RECT_OUT_OF_BOUNDS 0x0023 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_MEM2_MEM_RECT_OUT_OF_BOUNDS 0x0023 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_VS_INPUT_COUNT 0x0024 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_CLEAR_REQIRES_BLOCK_LINEAR 0x0025 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_GRF_SIZE_GRID_RASTER_DISABLED 0x0026 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_GRF_SIZE_GRID_RASTER_SIMPLE 0x0027 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_REGISTER_ALLOCATION 0x0028 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_GRID_WIDTH_ZERO 0x002a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_THREAD_COUNT_EXCEEDS_DIMENSIONS 0x002b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_CTA_MEMORY_THROTTLE_EXCEEDED 0x002c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_CTA_STACK_THROTTLE_EXCEEDED 0x002d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_MISSING_INITIALIZE 0x002e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_SRC_FORMAT 0x002f /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_SRC_FORMAT_WITH_COLOR_KEY 0x0030 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_DST_FORMAT 0x0031 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_DST_FORMAT_WITH_COLOR_KEY 0x0032 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_DST_FORMAT_WITH_OPERATION 0x0033 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_MISMATCHED_DST_FORMAT 0x0034 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_MISMATCHED_FORMAT_WITH_COLOR_KEY 0x0035 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_Y1_8_X8_REQUIRES_BLOCKLINEAR 0x0036 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_Y1_8_X8_REQUIRES_POINT_SAMPLING 0x0037 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_MONO_PATTERN_COLOR_FORMAT_WITH_DST_FORMAT 0x0038 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LRF_BALANCE_SM0_PS 0x0039 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LRF_BALANCE_SM0_VS 0x003a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LRF_BALANCE_SM1_PS 0x003b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LRF_BALANCE_SM1_VS 0x003c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LRF_BALANCE_SM1_GS 0x003d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_OBSOLETE_PS_INPUT_VIEWPORT_INDEX_ENABLE_FIELD 0x003e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PRIMITIVE_ID_SLOT 0x003f /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PS_REGISTER_ALLOCATION 0x0040 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_WINDOW_OFFSET_Y 0x0041 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_GRF_ALLOCATION 0x0042 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LINE_WIDTH 0x0043 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_VIEWPORT_INDEX_SLOT 0x0044 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_SLOT 0x0045 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_GS_SELECTS_LAYER 0x0046 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_USER_CLIP_SLOT 0x0047 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_POINT_SIZE_SLOT 0x0048 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHARED_MEMORY_SIZE_PER_SM 0x0049 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_SRGB_DST_FORMAT_FOR_SOLID_PRIM 0x004a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_FP_DST_FORMAT_FOR_SOLID_PRIM 0x004b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_DST_FORMAT_FOR_SOLID_PRIM 0x004c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_DST_FORMAT_FOR_PIXELS_FROM_CPU 0x004d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LINE_TOO_LONG 0x004e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_SRC_LINE_TOO_LONG 0x004f /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DST_LINE_TOO_LONG 0x0050 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_SRC_LINE_EXCEEDS_PITCH 0x0051 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_SRC_LINE_EXCEEDS_NEG_PITCH 0x0052 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DST_LINE_EXCEEDS_PITCH 0x0053 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DST_LINE_EXCEEDS_NEG_PITCH 0x0054 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_SRC_INLINE_NOT_PITCH 0x0055 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_GA_TO_VA_MAPPING_UPDATE_WHILE_ENABLED 0x0056 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PITCH_SURFACE_HEIGHT_GREATER_THAN_ONE 0x0057 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_BAD_SRC_PIXEL_COMPONENT_REFERENCE 0x0058 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_TARGET_COUNT 0x0059 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_TARGET0_NOT0 0x005b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_WITHOUT_SEPERATE_ALPHA 0x005c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_WITH_PER_TARGET_BLEND 0x005d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_WITH_DUAL_SOURCE 0x005e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_R_TO_A_WITHOUT_ITERATED_ALPHA 0x005f /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_ALPHA_ILLEGAL_R_TO_A 0x0060 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_WRONG_PROGRAM_SIZE 0x0061 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS01 0x0064 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS02 0x0065 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS12 0x0066 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS03 0x0067 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS13 0x0068 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS23 0x0069 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS04 0x006a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS14 0x006b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS24 0x006c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS34 0x006d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS05 0x006e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS15 0x006f /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS25 0x0070 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS35 0x0071 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS45 0x0072 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS06 0x0073 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS16 0x0074 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS26 0x0075 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS36 0x0076 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS46 0x0077 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS56 0x0078 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS07 0x0079 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS17 0x007a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS27 0x007b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS37 0x007c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS47 0x007d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS57 0x007e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS67 0x007f /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT01 0x0080 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT02 0x0081 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT03 0x0082 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT04 0x0083 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT05 0x0084 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT06 0x0085 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT07 0x0086 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT12 0x0087 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT13 0x0088 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT14 0x0089 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT15 0x008a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT16 0x008b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT17 0x008c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT23 0x008d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT24 0x008e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT25 0x008f /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT26 0x0090 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT27 0x0091 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT34 0x0092 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT35 0x0093 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT36 0x0094 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT37 0x0095 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT45 0x0096 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT46 0x0097 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT47 0x0098 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT56 0x0099 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT57 0x009a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT67 0x009b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR0 0x009c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR1 0x009d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR2 0x009e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR3 0x009f /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR4 0x00a0 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR5 0x00a1 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR6 0x00a2 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR7 0x00a3 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH0 0x00a4 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH1 0x00a5 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH2 0x00a6 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH3 0x00a7 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH4 0x00a8 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH5 0x00a9 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH6 0x00aa /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH7 0x00ab /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR0 0x00ac /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR1 0x00ad /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR2 0x00ae /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR3 0x00af /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR4 0x00b0 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR5 0x00b1 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR6 0x00b2 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR7 0x00b3 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_REGISTER_COUNT0 0x00b4 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_REGISTER_COUNT1 0x00b5 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_REGISTER_COUNT2 0x00b6 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_REGISTER_COUNT3 0x00b7 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_REGISTER_COUNT4 0x00b8 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_REGISTER_COUNT5 0x00b9 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_LOCAL_MEMORY0 0x00ba /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_LOCAL_MEMORY1 0x00bb /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_LOCAL_MEMORY2 0x00bc /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_ENABLES0 0x00bd /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_ENABLES1 0x00be /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_RESTART_TOPOLOGY 0x00bf /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_STREAM_STRIDE0 0x00c0 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_STREAM_STRIDE1 0x00c1 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_STREAM_STRIDE2 0x00c2 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_STREAM_STRIDE3 0x00c3 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHARED_LOCAL_OVERLAP 0x00cc /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHARED_MEMORY_SIZE16_K_B 0x00cd /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHARED_MEMORY_SIZE48_K_B 0x00ce /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TWO_SIDED_LIGHTING_ILLEGAL_WITH_SM3_REORDER 0x00cf /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_STREAM_OUTPUT_ILLEGAL_WITH_SM3_REORDER 0x00d0 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_SM3_REORDER_WITHOUT_PIXEL_SHADER 0x00d1 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET0_LAYER_OFFSET_VS_THIRD_DIMENSION 0x00d2 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET1_LAYER_OFFSET_VS_THIRD_DIMENSION 0x00d3 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET2_LAYER_OFFSET_VS_THIRD_DIMENSION 0x00d4 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET3_LAYER_OFFSET_VS_THIRD_DIMENSION 0x00d5 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET4_LAYER_OFFSET_VS_THIRD_DIMENSION 0x00d6 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET5_LAYER_OFFSET_VS_THIRD_DIMENSION 0x00d7 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET6_LAYER_OFFSET_VS_THIRD_DIMENSION 0x00d8 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET7_LAYER_OFFSET_VS_THIRD_DIMENSION 0x00d9 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_ZT_LAYER_OFFSET_VS_THIRD_DIMENSION 0x00da /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_ZT_LAYER_OFFSET_VS_DEPTH_IS_ONE 0x00db /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR1 0x00f4 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR2 0x00f5 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR3 0x00f6 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR4 0x00f7 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR5 0x00f8 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR6 0x00f9 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR7 0x00fa /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR1_COLOR2 0x00fb /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR1_COLOR3 0x00fc /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR1_COLOR4 0x00fd /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR1_COLOR5 0x00fe /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR1_COLOR6 0x00ff /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR1_COLOR7 0x0100 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR2_COLOR3 0x0101 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR2_COLOR4 0x0102 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR2_COLOR5 0x0103 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR2_COLOR6 0x0104 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR2_COLOR7 0x0105 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR3_COLOR4 0x0106 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR3_COLOR5 0x0107 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR3_COLOR6 0x0108 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR3_COLOR7 0x0109 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR4_COLOR5 0x010a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR4_COLOR6 0x010b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR4_COLOR7 0x010c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR5_COLOR6 0x010d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR5_COLOR7 0x010e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR6_COLOR7 0x010f /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR0 0x0110 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR1 0x0111 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR2 0x0112 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR3 0x0113 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR4 0x0114 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR5 0x0115 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR6 0x0116 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR7 0x0117 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_MAX_PIXEL_WARP_REGISTERS 0x0118 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_DEPTH_TEST 0x0119 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_STENCIL_TEST 0x011a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_DEPTH_BOUNDS_TEST 0x011b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_BLEND_WITH_DUAL_SOURCE 0x011c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_TARGET_COUNT 0x011d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_TARGET0_NOT0 0x011e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_TIR 0x011f /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM16X_A_A 0x0120 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_RASTER_SAMPLES_MODE 0x0121 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_SAMPLES 0x0122 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION01 0x0123 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION02 0x0124 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION03 0x0125 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION04 0x0126 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION05 0x0127 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION06 0x0128 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION07 0x0129 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION08 0x012a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION09 0x012b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION10 0x012c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION11 0x012d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION12 0x012e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION13 0x012f /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION14 0x0130 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION15 0x0131 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_A_A_COMBINATION01 0x0132 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_A_A_COMBINATION02 0x0133 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_A_A_COMBINATION03 0x0134 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_CLIPPING_COMBINATION01 0x0135 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_CLIPPING_COMBINATION02 0x0136 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_EARLY_Z_COMBINATION01 0x0137 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_A_A_COMBINATION04 0x0138 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_A_A_COMBINATION05 0x0139 /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_A_A_COMBINATION06 0x013a /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_C2_C 0x013b /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONSTANT_COLOR_RENDERING_WITHOUT_PRE_PS_COVERAGE 0x013c /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_VPRS_COMBINATION 0x013d /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_OTHER 0x013e /* R---V */ #define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_CONSERVATIVE_RASTER 0x013f /* R---V */ #define NV_PGRAPH_NONSTALL_INTR_EN 0x00400124 /* RWE4R */ #define NV_PGRAPH_NONSTALL_INTR_EN_TRAP 1:1 /* RWEVF */ #define NV_PGRAPH_NONSTALL_INTR_EN_TRAP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_NONSTALL_INTR_EN_TRAP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_NONSTALL_INTR_EN_TRAP__PROD 0x1 /* RW--V */ #define NV_PGRAPH_NONSTALL_INTR_EN_FE_DEBUG_INTR 2:2 /* RWEVF */ #define NV_PGRAPH_NONSTALL_INTR_EN_FE_DEBUG_INTR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_NONSTALL_INTR_EN_FE_DEBUG_INTR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_NONSTALL_INTR_EN_FE_DEBUG_INTR__PROD 0x1 /* RW--V */ #define NV_PGRAPH_GRFIFO_CONTROL 0x00400500 /* RWE4R */ #define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 /* RWEVF */ #define NV_PGRAPH_GRFIFO_CONTROL_ACCESS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_GRFIFO_CONTROL_ACCESS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_GRFIFO_CONTROL_ACCESS__PROD 0x1 /* RW--V */ #define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 /* RWEVF */ #define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS__PROD 0x1 /* RW--V */ #define NV_PGRAPH_GRFIFO_STATUS 0x00400504 /* R--4R */ #define NV_PGRAPH_GRFIFO_STATUS_EMPTY 0:0 /* R-IVF */ #define NV_PGRAPH_GRFIFO_STATUS_EMPTY_FALSE 0x0 /* R---V */ #define NV_PGRAPH_GRFIFO_STATUS_EMPTY_TRUE 0x1 /* R-I-V */ #define NV_PGRAPH_GRFIFO_STATUS_FULL 1:1 /* R-IVF */ #define NV_PGRAPH_GRFIFO_STATUS_FULL_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_GRFIFO_STATUS_FULL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_GRFIFO_STATUS_COUNT 13:8 /* R-IVF */ #define NV_PGRAPH_GRFIFO_STATUS_COUNT_0 0x00 /* R-I-V */ #define NV_PGRAPH_GRFIFO_STATUS_READ_PTR 20:16 /* R-IVF */ #define NV_PGRAPH_GRFIFO_STATUS_READ_PTR_0 0x00 /* R-I-V */ #define NV_PGRAPH_GRFIFO_STATUS_WRITE_PTR 28:24 /* R-IVF */ #define NV_PGRAPH_GRFIFO_STATUS_WRITE_PTR_0 0x00 /* R-I-V */ #define NV_PGRAPH_GRFIFO1_STATUS 0x00400508 /* R--4R */ #define NV_PGRAPH_GRFIFO1_STATUS_EMPTY 0:0 /* R-IVF */ #define NV_PGRAPH_GRFIFO1_STATUS_EMPTY_FALSE 0x0 /* R---V */ #define NV_PGRAPH_GRFIFO1_STATUS_EMPTY_TRUE 0x1 /* R-I-V */ #define NV_PGRAPH_GRFIFO1_STATUS_FULL 1:1 /* R-IVF */ #define NV_PGRAPH_GRFIFO1_STATUS_FULL_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_GRFIFO1_STATUS_FULL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_GRFIFO1_STATUS_COUNT 13:8 /* R-IVF */ #define NV_PGRAPH_GRFIFO1_STATUS_COUNT_0 0x00 /* R-I-V */ #define NV_PGRAPH_GRFIFO1_STATUS_READ_PTR 20:16 /* R-IVF */ #define NV_PGRAPH_GRFIFO1_STATUS_READ_PTR_0 0x00 /* R-I-V */ #define NV_PGRAPH_GRFIFO1_STATUS_WRITE_PTR 28:24 /* R-IVF */ #define NV_PGRAPH_GRFIFO1_STATUS_WRITE_PTR_0 0x00 /* R-I-V */ #define NV_PGRAPH_TRAPPED_ADDR 0x00400704 /* R--4R */ #define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 /* R-XVF */ #define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 /* R-XVF */ #define NV_PGRAPH_TRAPPED_ADDR_MME_GENERATED 20:20 /* R-XVF */ #define NV_PGRAPH_TRAPPED_ADDR_MME_GENERATED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_TRAPPED_ADDR_MME_GENERATED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_TRAPPED_ADDR_FEPIPE 22:22 /* R-XVF */ #define NV_PGRAPH_TRAPPED_ADDR_FEPIPE_FE0 0x0 /* R---V */ #define NV_PGRAPH_TRAPPED_ADDR_FEPIPE_FE1 0x1 /* R---V */ #define NV_PGRAPH_TRAPPED_ADDR_DATAHIGH 24:24 /* R-XVF */ #define NV_PGRAPH_TRAPPED_ADDR_DATAHIGH_INVALID 0x0 /* R---V */ #define NV_PGRAPH_TRAPPED_ADDR_DATAHIGH_VALID 0x1 /* R---V */ #define NV_PGRAPH_TRAPPED_ADDR_PRIV 28:28 /* R-XUF */ #define NV_PGRAPH_TRAPPED_ADDR_PRIV_DISABLED 0x0 /* R---V */ #define NV_PGRAPH_TRAPPED_ADDR_PRIV_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_TRAPPED_ADDR_STATUS 31:31 /* R-XVF */ #define NV_PGRAPH_TRAPPED_ADDR_STATUS_INVALID 0x1 /* R---V */ #define NV_PGRAPH_TRAPPED_ADDR_STATUS_VALID 0x0 /* R---V */ #define NV_PGRAPH_TRAPPED_DATA_LOW 0x00400708 /* R--4R */ #define NV_PGRAPH_TRAPPED_DATA_LOW_VALUE 31:0 /* R-XVF */ #define NV_PGRAPH_TRAPPED_DATA_HIGH 0x0040070c /* R--4R */ #define NV_PGRAPH_TRAPPED_DATA_HIGH_VALUE 31:0 /* R-XVF */ #define NV_PGRAPH_TRAPPED_DATA_MME 0x00400710 /* R--4R */ #define NV_PGRAPH_TRAPPED_DATA_MME_PC 11:0 /* R-XVF */ #define NV_PGRAPH_TRAPPED_DATA_MME_MACRO_ADDRESS 19:12 /* R-XVF */ #define NV_PGRAPH_TRAPPED_ADDR_EX 0x00400714 /* R--4R */ #define NV_PGRAPH_TRAPPED_ADDR_EX_VEID 29:24 /* R-XVF */ #define NV_PGRAPH_TRAPPED_ADDR_EX_VEID_INIT 0x00 /* R---V */ #define NV_PGRAPH_STATUS 0x00400700 /* R--4R */ #define NV_PGRAPH_STATUS_STATE 0:0 /* R-IVF */ #define NV_PGRAPH_STATUS_STATE_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_STATE_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 /* R-IVF */ #define NV_PGRAPH_STATUS_FE_METHOD_UPPER_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_FE_METHOD_UPPER_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 /* R-IVF */ #define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_FE_METHOD_LOWER_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_FE_FUNNEL 3:3 /* R-IVF */ #define NV_PGRAPH_STATUS_FE_FUNNEL_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_FE_FUNNEL_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_FE_NOTIFY 4:4 /* R-IVF */ #define NV_PGRAPH_STATUS_FE_NOTIFY_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_FE_NOTIFY_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_SEMAPHORE 5:5 /* R-IVF */ #define NV_PGRAPH_STATUS_SEMAPHORE_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_SEMAPHORE_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_MEMFMT 6:6 /* R-IVF */ #define NV_PGRAPH_STATUS_MEMFMT_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_MEMFMT_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_CONTEXT_SWITCH 7:7 /* R-IVF */ #define NV_PGRAPH_STATUS_CONTEXT_SWITCH_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_CONTEXT_SWITCH_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_PD 8:8 /* R-IVF */ #define NV_PGRAPH_STATUS_PD_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_PD_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_PDB 9:9 /* R-IVF */ #define NV_PGRAPH_STATUS_PDB_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_PDB_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_SCC 11:11 /* R-IVF */ #define NV_PGRAPH_STATUS_SCC_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_SCC_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_SSYNC 12:12 /* R-IVF */ #define NV_PGRAPH_STATUS_SSYNC_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_SSYNC_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_CWD 13:13 /* R-IVF */ #define NV_PGRAPH_STATUS_CWD_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_CWD_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_RASTWOD 14:14 /* R-IVF */ #define NV_PGRAPH_STATUS_RASTWOD_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_RASTWOD_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_SMCARB 15:15 /* R-IVF */ #define NV_PGRAPH_STATUS_SMCARB_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_SMCARB_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_FB 17:17 /* R-IVF */ #define NV_PGRAPH_STATUS_FB_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_FB_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_SKED 18:18 /* R-IVF */ #define NV_PGRAPH_STATUS_SKED_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_SKED_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_FE_CONST 19:19 /* R-IVF */ #define NV_PGRAPH_STATUS_FE_CONST_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_FE_CONST_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_FE_GI 21:21 /* R-IVF */ #define NV_PGRAPH_STATUS_FE_GI_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_FE_GI_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_TPC_MGR 22:22 /* R-IVF */ #define NV_PGRAPH_STATUS_TPC_MGR_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_TPC_MGR_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_GPC 24:24 /* R-IVF */ #define NV_PGRAPH_STATUS_GPC_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_GPC_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_FE_METHOD_UPPER_FE1 26:26 /* R-IVF */ #define NV_PGRAPH_STATUS_FE_METHOD_UPPER_FE1_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_FE_METHOD_UPPER_FE1_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_FE_NOTIFY_FE1 27:27 /* R-IVF */ #define NV_PGRAPH_STATUS_FE_NOTIFY_FE1_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_STATUS_FE_NOTIFY_FE1_BUSY 0x1 /* R---V */ #define NV_PGRAPH_STATUS_MASK 0x00400610 /* RWE4R */ #define NV_PGRAPH_STATUS_MASK_PD 8:8 /* RWEVF */ #define NV_PGRAPH_STATUS_MASK_PD_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_STATUS_MASK_PD_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_STATUS_MASK_PDB 9:9 /* RWEVF */ #define NV_PGRAPH_STATUS_MASK_PDB_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_STATUS_MASK_PDB_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_STATUS_MASK_SCC 11:11 /* RWEVF */ #define NV_PGRAPH_STATUS_MASK_SCC_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_STATUS_MASK_SCC_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_STATUS_MASK_SSYNC 12:12 /* RWEVF */ #define NV_PGRAPH_STATUS_MASK_SSYNC_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_STATUS_MASK_SSYNC_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_STATUS_MASK_RASTWOD 14:14 /* RWEVF */ #define NV_PGRAPH_STATUS_MASK_RASTWOD_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_STATUS_MASK_RASTWOD_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_STATUS_MASK_SMCARB 15:15 /* RWEVF */ #define NV_PGRAPH_STATUS_MASK_SMCARB_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_STATUS_MASK_SMCARB_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_STATUS_MASK_FB 17:17 /* RWEVF */ #define NV_PGRAPH_STATUS_MASK_FB_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_STATUS_MASK_FB_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_STATUS_MASK_BE 25:25 /* RWEVF */ #define NV_PGRAPH_STATUS_MASK_BE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_STATUS_MASK_BE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_ENGINE_CONFIG 0x00400614 /* RW-4R */ #define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_3D 0:0 /* RWXUF */ #define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_3D_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_3D_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_COMPUTE 1:1 /* RWXUF */ #define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_COMPUTE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_COMPUTE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_I2M 2:2 /* RWXUF */ #define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_I2M_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_I2M_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_2D 3:3 /* RWXUF */ #define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_2D_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_2D_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_STATUS1 0x00400604 /* R--4R */ #define NV_PGRAPH_STATUS1_GPC 31:0 /* R-IVF */ #define NV_PGRAPH_STATUS1_GPC_IDLE 0x00000000 /* R-I-V */ #define NV_PGRAPH_STATUS1_GPC_0_IDLE 0x00000000 /* R---V */ #define NV_PGRAPH_STATUS1_GPC_0_BUSY 0x00000001 /* R---V */ #define NV_PGRAPH_ENGINE_STATUS 0x0040060c /* R--4R */ #define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 /* R-IVF */ #define NV_PGRAPH_ENGINE_STATUS_VALUE_IDLE 0x0 /* R-I-V */ #define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY0 0x00400380 /* R--4R */ #define NV_PGRAPH_ACTIVITY0_PD 2:0 /* R-IVF */ #define NV_PGRAPH_ACTIVITY0_PD_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY0_PD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PD_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PD_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PD_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PD_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PD_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PD_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PDB 5:3 /* R-IVF */ #define NV_PGRAPH_ACTIVITY0_PDB_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY0_PDB_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PDB_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PDB_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PDB_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PDB_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PDB_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY0_PDB_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SCC 8:6 /* R-IVF */ #define NV_PGRAPH_ACTIVITY0_SCC_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY0_SCC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SCC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SCC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SCC_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SCC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SCC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SCC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY0_RASTWOD 11:9 /* R-IVF */ #define NV_PGRAPH_ACTIVITY0_RASTWOD_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY0_RASTWOD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY0_RASTWOD_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY0_RASTWOD_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY0_RASTWOD_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY0_RASTWOD_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY0_RASTWOD_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY0_RASTWOD_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SSYNC 14:12 /* R-IVF */ #define NV_PGRAPH_ACTIVITY0_SSYNC_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY0_SSYNC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SSYNC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SSYNC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SSYNC_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SSYNC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SSYNC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SSYNC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY0_CWD 17:15 /* R-IVF */ #define NV_PGRAPH_ACTIVITY0_CWD_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY0_CWD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY0_CWD_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY0_CWD_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY0_CWD_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY0_CWD_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY0_CWD_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY0_CWD_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SKED 20:18 /* R-IVF */ #define NV_PGRAPH_ACTIVITY0_SKED_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY0_SKED_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SKED_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SKED_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SKED_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SKED_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SKED_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SKED_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SMCARB 23:21 /* R-IVF */ #define NV_PGRAPH_ACTIVITY0_SMCARB_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY0_SMCARB_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SMCARB_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SMCARB_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SMCARB_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SMCARB_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SMCARB_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY0_SMCARB_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY1 0x00400384 /* R--4R */ #define NV_PGRAPH_ACTIVITY1_MEMFMT 8:6 /* R-IVF */ #define NV_PGRAPH_ACTIVITY1_MEMFMT_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY1_MEMFMT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY1_MEMFMT_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY1_MEMFMT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY1_MEMFMT_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY1_MEMFMT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY1_MEMFMT_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY1_MEMFMT_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY1_SEMAPHORE 11:9 /* R-IVF */ #define NV_PGRAPH_ACTIVITY1_SEMAPHORE_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY1_SEMAPHORE_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY1_SEMAPHORE_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY1_SEMAPHORE_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY1_SEMAPHORE_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY1_SEMAPHORE_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY1_SEMAPHORE_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY1_SEMAPHORE_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FUNNEL 14:12 /* R-IVF */ #define NV_PGRAPH_ACTIVITY1_FUNNEL_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY1_FUNNEL_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FUNNEL_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FUNNEL_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FUNNEL_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FUNNEL_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FUNNEL_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FUNNEL_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FECONST 17:15 /* R-IVF */ #define NV_PGRAPH_ACTIVITY1_FECONST_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY1_FECONST_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FECONST_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FECONST_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FECONST_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FECONST_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FECONST_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY1_FECONST_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY1_TPCMGR 20:18 /* R-IVF */ #define NV_PGRAPH_ACTIVITY1_TPCMGR_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY1_TPCMGR_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY1_TPCMGR_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY1_TPCMGR_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY1_TPCMGR_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY1_TPCMGR_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY1_TPCMGR_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY1_TPCMGR_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY2 0x00400388 /* R--4R */ #define NV_PGRAPH_ACTIVITY2_BE0 2:0 /* R-IVF */ #define NV_PGRAPH_ACTIVITY2_BE0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY2_BE0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE1 5:3 /* R-IVF */ #define NV_PGRAPH_ACTIVITY2_BE1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY2_BE1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE2 8:6 /* R-IVF */ #define NV_PGRAPH_ACTIVITY2_BE2_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY2_BE2_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE2_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE2_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE2_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE2_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE2_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE2_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE3 11:9 /* R-IVF */ #define NV_PGRAPH_ACTIVITY2_BE3_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY2_BE3_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE3_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE3_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE3_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE3_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE3_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE3_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE4 14:12 /* R-IVF */ #define NV_PGRAPH_ACTIVITY2_BE4_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY2_BE4_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE4_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE4_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE4_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE4_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE4_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE4_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE5 17:15 /* R-IVF */ #define NV_PGRAPH_ACTIVITY2_BE5_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY2_BE5_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE5_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE5_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE5_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE5_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE5_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE5_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE6 20:18 /* R-IVF */ #define NV_PGRAPH_ACTIVITY2_BE6_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY2_BE6_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE6_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE6_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE6_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE6_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE6_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE6_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE7 23:21 /* R-IVF */ #define NV_PGRAPH_ACTIVITY2_BE7_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY2_BE7_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE7_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE7_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE7_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE7_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE7_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY2_BE7_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY3 0x0040038c /* R--4R */ #define NV_PGRAPH_ACTIVITY3_BE8 2:0 /* R-IVF */ #define NV_PGRAPH_ACTIVITY3_BE8_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY3_BE8_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE8_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE8_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE8_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE8_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE8_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE8_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE9 5:3 /* R-IVF */ #define NV_PGRAPH_ACTIVITY3_BE9_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY3_BE9_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE9_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE9_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE9_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE9_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE9_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE9_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE10 8:6 /* R-IVF */ #define NV_PGRAPH_ACTIVITY3_BE10_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY3_BE10_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE10_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE10_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE10_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE10_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE10_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE10_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE11 11:9 /* R-IVF */ #define NV_PGRAPH_ACTIVITY3_BE11_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY3_BE11_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE11_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE11_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE11_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE11_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE11_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE11_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE12 14:12 /* R-IVF */ #define NV_PGRAPH_ACTIVITY3_BE12_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY3_BE12_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE12_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE12_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE12_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE12_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE12_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE12_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE13 17:15 /* R-IVF */ #define NV_PGRAPH_ACTIVITY3_BE13_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY3_BE13_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE13_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE13_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE13_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE13_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE13_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY3_BE13_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY4 0x00400390 /* R--4R */ #define NV_PGRAPH_ACTIVITY4_GPC0 2:0 /* R-IVF */ #define NV_PGRAPH_ACTIVITY4_GPC0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY4_GPC0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC1 5:3 /* R-IVF */ #define NV_PGRAPH_ACTIVITY4_GPC1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY4_GPC1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC2 8:6 /* R-IVF */ #define NV_PGRAPH_ACTIVITY4_GPC2_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY4_GPC2_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC2_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC2_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC2_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC2_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC2_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC2_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC3 11:9 /* R-IVF */ #define NV_PGRAPH_ACTIVITY4_GPC3_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY4_GPC3_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC3_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC3_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC3_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC3_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC3_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC3_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC4 14:12 /* R-IVF */ #define NV_PGRAPH_ACTIVITY4_GPC4_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY4_GPC4_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC4_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC4_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC4_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC4_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC4_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC4_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC5 17:15 /* R-IVF */ #define NV_PGRAPH_ACTIVITY4_GPC5_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY4_GPC5_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC5_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC5_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC5_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC5_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC5_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC5_HALTED 0x7 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC6 20:18 /* R-IVF */ #define NV_PGRAPH_ACTIVITY4_GPC6_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_ACTIVITY4_GPC6_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC6_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC6_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC6_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC6_STALLED 0x5 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC6_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_ACTIVITY4_GPC6_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK 0x004001fc /* RWE4R */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x00400200 /* RWE4R */ #define NV_PGRAPH_PIPE_BUNDLE_ADDRESS__PRIV_LEVEL_MASK 0x004001fc /* */ #define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_BROADCAST 16:16 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_BROADCAST_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VEID 25:20 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VEID_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_DATA 0x00400204 /* RWE4R */ #define NV_PGRAPH_PIPE_BUNDLE_DATA__PRIV_LEVEL_MASK 0x004001fc /* */ #define NV_PGRAPH_PIPE_BUNDLE_DATA_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_DATA_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_DATA_HI 0x0040020c /* RWE4R */ #define NV_PGRAPH_PIPE_BUNDLE_DATA_HI__PRIV_LEVEL_MASK 0x004001fc /* */ #define NV_PGRAPH_PIPE_BUNDLE_DATA_HI_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_DATA_HI_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x00400208 /* RWE4R */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG__PRIV_LEVEL_MASK 0x004001fc /* */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_DUMMY 0x00400208 #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE 3:0 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE_DUMMY 3:0 #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE_NONE 0x0 /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE_MEM_TO_MEMFMT 0x1 /* RW--V */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE_TWOD 0x2 /* RW--V */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE_THREED 0x4 /* RW--V */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE_COMPUTE 0x8 /* RW--V */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_CURRENT_OBJECT_MAJOR_MODE 7:4 /* R-EVF */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_CURRENT_OBJECT_MAJOR_MODE_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_CURRENT_OBJECT_MAJOR_MODE_MEM_TO_MEMFMT 0x1 /* R---V */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_CURRENT_OBJECT_MAJOR_MODE_TWOD 0x2 /* R---V */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_CURRENT_OBJECT_MAJOR_MODE_THREED 0x4 /* R---V */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_CURRENT_OBJECT_MAJOR_MODE_COMPUTE 0x8 /* R---V */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 /* RWEVF */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_HWW_ESR 0x00404000 /* RWE4R */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INJECTED_BUNDLE_ERROR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INJECTED_BUNDLE_ERROR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INJECTED_BUNDLE_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_CLASS_SUBCH_MISMATCH 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_CLASS_SUBCH_MISMATCH_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_CLASS_SUBCH_MISMATCH_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_SPECULATIVE_GO_IDLE 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_SPECULATIVE_GO_IDLE_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_SPECULATIVE_GO_IDLE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_ILLEGAL_FE_ATOMIC_SEQ 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_ILLEGAL_FE_ATOMIC_SEQ_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_ILLEGAL_FE_ATOMIC_SEQ_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_ILLEGAL_SMC_MEM_PARTITIONING 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_ILLEGAL_SMC_MEM_PARTITIONING_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_ILLEGAL_SMC_MEM_PARTITIONING_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_CLASS_VEID_MISMATCH 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_CLASS_VEID_MISMATCH_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_CLASS_VEID_MISMATCH_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_V_0 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO 0x004041b0 /* R--4R */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_CLASS 15:0 /* R-EVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_CLASS_0 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_SUBCH 18:16 /* R-EVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_SUBCH_0 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_SUBCH_1 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_FEPIPE 19:19 /* R-EVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_FEPIPE_FE0 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_FEPIPE_FE1 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_ILLEGAL_FE_ATOMIC_SEQ_FEPIPE 21:21 /* R-EVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_ILLEGAL_FE_ATOMIC_SEQ_FEPIPE_FE0 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_ILLEGAL_FE_ATOMIC_SEQ_FEPIPE_FE1 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_VEID 29:24 /* R-EVF */ #define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_VEID_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK 0x004041ec /* RWE4R */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWE-V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE(i) (0x0040a600+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_MTHD 11:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_SUBCH 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_SUBCH_3D 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_SUBCH_COMPUTE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_SUBCH_I2M 0x2 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_SUBCH_2D 0x3 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FSM 20:16 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FORCE_SUBCHSW 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FORCE_SUBCHSW_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FORCE_SUBCHSW_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_IS_INTERNAL_MTHD 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_IS_INTERNAL_MTHD_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_IS_INTERNAL_MTHD_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_VEID 28:23 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_VALID 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_VALID_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_VALID_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1(i) (0x0040a610+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_MTHD 11:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_SUBCH 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_SUBCH_3D 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_SUBCH_COMPUTE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_SUBCH_I2M 0x2 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_SUBCH_2D 0x3 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_FSM 20:16 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_FORCE_SUBCHSW 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_FORCE_SUBCHSW_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_FORCE_SUBCHSW_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_IS_INTERNAL_MTHD 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_IS_INTERNAL_MTHD_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_IS_INTERNAL_MTHD_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_VEID 28:23 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_VALID 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_VALID_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SETOBJ_STATE_FE1_VALID_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_DECODE_STATE(i) (0x0040a620+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_DECODE_STATE__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_MTHD 11:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_FSM 20:16 /* R-XVF */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_VALID 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_VALID_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_VALID_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_EX(i) (0x0040a630+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_EX__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_EX_MME_PC 11:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_EX_MME_MACRO_ADDR 21:12 /* R-XVF */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_EX_MME_GENERATED 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_EX_MME_GENERATED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_EX_MME_GENERATED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_DATA(i) (0x0040a640+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_DATA__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_DATA_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_FE1(i) (0x0040a650+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_FE1__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_FE1_MTHD 11:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_FE1_FSM 20:16 /* R-XVF */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_FE1_VALID 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_FE1_VALID_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_FE1_VALID_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_DATA_FE1(i) (0x0040a660+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_DATA_FE1__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FE_DECODE_STATE_DATA_FE1_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_0 0x00404014 /* RWI4R */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_0_ADDR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_0_ADDR_NONE 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_0_AMASK 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_0_AMASK_EMPTY 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_1 0x00404018 /* RWI4R */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_1_ADDR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_1_ADDR_NONE 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_1_AMASK 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_1_AMASK_EMPTY 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_2 0x0040401c /* RWI4R */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_2_ADDR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_2_ADDR_NONE 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_2_AMASK 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_2_AMASK_EMPTY 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_3 0x00404020 /* RWI4R */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_3_ADDR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_3_ADDR_NONE 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_3_AMASK 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_FE_BUNDLE_BROADCAST_3_AMASK_EMPTY 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_CHIP_DEF_INFO 0x00404030 /* C--4R */ #define NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT 11:0 /* C--UF */ #define NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT_INIT 0x040 /* C---V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_THREED 0x004040a8 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_THREED_V 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_THREED_V_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_THREED 0x004040ac /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_THREED_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_THREED_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_TWOD 0x004040b0 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_TWOD_V 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_TWOD_V_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_TWOD 0x004040b4 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_TWOD_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_TWOD_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_M2M 0x004040b8 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_M2M_V 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_M2M_V_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_M2M 0x004040bc /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_M2M_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_M2M_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_GLOBAL 0x004040c0 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_GLOBAL_V 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_GLOBAL_V_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_GLOBAL 0x004040c4 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_GLOBAL_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_GLOBAL_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE 0x004040c8 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_THREED 0:0 /* R-IVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_THREED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_THREED_TRUE 0x1 /* R-I-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_TWOD 1:1 /* R-IVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_TWOD_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_TWOD_TRUE 0x1 /* R-I-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_M2M 2:2 /* R-IVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_M2M_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_M2M_TRUE 0x1 /* R-I-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_STATE 6:4 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_STATE_IDLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_STATE_REQ 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_STATE_RESP 0x4 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_STATE_REPORT 0x5 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_STATE_REQ_2 0x6 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_CONDITIONAL_LCB 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_CONDITIONAL_LCB_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_CONDITIONAL_LCB_TRUE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OVERRIDE_THREED 21:20 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OVERRIDE_THREED_USE_RENDER_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OVERRIDE_THREED_ALWAYS_RENDER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OVERRIDE_THREED_NEVER_RENDER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OVERRIDE_TWOD 23:22 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OVERRIDE_TWOD_USE_RENDER_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OVERRIDE_TWOD_ALWAYS_RENDER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OVERRIDE_TWOD_NEVER_RENDER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OVERRIDE_M2M 25:24 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OVERRIDE_M2M_USE_RENDER_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OVERRIDE_M2M_ALWAYS_RENDER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OVERRIDE_M2M_NEVER_RENDER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_PARTIAL_THREED 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_PARTIAL_THREED_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_PARTIAL_THREED_TRUE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_PARTIAL_TWOD 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_PARTIAL_TWOD_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_PARTIAL_TWOD_TRUE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_PARTIAL_M2M 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_PARTIAL_M2M_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_PARTIAL_M2M_TRUE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_PARTIAL_GLOBAL 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_PARTIAL_GLOBAL_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_PARTIAL_GLOBAL_TRUE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_THREED 0x004040d0 /* RWI4R */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_THREED_V 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_THREED_V_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_THREED 0x004040d4 /* RWI4R */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_THREED_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_THREED_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_TWOD 0x004040d8 /* RWI4R */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_TWOD_V 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_TWOD_V_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_TWOD 0x004040dc /* RWI4R */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_TWOD_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_TWOD_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_M2M 0x004040e0 /* RWI4R */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_M2M_V 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_M2M_V_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_M2M 0x004040e4 /* RWI4R */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_M2M_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_M2M_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0 0x00404130 /* RWE4R */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0__PRIV_LEVEL_MASK 0x004041ec /* */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_ADDR 13:2 /* RWEVF */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_ADDR_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_THREED 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_THREED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_THREED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_TWOD 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_TWOD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_TWOD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_COMPUTE 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_COMPUTE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_COMPUTE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_MEMFMT 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_MEMFMT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_0_MEMFMT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1 0x00404134 /* RWE4R */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1__PRIV_LEVEL_MASK 0x004041ec /* */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_ADDR 13:2 /* RWEVF */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_ADDR_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_THREED 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_THREED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_THREED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_TWOD 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_TWOD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_TWOD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_COMPUTE 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_COMPUTE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_COMPUTE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_MEMFMT 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_MEMFMT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_DEBUG_METHOD_1_MEMFMT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE 0x00404138 /* RWI4R */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE0_FROM_CE_TO_COMPUTE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE0_FROM_CE_TO_COMPUTE_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE0_FROM_CE_TO_COMPUTE_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE0_FROM_THREED_TO_COMPUTE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE0_FROM_THREED_TO_COMPUTE_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE0_FROM_THREED_TO_COMPUTE_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE0_FROM_CE_TO_THREED 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE0_FROM_CE_TO_THREED_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE0_FROM_CE_TO_THREED_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE0_FROM_COMPUTE_TO_THREED 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE0_FROM_COMPUTE_TO_THREED_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE0_FROM_COMPUTE_TO_THREED_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE1_FROM_CE_TO_COMPUTE 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE1_FROM_CE_TO_COMPUTE_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_FE1_FROM_CE_TO_COMPUTE_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SHADER_CACHES_INSTR 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SHADER_CACHES_INSTR_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SHADER_CACHES_INSTR_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SHADER_CACHES_DATA 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SHADER_CACHES_DATA_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SHADER_CACHES_DATA_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SHADER_CACHES_CONSTANT 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SHADER_CACHES_CONSTANT_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SHADER_CACHES_CONSTANT_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SHADER_CACHES_LOCKS 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SHADER_CACHES_LOCKS_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SHADER_CACHES_LOCKS_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SAMPLER_CACHE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SAMPLER_CACHE_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_SAMPLER_CACHE_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_TEXTURE_HEADER_CACHE 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_TEXTURE_HEADER_CACHE_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_TEXTURE_HEADER_CACHE_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_RASTER_CACHE 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_RASTER_CACHE_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_RASTER_CACHE_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_ROP_MINI_CACHE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_ROP_MINI_CACHE_DISABLED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_SUBCHSW_OVERRIDE_INV_ROP_MINI_CACHE_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_A 0x0040413c /* R--4R */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_A_OFFSET_UPPER 7:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_B 0x00404140 /* R--4R */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_B_OFFSET_LOWER 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_C 0x00404144 /* R--4R */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_C_PAYLOAD 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D 0x00404148 /* R--4R */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_OPERATION 1:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_OPERATION_RELEASE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_OPERATION_REPORT_ONLY 0x2 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_OPERATION_TRAP 0x3 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_TRAP_TYPE 3:2 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_TRAP_TYPE_TRAP_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_TRAP_TYPE_TRAP_UNCONDITIONAL 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_TRAP_TYPE_TRAP_CONDITIONAL 0x2 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x3 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION 7:4 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_WORLD 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_WORLD_ALPHA 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_WORLD_BETA 0x2 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_CWD 0x3 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_SCREEN 0x4 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_FE 0x5 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_SCREEN_CROP 0x6 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PAYLOAD_SIZE64 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PAYLOAD_SIZE64_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PAYLOAD_SIZE64_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_AWAKEN_ENABLE 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_AWAKEN_ENABLE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_AWAKEN_ENABLE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT 14:10 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_NONE 0x00 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_DA_VERTICES_GENERATED 0x01 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ZPASS_PIXEL_CNT 0x02 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_DA_PRIMITIVES_GENERATED 0x03 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ALPHA_BETA_CLOCKS 0x04 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_VS_INVOCATIONS 0x05 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MIN_SUCC 0x06 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_GS_INVOCATIONS 0x07 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_GS_PRIMITIVES_GENERATED 0x09 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ZCULL_STATS0 0x0a /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0b /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ZCULL_STATS1 0x0c /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0d /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ZCULL_STATS2 0x0e /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_CLIPPER_INVOCATIONS 0x0f /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ZCULL_STATS3 0x10 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x11 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_VTG_PRIMITIVES_OUT 0x12 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_PS_INVOCATIONS 0x13 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_TIMESTAMP 0x14 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ZPASS_PIXEL_CNT64 0x15 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x18 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x19 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_STREAMING_BYTE_COUNT 0x1a /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_TI_INVOCATIONS 0x1b /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_TS_INVOCATIONS 0x1d /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_TOTAL_STREAMING_PRIMS_NEEDED_MIN_SUCC 0x1e /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_TS_PRIMITIVES_GENERATED 0x1f /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_SUB_REPORT 18:16 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_FLUSH_DISABLE 19:19 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_FLUSH_DISABLE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_FLUSH_DISABLE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_SIZE 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_SIZE_FOUR_BYTES 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_SIZE_EIGHT_BYTES 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_DWORD_NUM 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_DWORD_NUM_LOWER 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_DWORD_NUM_UPPER 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_STRUCTURE_SIZE 23:22 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_STRUCTURE_SIZE_FOUR_WORDS 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_STRUCTURE_SIZE_ONE_WORD 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_STRUCTURE_SIZE_TWO_WORD 0x2 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_VEID 29:24 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_VEID_0 0x00 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_REPORT 0x0040414c /* R--4R */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_REPORT_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x00404154 /* RWI4R */ #define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT_INIT 0x7fffffff /* RWI-V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT__PROD 0x00001800 /* RW--V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT_DISABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_FE_COMPUTE_GO_IDLE_TIMEOUT 0x00404160 /* RWI4R */ #define NV_PGRAPH_PRI_FE_COMPUTE_GO_IDLE_TIMEOUT_COUNT 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_COMPUTE_GO_IDLE_TIMEOUT_COUNT_INIT 0x00000040 /* RWI-V */ #define NV_PGRAPH_PRI_FE_COMPUTE_GO_IDLE_TIMEOUT_COUNT_DISABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON 0x0040415c /* RWE4R */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_EMITTER_IF 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_BUNDLE_IF 0x01 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_INTR 0x02 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE2FB 0x03 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MEMFMT_RD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MEMFMT_WR 0x05 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MME_CPU 0x06 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA 0x07 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE_ACTIVITY 0x08 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_PM_TRIGGER 0x09 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_BLG_STATUS 0x0a /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MEMFMT_BUF 0x0b /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_COAL1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_FPW_PREEMPT_ACK 0x0d /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_8_FPW_PREEMPT_ACK 0x0e /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_16_FPW_PREEMPT_ACK 0x0f /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_24_FPW_PREEMPT_ACK 0x10 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MIW_1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MIW_2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SKED_1 0x13 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_CONST 0x14 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_DECODE 0x15 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MEMFMT_ACK 0x16 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_SEMA_0 0x17 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_MISC_0 0x18 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_MISC_1 0x19 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SUBUNIT_STATUS_0 0x1a /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SUBUNIT_STATUS_1 0x1b /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SUBUNIT_STATUS_2 0x1c /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SETOBJ 0x1d /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE_METHOD_PIPE 0x1e /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_TPCM 0x1f /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_TPCM_GFX_BUNDLES 0x20 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_PIPE_STATE 0x21 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_WRACK 0x22 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_FPW_WFI_ACK 0x23 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_8_FPW_WFI_ACK 0x24 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_16_FPW_WFI_ACK 0x25 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_24_FPW_WFI_ACK 0x26 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_GR_TPCS 0x27 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA2 0x28 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_SEMA_1 0x29 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_CTXSW_0 0x2a /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_CTXSW_1 0x2b /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_PREEMPT 0x2c /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_PREEMPT_RESTORE 0x2d /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_STATIC_PATTERN_0X55_8_GROUP 0x2e /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_STATIC_PATTERN_0XAA_8_GROUP 0x2f /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_CTXSW_2 0x30 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_CTXSW_3 0x31 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_CTXSW_4 0x32 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_GPM_FPW_PREEMPT_ACK 0x33 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_GPM_8_FPW_PREEMPT_ACK 0x34 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_CTXSW_5 0x35 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_TPCM_LATENCY 0x36 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MME_SHADOW 0x37 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MERGE_FSM_0 0x38 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MERGE_FSM_1 0x39 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_FSM_MISC 0x3a /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_SETOBJ 0x3b /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_DECODE 0x3c /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_DECODE_FSM 0x3d /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_NOTIFY_FSM 0x3e /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_EMIT_PGI_FSM 0x3f /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_TFQ_FSM 0x40 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_TPCM_PACKETS 0x41 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MERGE 0x42 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MERGE_FE0_STALL 0x43 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MERGE_FE1_STALL 0x44 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE0_WFI_PENDING 0x45 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_WFI_PENDING 0x46 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE_WFI_PENDING 0x47 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_GFX_WFI_PENDING_0 0x48 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_COMP_WFI_PENDING_0 0x49 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MME_CPU_DATA 0x4a /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MME_CPU_STALL 0x4b /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MME_CPU_FLUSH 0x4c /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MME_CPU_BRANCH 0x4d /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_WFI_PENDING_0 0x4e /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_WFI_PENDING_1 0x4f /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_COMP_VEID_GOIDLE_PENDING 0x50 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_GOIDLE_PENDING 0x51 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_GOIDLE_MISC_0 0x52 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_GOIDLE_MISC_1 0x53 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_EMIT_GOIDLE 0x54 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_EMIT_GOIDLE_PRI 0x55 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_EMIT_GOIDLE_FE0 0x56 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_EMIT_GOIDLE_FE1 0x57 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_BUNDLE64_DECODE_FE0 0x58 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_BUNDLE64_DECODE_FE1 0x59 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_BUNDLE64_EMIT 0x5a /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_I2M_INLINE_HISTO 0x5b /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_HOST_HISTO 0x5c /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_EMIT_GOIDLE_TPCM 0x5d /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_EMIT_GOIDLE_FECSIF 0x5e /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_EMIT_GOIDLE_FECSIF2 0x5f /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_EMIT_GOIDLE_INTR 0x60 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_EMIT_GOIDLE_GFX_AUTOWFI 0x61 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FSM_EMIT_GOIDLE_COMP_AUTOWFI 0x62 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_RENDER_ENABLE 0x63 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_IDLE_AFTER_EMIT 0x64 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_VEID_GOIDLE_SENT 0x65 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_TPCM_COMP_BUNDLES 0x66 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_EMITTER2_IF 0x67 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_DECODE2 0x68 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SINGLEPASS_1 0x69 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SINGLEPASS_2 0x6a /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SINGLEPASS_3 0x6b /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SINGLEPASS_4 0x6c /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SINGLEPASS_GFX_SOL1 0x6d /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SINGLEPASS_GFX_SOL2 0x6e /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SINGLEPASS_SMC_SOL1 0x6f /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_DMA_METHODS_SERVICED 0x70 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_DMA_DRAM_READ_WRITE_WORDS 0x71 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_DMA_OUTSTANDING_RDAT 0x72 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_DMA_OUTSTANDING_WDAT 0x73 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_DMA_STALL 0x74 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_DMA_FIFOED 0x75 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_GPM_FPW_WFI_ACK 0x76 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_GPM_8_FPW_WFI_ACK 0x77 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SMC_MISC 0x78 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_MME_CPU 0x79 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_MME_SHADOW 0x7a /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_MME_CPU_DATA 0x7b /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_MME_CPU_STALL 0x7c /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_MME_CPU_FLUSH 0x7d /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_MME_CPU_BRANCH 0x7e /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_DMA_METHODS_SERVICED 0x7f /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_DMA_DRAM_READ_WRITE_WORDS 0x80 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_DMA_OUTSTANDING_RDAT 0x81 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_DMA_OUTSTANDING_WDAT 0x82 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_DMA_STALL 0x83 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_DMA_FIFOED 0x84 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_MME_MISC 0x85 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_MME_MISC 0x86 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SKIP_SUBCH_STIM 0x87 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_GPM_TRAILING 0x88 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_GPM_8_TRAILING 0x89 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_TRAILING 0x8a /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_8_TRAILING 0x8b /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_16_TRAILING 0x8c /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_24_TRAILING 0x8d /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_ROP_ACK_STATUS 0x8e /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA_RIG_LIMIT 0x8f /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_SEMA3 0x90 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_DMA_OUTSTANDING_ALL 0x91 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SEL_FE1_DMA_OUTSTANDING_ALL 0x92 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_TPCM_LATENCY_SEL 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PERFMON_TPCM_LATENCY_SEL_FDRAIN 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PERFMON_TPCM_LATENCY_SEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_TPCM_LATENCY_SEL_DISABLE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_TPCM_LATENCY_SEL_SDRAIN 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PERFMON_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2A 0x0040a270 /* RWE4R */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2A_SEL 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2A_SEL_EMITTER_IF 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2A_TPCM_LATENCY_SEL 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2A_TPCM_LATENCY_SEL_FDRAIN 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2A_TPCM_LATENCY_SEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2A_TPCM_LATENCY_SEL_DISABLE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2A_TPCM_LATENCY_SEL_SDRAIN 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2B 0x0040a274 /* RWE4R */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2B_SEL 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2B_SEL_EMITTER_IF 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2B_TPCM_LATENCY_SEL 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2B_TPCM_LATENCY_SEL_FDRAIN 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2B_TPCM_LATENCY_SEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2B_TPCM_LATENCY_SEL_DISABLE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_PERFMON_SYS2B_TPCM_LATENCY_SEL_SDRAIN 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY 0x00404164 /* RWI4R */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_RENDER_ENABLE 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_RENDER_ENABLE_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_RENDER_ENABLE_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_RENDER_ENABLE_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_NOTIFY 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_NOTIFY_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_NOTIFY_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_NOTIFY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_SEMA_RELEASE 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_SEMA_RELEASE_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_SEMA_RELEASE_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_SEMA_RELEASE_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_MME_DMA 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_MME_DMA_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_MME_DMA_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_MME_DMA_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_MME_FE1_DMA 11:10 /* RWIVF */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_MME_FE1_DMA_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_MME_FE1_DMA_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FE_L2_EVICT_POLICY_MME_FE1_DMA_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_FEATURE_CONFIG 0x00404168 /* RWE4R */ #define NV_PGRAPH_PRI_FE_FEATURE_CONFIG_SEMA_EARLY_ROP_SYNC 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_FEATURE_CONFIG_SEMA_EARLY_ROP_SYNC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_FEATURE_CONFIG_SEMA_EARLY_ROP_SYNC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX 0x0040416c /* R--4R */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_MSG_FB_SUBID 7:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_MSG_FB_SUBID_0 0x00 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_END_2D_OP 16:16 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_END_2D_OP_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_END_2D_OP_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_END_PM_TRIGGER_OP 17:17 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_END_PM_TRIGGER_OP_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_END_PM_TRIGGER_OP_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_REDUCTION_OP 22:20 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_REDUCTION_OP_0 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_REDUCTION_ENABLE 23:23 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_REDUCTION_ENABLE_DISABLED 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_REDUCTION_ENABLE_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_REDUCTION_FORMAT 24:24 /* R-XVF */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_REDUCTION_FORMAT_UNSIGNED 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_EX_REDUCTION_FORMAT_SIGNED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_PWR_MODE 0x00404170 /* RWE4R */ #define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_SLOW 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_POWER 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FE_MIW_STATUS 0x00404184 /* R--4R */ #define NV_PGRAPH_PRI_FE_MIW_STATUS_VALUE 2:0 /* R-EVF */ #define NV_PGRAPH_PRI_FE_MIW_STATUS_VALUE_EMPTY 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FE_MIW_STATUS_VALUE_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_MIW_STATUS_VALUE_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_FE_MIW_STATUS_VALUE_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_FE_MIW_STATUS_VALUE_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_FE_MIW_STATUS_VALUE_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_FE_MIW_STATUS_VALUE_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO 0x00404194 /* RWI4R */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_ROP_CNT 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_ROP_CNT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_MAX_GPM_ROP_CNT 11:8 /* RWIVF */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_MAX_GPM_ROP_CNT_INIT 0x7 /* RWI-V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_OUTSTANDING_GO_IDLE 13:12 /* R-IVF */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_OUTSTANDING_GO_IDLE_IS_NONE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_OUTSTANDING_GO_IDLE_IS_SINGLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_OUTSTANDING_GO_IDLE_IS_ALL 0x2 /* R---V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_CNT 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_CNT_MAX 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_CNT_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_I2M_CNT 20:20 /* R-IVF */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_I2M_CNT_MAX 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_I2M_CNT_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_GFX_LAST_EMITTER_IS_GO_IDLE 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_GFX_LAST_EMITTER_IS_GO_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_GFX_LAST_EMITTER_IS_GO_IDLE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_COMPUTE 0x004041a0 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_COMPUTE_V 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_COMPUTE_V_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_COMPUTE 0x004041a4 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_COMPUTE_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_COMPUTE_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_COMPUTE 0x004041a8 /* RWI4R */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_COMPUTE_V 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_COMPUTE_V_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_COMPUTE 0x004041ac /* RWI4R */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_COMPUTE_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_COMPUTE_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_PREEMPT 0x004041b4 /* RWE4R */ #define NV_PGRAPH_PRI_FE_PREEMPT_RESTORE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PREEMPT_RESTORE_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FE_PREEMPT_RESTORE_DONE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PREEMPT_CTXSW_TYPE_THREED_TYPE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PREEMPT_CTXSW_TYPE_THREED_TYPE_WFI 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PREEMPT_CTXSW_TYPE_THREED_TYPE_GFXP_PREEMPT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_PREEMPT_CTXSW_TYPE_COMPUTE_TYPE 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_FE_PREEMPT_CTXSW_TYPE_COMPUTE_TYPE_WFI 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_PREEMPT_CTXSW_TYPE_COMPUTE_TYPE_CTA_PREEMPT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_PREEMPT_CTXSW_TYPE_COMPUTE_TYPE_CILP_PREEMPT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FE_CTXSW_CONFIG 0x004041b8 /* RWE4R */ #define NV_PGRAPH_PRI_FE_CTXSW_CONFIG_THREED_TYPE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_CTXSW_CONFIG_THREED_TYPE_WFI 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_CTXSW_CONFIG_THREED_TYPE_PSEUDO_PREEMPT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_CTXSW_CONFIG_THREED_TYPE_GFXP_PREEMPT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_FE_CTXSW_CONFIG_COMPUTE_TYPE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_FE_CTXSW_CONFIG_COMPUTE_TYPE_WFI 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_CTXSW_CONFIG_COMPUTE_TYPE_CTA_PREEMPT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_CTXSW_CONFIG_COMPUTE_TYPE_CILP_PREEMPT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_FE_GFXP_TEST 0x004041bc /* RWE4R */ #define NV_PGRAPH_PRI_FE_GFXP_TEST_METHOD_COUNT 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_GFXP_TEST_METHOD_COUNT_DISABLED 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT 0x004041c0 /* RWI4R */ #define NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT_COUNT 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT_COUNT_DISABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_FE_INTERVAL_TIMER 0x004041c4 /* RWI4R */ #define NV_PGRAPH_PRI_FE_INTERVAL_TIMER_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_INTERVAL_TIMER_VALUE_DISABLED 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_MERGE_SWITCH 0x004041d0 /* RWI4R */ #define NV_PGRAPH_PRI_FE_MERGE_SWITCH_GFX_MTHD_COUNT 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_MERGE_SWITCH_GFX_MTHD_COUNT_INIT 0x0100 /* RWI-V */ #define NV_PGRAPH_PRI_FE_MERGE_SWITCH_GFX_MTHD_COUNT_DISABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_FE_MERGE_SWITCH_ACO_MTHD_COUNT 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_FE_MERGE_SWITCH_ACO_MTHD_COUNT_INIT 0x0100 /* RWI-V */ #define NV_PGRAPH_PRI_FE_MERGE_SWITCH_ACO_MTHD_COUNT_DISABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_FE_RIG_SYNC_INFO 0x00404220 /* R-I4R */ #define NV_PGRAPH_PRI_FE_RIG_SYNC_INFO_ISSUE_CNT 15:0 /* R-IVF */ #define NV_PGRAPH_PRI_FE_RIG_SYNC_INFO_ISSUE_CNT_INIT 0x0000 /* R-I-V */ #define NV_PGRAPH_PRI_FE_RIG_SYNC_WATERMARK 0x00404224 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RIG_SYNC_WATERMARK_CNT 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RIG_SYNC_WATERMARK_CNT_INIT 0xffdc /* RWI-V */ #define NV_PGRAPH_PRI_FE_RIG_REPORT_GPM_ACCUM_INFO 0x004042c0 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RIG_REPORT_GPM_ACCUM_INFO_ISSUE_CNT 9:0 /* R-IVF */ #define NV_PGRAPH_PRI_FE_RIG_REPORT_GPM_ACCUM_INFO_ISSUE_CNT_INIT 0x000 /* R-I-V */ #define NV_PGRAPH_PRI_FE_RIG_REPORT_GPM_ACCUM_INFO_WATERMARK 25:16 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RIG_REPORT_GPM_ACCUM_INFO_WATERMARK_INIT 0x0ff /* RWI-V */ #define NV_PGRAPH_PRI_FE_RIG_REPORT_ROP_ACCUM_INFO 0x004042c4 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RIG_REPORT_ROP_ACCUM_INFO_ISSUE_CNT 9:0 /* R-IVF */ #define NV_PGRAPH_PRI_FE_RIG_REPORT_ROP_ACCUM_INFO_ISSUE_CNT_INIT 0x000 /* R-I-V */ #define NV_PGRAPH_PRI_FE_RIG_REPORT_ROP_ACCUM_INFO_WATERMARK 25:16 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RIG_REPORT_ROP_ACCUM_INFO_WATERMARK_INIT 0x0ff /* RWI-V */ #define NV_PGRAPH_PRI_FE_GFX_DRAIN_FIFO 0x004041d8 /* RWI4R */ #define NV_PGRAPH_PRI_FE_GFX_DRAIN_FIFO_MERGE_WATERMARK 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_GFX_DRAIN_FIFO_MERGE_WATERMARK_INIT 0x048 /* RWI-V */ #define NV_PGRAPH_PRI_FE_GFX_DRAIN_FIFO_TOTAL_ENTRIES 17:9 /* RWIVF */ #define NV_PGRAPH_PRI_FE_GFX_DRAIN_FIFO_TOTAL_ENTRIES_MAX 0x0cc /* RWI-V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS 0x004041e0 /* RWE4R */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_SELECTED_FEPIPE 0:0 /* R--VF */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_SELECTED_FEPIPE_FE0 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_SELECTED_FEPIPE_FE1 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_SAFE_TO_SWITCH 1:1 /* R--VF */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_SAFE_TO_SWITCH_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_SAFE_TO_SWITCH_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_ATOMIC_SEQUENCE 2:2 /* R--VF */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_ATOMIC_SEQUENCE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_ATOMIC_SEQUENCE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_I2M 3:3 /* R--VF */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_I2M_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_I2M_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_ALLOW_SCG_SWITCH_ON_IDLE 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_ALLOW_SCG_SWITCH_ON_IDLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_ALLOW_SCG_SWITCH_ON_IDLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_TPCM_GO_IDLE_ANY_TIME 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_TPCM_GO_IDLE_ANY_TIME_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_TPCM_GO_IDLE_ANY_TIME_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE0_UPPER_PIPE 18:16 /* R--VF */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE0_UPPER_PIPE_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE0_UPPER_PIPE_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE0_UPPER_PIPE_WFI_WAITING 0x2 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE0_UPPER_PIPE_WFI_BLOCKING 0x3 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE0_UPPER_PIPE_WFI_NOT_BLOCKING 0x4 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE0_GFX_ONLY 19:19 /* R--VF */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE0_GFX_ONLY_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE0_GFX_ONLY_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE1_UPPER_PIPE 26:24 /* R--VF */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE1_UPPER_PIPE_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE1_UPPER_PIPE_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE1_UPPER_PIPE_WFI_WAITING 0x2 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE1_UPPER_PIPE_WFI_BLOCKING 0x3 /* R---V */ #define NV_PGRAPH_PRI_FE_MERGE_STATUS_FE1_UPPER_PIPE_WFI_NOT_BLOCKING 0x4 /* R---V */ #define NV_PGRAPH_PRI_FE_CG 0x004041f0 /* RWE4R */ #define NV_PGRAPH_PRI_FE_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FE_CG_IDLE_CG_DLY_CNT__PROD 0x06 /* RW--V */ #define NV_PGRAPH_PRI_FE_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_FE_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_FE_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FE_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_FE_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_FE_CG_STALL_CG_DLY_CNT__PROD 0x06 /* */ #define NV_PGRAPH_PRI_FE_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_FE_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_FE_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FE_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_FE_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_FE_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_FE_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_FE_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_FE_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_FE_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FE_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_FE_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_FE_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_FE_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FE_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_FE_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FE_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FE_CG1 0x004041f4 /* RWE4R */ #define NV_PGRAPH_PRI_FE_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FE_CG1_SLCG 27:1 /* RWEVF */ #define NV_PGRAPH_PRI_FE_CG1_SLCG_ENABLED 0x0000000 /* RW--V */ #define NV_PGRAPH_PRI_FE_CG1_SLCG_DISABLED 0x7ffffff /* RWE-V */ #define NV_PGRAPH_PRI_FE_CG1_SLCG__PROD 0x0000000 /* RW--V */ #define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x00404200+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_OBJECT_TABLE__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 /* R--VF */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_COMPUTE(i) (0x00404210+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_COMPUTE__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_COMPUTE_LAST_EMITTER_IS_GO_IDLE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_COMPUTE_LAST_EMITTER_IS_GO_IDLE_INIT 0xffffffff /* R-I-V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_COMPUTE_LAST_EMITTER_IS_GO_IDLE_TRUE 0x00000001 /* R---V */ #define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_COMPUTE_LAST_EMITTER_IS_GO_IDLE_FALSE 0x00000000 /* R---V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_FE1 0x0040a0c8 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_FE1_STATE 6:4 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_FE1_STATE_IDLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_FE1_STATE_REQ 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_FE1_STATE_RESP 0x4 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_FE1_STATE_REPORT 0x5 /* RW--V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_FE1_STATE_REQ_2 0x6 /* RW--V */ #define NV_PGRAPH_PRI_FE_COMPUTE_RENDER_ENABLE_OVERALL(i) (0x0040a0d0+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_COMPUTE_RENDER_ENABLE_OVERALL__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_FE_COMPUTE_RENDER_ENABLE_OVERALL_MASK 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_FE_COMPUTE_RENDER_ENABLE_OVERALL_MASK_INIT 0xffffffff /* R-I-V */ #define NV_PGRAPH_PRI_FE_COMPUTE_RENDER_ENABLE_OVERALL_MASK_TRUE 0x00000001 /* R---V */ #define NV_PGRAPH_PRI_FE_COMPUTE_RENDER_ENABLE_OVERALL_MASK_FALSE 0x00000000 /* R---V */ #define NV_PGRAPH_PRI_FE_COMPUTE_RENDER_ENABLE_OVERALL_FE1(i) (0x0040a0f0+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_COMPUTE_RENDER_ENABLE_OVERALL_FE1__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_FE_COMPUTE_RENDER_ENABLE_OVERALL_FE1_MASK 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_FE_COMPUTE_RENDER_ENABLE_OVERALL_FE1_MASK_INIT 0xffffffff /* R-I-V */ #define NV_PGRAPH_PRI_FE_COMPUTE_RENDER_ENABLE_OVERALL_FE1_MASK_TRUE 0x00000001 /* R---V */ #define NV_PGRAPH_PRI_FE_COMPUTE_RENDER_ENABLE_OVERALL_FE1_MASK_FALSE 0x00000000 /* R---V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_COMPUTE_FE1 0x0040a1a0 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_COMPUTE_FE1_V 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_UPPER_COMPUTE_FE1_V_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_COMPUTE_FE1 0x0040a1a4 /* RWI4R */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_COMPUTE_FE1_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_RENDER_ENABLE_OFFSET_LOWER_COMPUTE_FE1_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_COMPUTE_FE1 0x0040a1a8 /* RWI4R */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_COMPUTE_FE1_V 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_UPPER_COMPUTE_FE1_V_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_COMPUTE_FE1 0x0040a1ac /* RWI4R */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_COMPUTE_FE1_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_NOTIFY_OFFSET_LOWER_COMPUTE_FE1_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_TPC_FS(i) (0x0040a200+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_TPC_FS__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_FE_TPC_FS_MASK 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_FE_TPC_FS_MASK_TPC_DISABLED 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_FE_TPC_FS_MASK_TPC_ENABLED 0x00000001 /* R---V */ #define NV_PGRAPH_PRI_FE_TPC_SKIP_GRAPHICS(i) (0x0040a220+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_FE_TPC_SKIP_GRAPHICS__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_FE_TPC_SKIP_GRAPHICS_MASK 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_TPC_SKIP_GRAPHICS_MASK_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FE_TPC_OWNER_CLASS(i) (0x0040a240+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_TPC_OWNER_CLASS__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_FE_TPC_OWNER_CLASS_MASK 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_FE_TPC_OWNER_CLASS_MASK_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_FE_TPC_OWNER_CLASS_MASK_GRAPHICS 0x00000000 /* R---V */ #define NV_PGRAPH_PRI_FE_TPC_OWNER_CLASS_MASK_COMPUTE 0x00000001 /* R---V */ #define NV_PGRAPH_PRI_FE_SCG_SCHEDULING 0x0040a264 /* R--4R */ #define NV_PGRAPH_PRI_FE_SCG_SCHEDULING_MODE 1:0 /* R--VF */ #define NV_PGRAPH_PRI_FE_SCG_SCHEDULING_MODE_MIXED 0x0 /* R---V */ #define NV_PGRAPH_PRI_FE_SCG_SCHEDULING_MODE_ALL_COMPUTE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_SCG_SCHEDULING_MODE_COMPUTE_IN_GRAPHICS 0x2 /* R---V */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK 0x0040a260 /* RWE4R */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_MASK 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_MASK_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_GPCID 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_GPCID_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_PESID 29:24 /* RWEVF */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_PESID_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_ACTION 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_ACTION_READ 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_ACTION_WRITE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_REQ 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_REQ_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_REQ_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FE_TPC_PESMASK_REQ_SEND 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_BASEA(i) (0x0040a300+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_BASEA__SIZE_1 64 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_BASEA_ADDR_UPPER 7:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_BASEB(i) (0x0040a400+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_BASEB__SIZE_1 64 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_BASEB_ADDR 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL(i) (0x0040a500+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL__SIZE_1 64 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_MASK 7:0 /* R-XVF */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_I2M_ADDR_ENABLE 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_I2M_ADDR_ENABLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_I2M_ADDR_ENABLE_TRUE 0x0 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 /* R-XVF */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_I2M_DEPENDENT_ENABLE 13:13 /* R-XVF */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_I2M_DEPENDENT_ENABLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_I2M_DEPENDENT_ENABLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_IQ2M_ADDR_ENABLE 16:16 /* R-XVF */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_IQ2M_DEPENDENT_ENABLE 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_IQ2M_DEPENDENT_ENABLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_IQ2M_DEPENDENT_ENABLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_SEND_PCAS_ENABLE 24:24 /* R-XVF */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_SEND_PCAS_ENABLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FE_QMD_VIRT_CONTROL_SEND_PCAS_ENABLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FE_TPCM_GR_TPC_MASK(i) (0x0040a680+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_FE_TPCM_GR_TPC_MASK__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_FE_TPCM_GR_TPC_MASK_MASK 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_TPCM_GR_TPC_MASK_MASK_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_TPCM_GR_TPC_MASK_MASK_GRAPHICS 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_FE_TPCM_GR_TPC_MASK_MASK_COMPUTE 0x00000001 /* RW--V */ #define NV_PGRAPH_PRI_FE_LAST_GR_TPC_MASK(i) (0x0040a6a0+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_FE_LAST_GR_TPC_MASK__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_FE_LAST_GR_TPC_MASK_MASK 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_LAST_GR_TPC_MASK_MASK_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_LAST_GR_TPC_MASK_MASK_GRAPHICS 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_FE_LAST_GR_TPC_MASK_MASK_COMPUTE 0x00000001 /* RW--V */ #define NV_PGRAPH_PRI_FE_CWD_OWN_TPC_MASK(i) (0x0040a6c0+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_FE_CWD_OWN_TPC_MASK__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_FE_CWD_OWN_TPC_MASK_MASK 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FE_CWD_OWN_TPC_MASK_MASK_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FE_CWD_OWN_TPC_MASK_MASK_GRAPHICS 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_FE_CWD_OWN_TPC_MASK_MASK_COMPUTE 0x00000001 /* RW--V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK 0x00404484 /* RWE4R */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x00404488 /* RWE4R */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX__PRIV_LEVEL_MASK 0x00404484 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_NVCLASS 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_NVCLASS_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_METHOD_ADDR 27:16 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_METHOD_ADDR_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_FEPIPE 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_FEPIPE_FE0 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_FEPIPE_FE1 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_READ 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_READ_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_READ_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x0040448c /* RWE4R */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA__PRIV_LEVEL_MASK 0x00404484 /* */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA_V_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA_V_DUMMY 0x00000000 /* */ #define NV_PGRAPH_PRI_MME_HWW_ESR 0x00404490 /* RWE4R */ #define NV_PGRAPH_PRI_MME_HWW_ESR_MISSING_MACRO_DATA 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_MISSING_MACRO_DATA_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_MISSING_MACRO_DATA_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_EXTRA_MACRO_DATA 1:1 /* C--VF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_EXTRA_MACRO_DATA_NOT_PENDING 0x0 /* C---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_EXTRA_MACRO_DATA_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_OPCODE 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_OPCODE_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_OPCODE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_BRANCH_IN_DELAY_SLOT 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_BRANCH_IN_DELAY_SLOT_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_BRANCH_IN_DELAY_SLOT_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_MAX_INSTR_LIMIT 4:4 /* C--VF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_MAX_INSTR_LIMIT_NOT_PENDING 0x0 /* C---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_MAX_INSTR_LIMIT_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DATA_RAM_ACCESS_OUT_OF_BOUNDS 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DATA_RAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DATA_RAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_MME_METHOD 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_MME_METHOD_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_MME_METHOD_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_MME_INSTR_WRITE 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_MME_INSTR_WRITE_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_MME_INSTR_WRITE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_DRAM_ACCESS_OUT_OF_BOUNDS 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_DRAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_DRAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_FROM_PB 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_FROM_PB_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_FROM_PB_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_ILLEGAL_FIFO_CONFIG 18:18 /* C--VF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_ILLEGAL_FIFO_CONFIG_NOT_PENDING 0x0 /* C---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_ILLEGAL_FIFO_CONFIG_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_OVERFLOW 19:19 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_OVERFLOW_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_FIFO_RESIZED_WHEN_NONIDLE 20:20 /* C--VF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_FIFO_RESIZED_WHEN_NONIDLE_NOT_PENDING 0x0 /* C---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_FIFO_RESIZED_WHEN_NONIDLE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_STOP_ON_TRAP 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_STOP_ON_TRAP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_STOP_ON_TRAP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_V_0 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO 0x00404494 /* R--4R */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC 11:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC_INIT 0x000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MACRO_ADDRESS 19:12 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MACRO_ADDRESS_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_VEID 27:22 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_VEID_0 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC_VALID 28:28 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC_VALID_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX 0x004044a4 /* R--4R */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_DATA_FIFO_SIZE 7:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_DATA_FIFO_SIZE_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_LOADSOURCE 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_LOADSOURCE_MTHD 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_LOADSOURCE_DMA 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_DATA_RAM_SIZE 23:16 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_DATA_RAM_SIZE_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MTHD 0x004044a0 /* R--4R */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MTHD_ADDR 13:2 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MTHD_ADDR_INIT 0x000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MTHD_SUBCH 18:16 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MTHD_SUBCH_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MTHD_PRECISE 30:30 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MTHD_PRECISE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MTHD_VALID 31:31 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MTHD_VALID_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MTHD2 0x004044bc /* R--4R */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MTHD2_DATA 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MTHD2_DATA_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO2 0x0040449c /* R--4R */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO2_IR 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO2_IR_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO3 0x004044a8 /* R--4R */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO3_IR 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO3_IR_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO4 0x004044ac /* R--4R */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO4_IR 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO4_IR_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK 0x004044cc /* RWE4R */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_MME_DEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_MME_CONFIG 0x00404498 /* RWE4R */ #define NV_PGRAPH_PRI_MME_CONFIG__PRIV_LEVEL_MASK 0x004044cc /* */ #define NV_PGRAPH_PRI_MME_CONFIG_SHADOW_FILTER 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_CONFIG_SHADOW_FILTER_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_CONFIG_SHADOW_FILTER_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_CONFIG_PTIMER 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_MME_CONFIG_PTIMER_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_CONFIG_PTIMER_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_CONFIG_PTIMER__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_CONFIG_MME_TO_M2M_INLINE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_MME_CONFIG_MME_TO_M2M_INLINE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_CONFIG_MME_TO_M2M_INLINE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_CONFIG_MME_TO_M2M_INLINE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_WFI_ON_MTHD 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_WFI_ON_MTHD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_WFI_ON_MTHD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_SINGLE_MEM_REQ 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_SINGLE_MEM_REQ_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_SINGLE_MEM_REQ_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_MAX_ONE_SYNC 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_MAX_ONE_SYNC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_MAX_ONE_SYNC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_FIFOED_RESET 8:8 /* -WEVF */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_FIFOED_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_FIFOED_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_FORK_DMA_MTHDS 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_FORK_DMA_MTHDS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_FORK_DMA_MTHDS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_FIFOED_RESET_HYST 13:10 /* RWEVF */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_FIFOED_RESET_HYST_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_OUTSTANDING_WRITE_LIMIT 17:14 /* RWEVF */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_OUTSTANDING_WRITE_LIMIT_MAX 0xf /* RW--V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_OUTSTANDING_WRITE_LIMIT_INIT 0xf /* RWE-V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_OUTSTANDING_SYSMEMBAR_LIMIT 20:18 /* RWEVF */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_OUTSTANDING_SYSMEMBAR_LIMIT_MAX 0x7 /* RW--V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_OUTSTANDING_SYSMEMBAR_LIMIT_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_RDAT_STALL_WATERMARK 23:21 /* RWEVF */ #define NV_PGRAPH_PRI_MME_CONFIG_DMA_RDAT_STALL_WATERMARK_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO 0x004044c0 /* R--4R */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_METHOD 2:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_METHOD_READ 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_METHOD_WRITE 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_METHOD_REDUCTION 0x2 /* R---V */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_METHOD_SYNC 0x3 /* R---V */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_MME_GENERATED 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_MME_GENERATED_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_MME_PC 15:4 /* R-EVF */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_MME_PC_INIT 0x000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_MME_MACRO_ADDR 23:16 /* R-EVF */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_MME_MACRO_ADDR_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_VEID 31:26 /* R-EVF */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO_VEID_0 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO2 0x004044c4 /* R--4R */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO2_MTHD_DATA 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO2_MTHD_DATA_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO3 0x004044c8 /* R--4R */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO3_DRAM_ADDRESS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_DMA_HWW_ESR_INFO3_DRAM_ADDRESS_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_STATUS 0x004044b0 /* R--4R */ #define NV_PGRAPH_PRI_MME_STATUS_CPU_SADDR_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_CPU_UPPER_STATUS 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_CPU_LOWER_STATUS 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_CPU_CPU2DMA_STATUS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_DMA_STATUS 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_SHADOW_STATUS 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_CPU_WAIT_FOR_STATE_READ 25:25 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_CPU_WAIT_FOR_MTHD_DATA 26:26 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_CPU_WAIT_FOR_FIFO_DATA 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_CPU_WAIT_FOR_DRAM 28:28 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_CPU_WAIT_FOR_MTHD_PIPE 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_CPU_WAIT_FOR_EXCEPTION 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_CPU_WAIT_FOR_OTHER 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_MACRO 0x004044b4 /* R--4R */ #define NV_PGRAPH_PRI_MME_STATUS_MACRO_PC 11:0 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_MACRO_ADDRESS 19:12 /* R-XVF */ #define NV_PGRAPH_PRI_MME_STATUS_MACRO_RUNNING 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_MME_DEBUG 0x004044d0 /* RWE4R */ #define NV_PGRAPH_PRI_MME_DEBUG__PRIV_LEVEL_MASK 0x004044cc /* */ #define NV_PGRAPH_PRI_MME_DEBUG_STATUS 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_DEBUG_STATUS_RUNNING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_DEBUG_STATUS_STOPPED 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_DEBUG_ENABLE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_MME_DEBUG_ENABLE_DISABLED 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_DEBUG_ENABLE_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_DEBUG_IRAM_RD 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_MME_DEBUG_IRAM_RD_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_DEBUG_IRAM_RD_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_DEBUG_IRAM_PC 26:15 /* RWEVF */ #define NV_PGRAPH_PRI_MME_DEBUG_IRAM_PC_INIT 0x000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_INSTR_INS 0x004044d4 /* RWE4R */ #define NV_PGRAPH_PRI_MME_INSTR_INS__PRIV_LEVEL_MASK 0x004044cc /* */ #define NV_PGRAPH_PRI_MME_INSTR_INS_REQ 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_INSTR_INS_REQ_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_INSTR_INS_REQ_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_INSTR_INS_OP 5:1 /* RWEVF */ #define NV_PGRAPH_PRI_MME_INSTR_INS_OP_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_INSTR_INS_SRC0 10:6 /* RWEVF */ #define NV_PGRAPH_PRI_MME_INSTR_INS_SRC0_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_INSTR_INS_SRC1 15:11 /* RWEVF */ #define NV_PGRAPH_PRI_MME_INSTR_INS_SRC1_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_INSTR_INS_IMMED 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_MME_INSTR_INS_IMMED_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_INSTR_INS2 0x004044d8 /* RWE4R */ #define NV_PGRAPH_PRI_MME_INSTR_INS2__PRIV_LEVEL_MASK 0x004044cc /* */ #define NV_PGRAPH_PRI_MME_INSTR_INS2_DST 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_INSTR_INS2_DST_INIT_REG_ZERO 0x18 /* R-E-V */ #define NV_PGRAPH_PRI_MME_INSTR_INS2_MTHD 18:16 /* RWEVF */ #define NV_PGRAPH_PRI_MME_INSTR_INS2_MTHD_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_INSTR_INS2_EMIT 22:19 /* RWEVF */ #define NV_PGRAPH_PRI_MME_INSTR_INS2_EMIT_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_INSTR_INS_CAPT 0x004044dc /* R--4R */ #define NV_PGRAPH_PRI_MME_INSTR_INS_CAPT_DATA 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_MME_PERFMON_OPCODE 0x004044e0 /* RWE4R */ #define NV_PGRAPH_PRI_MME_PERFMON_OPCODE_OP_MATCH 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_PERFMON_OPCODE_OP_MATCH_JAL 0x18 /* R-E-V */ #define NV_PGRAPH_PRI_MME_PERFMON_OPCODE_OP_MASK 9:5 /* RWEVF */ #define NV_PGRAPH_PRI_MME_PERFMON_OPCODE_OP_MASK_INIT 0x1f /* R-E-V */ #define NV_PGRAPH_PRI_MME_PERFMON_OPCODE_IMMED_MASK 13:10 /* RWEVF */ #define NV_PGRAPH_PRI_MME_PERFMON_OPCODE_IMMED_MASK_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_PERFMON_OPCODE_IMMED_MATCH 17:14 /* RWEVF */ #define NV_PGRAPH_PRI_MME_PERFMON_OPCODE_IMMED_MATCH_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_INSTR_RAM_GFX_VEID_CONFIG 0x004044ec /* RWI4R */ #define NV_PGRAPH_PRI_MME_INSTR_RAM_GFX_VEID_CONFIG_WR_DISABLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_MME_INSTR_RAM_GFX_VEID_CONFIG_WR_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MME_INSTR_RAM_GFX_VEID_CONFIG_WR_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_INSTR_RAM_GFX_VEID_CONFIG_WR_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_INSTR_RAM_COMPUTE_VEID_CONFIG(i) (0x004044f0+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_MME_INSTR_RAM_COMPUTE_VEID_CONFIG__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_MME_INSTR_RAM_COMPUTE_VEID_CONFIG_WR_DISABLE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MME_INSTR_RAM_COMPUTE_VEID_CONFIG_WR_DISABLE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MME_INSTR_RAM_COMPUTE_VEID_CONFIG_WR_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGRAPH_PRI_MME_INSTR_RAM_COMPUTE_VEID_CONFIG_WR_DISABLE_FALSE 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR 0x0040a790 /* RWE4R */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_MISSING_MACRO_DATA 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_MISSING_MACRO_DATA_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_MISSING_MACRO_DATA_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_EXTRA_MACRO_DATA 1:1 /* C--VF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_EXTRA_MACRO_DATA_NOT_PENDING 0x0 /* C---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_EXTRA_MACRO_DATA_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_ILLEGAL_OPCODE 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_ILLEGAL_OPCODE_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_ILLEGAL_OPCODE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_BRANCH_IN_DELAY_SLOT 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_BRANCH_IN_DELAY_SLOT_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_BRANCH_IN_DELAY_SLOT_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_MAX_INSTR_LIMIT 4:4 /* C--VF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_MAX_INSTR_LIMIT_NOT_PENDING 0x0 /* C---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_MAX_INSTR_LIMIT_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DATA_RAM_ACCESS_OUT_OF_BOUNDS 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DATA_RAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DATA_RAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_ILLEGAL_MME_METHOD 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_ILLEGAL_MME_METHOD_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_ILLEGAL_MME_METHOD_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_ILLEGAL_MME_INSTR_WRITE 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_ILLEGAL_MME_INSTR_WRITE_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_ILLEGAL_MME_INSTR_WRITE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_DRAM_ACCESS_OUT_OF_BOUNDS 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_DRAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_DRAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_READ_FIFOED_FROM_PB 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_READ_FIFOED_FROM_PB_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_READ_FIFOED_FROM_PB_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_ILLEGAL_FIFO_CONFIG 18:18 /* C--VF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_ILLEGAL_FIFO_CONFIG_NOT_PENDING 0x0 /* C---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_ILLEGAL_FIFO_CONFIG_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_READ_FIFOED_OVERFLOW 19:19 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_READ_FIFOED_OVERFLOW_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_READ_FIFOED_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_FIFO_RESIZED_WHEN_NONIDLE 20:20 /* C--VF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_FIFO_RESIZED_WHEN_NONIDLE_NOT_PENDING 0x0 /* C---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_DMA_FIFO_RESIZED_WHEN_NONIDLE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_STOP_ON_TRAP 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_STOP_ON_TRAP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_STOP_ON_TRAP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_RESET_V_0 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO 0x0040a794 /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_PC 11:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_PC_INIT 0x000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MACRO_ADDRESS 19:12 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MACRO_ADDRESS_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_VEID 27:22 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_VEID_0 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_PC_VALID 28:28 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_PC_VALID_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_EX 0x0040a7a4 /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_EX_DATA_FIFO_SIZE 7:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_EX_DATA_FIFO_SIZE_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_EX_LOADSOURCE 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_EX_LOADSOURCE_MTHD 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_EX_LOADSOURCE_DMA 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_EX_DATA_RAM_SIZE 23:16 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_EX_DATA_RAM_SIZE_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MTHD 0x0040a7a0 /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MTHD_ADDR 13:2 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MTHD_ADDR_INIT 0x000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MTHD_SUBCH 18:16 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MTHD_SUBCH_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MTHD_PRECISE 30:30 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MTHD_PRECISE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MTHD_VALID 31:31 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MTHD_VALID_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MTHD2 0x0040a7bc /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MTHD2_DATA 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO_MTHD2_DATA_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO2 0x0040a79c /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO2_IR 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO2_IR_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO3 0x0040a7a8 /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO3_IR 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO3_IR_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO4 0x0040a7ac /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO4_IR 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_HWW_ESR_INFO4_IR_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK 0x0040a7cc /* RWE4R */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG 0x0040a798 /* RWE4R */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG__PRIV_LEVEL_MASK 0x0040a7cc /* */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_SHADOW_FILTER 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_SHADOW_FILTER_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_SHADOW_FILTER_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_PTIMER 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_PTIMER_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_PTIMER_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_PTIMER__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_MME_TO_M2M_INLINE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_MME_TO_M2M_INLINE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_MME_TO_M2M_INLINE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_MME_TO_M2M_INLINE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_WFI_ON_MTHD 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_WFI_ON_MTHD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_WFI_ON_MTHD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_SINGLE_MEM_REQ 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_SINGLE_MEM_REQ_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_SINGLE_MEM_REQ_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_MAX_ONE_SYNC 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_MAX_ONE_SYNC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_MAX_ONE_SYNC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_FIFOED_RESET 8:8 /* -WEVF */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_FIFOED_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_FIFOED_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_FORK_DMA_MTHDS 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_FORK_DMA_MTHDS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_FORK_DMA_MTHDS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_FIFOED_RESET_HYST 13:10 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_FIFOED_RESET_HYST_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_OUTSTANDING_WRITE_LIMIT 17:14 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_OUTSTANDING_WRITE_LIMIT_MAX 0xf /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_OUTSTANDING_WRITE_LIMIT_INIT 0xf /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_OUTSTANDING_SYSMEMBAR_LIMIT 20:18 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_OUTSTANDING_SYSMEMBAR_LIMIT_MAX 0x7 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_OUTSTANDING_SYSMEMBAR_LIMIT_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_RDAT_STALL_WATERMARK 23:21 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_CONFIG_DMA_RDAT_STALL_WATERMARK_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO 0x0040a7c0 /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_METHOD 2:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_METHOD_READ 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_METHOD_WRITE 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_METHOD_REDUCTION 0x2 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_METHOD_SYNC 0x3 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_MME_GENERATED 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_MME_GENERATED_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_MME_PC 15:4 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_MME_PC_INIT 0x000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_MME_MACRO_ADDR 23:16 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_MME_MACRO_ADDR_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_VEID 31:26 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO_VEID_0 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO2 0x0040a7c4 /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO2_MTHD_DATA 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO2_MTHD_DATA_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO3 0x0040a7c8 /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO3_DRAM_ADDRESS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_DMA_HWW_ESR_INFO3_DRAM_ADDRESS_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_STATUS 0x0040a7b0 /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_CPU_SADDR_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_CPU_UPPER_STATUS 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_CPU_LOWER_STATUS 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_CPU_CPU2DMA_STATUS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_DMA_STATUS 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_SHADOW_STATUS 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_CPU_WAIT_FOR_STATE_READ 25:25 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_CPU_WAIT_FOR_MTHD_DATA 26:26 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_CPU_WAIT_FOR_FIFO_DATA 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_CPU_WAIT_FOR_DRAM 28:28 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_CPU_WAIT_FOR_MTHD_PIPE 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_CPU_WAIT_FOR_EXCEPTION 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_CPU_WAIT_FOR_OTHER 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_MACRO 0x0040a7b4 /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_MACRO_PC 11:0 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_MACRO_ADDRESS 19:12 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_STATUS_MACRO_RUNNING 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG 0x0040a7d0 /* RWE4R */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG__PRIV_LEVEL_MASK 0x0040a7cc /* */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_STATUS 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_STATUS_RUNNING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_STATUS_STOPPED 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_ENABLE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_ENABLE_DISABLED 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_ENABLE_ENABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_IRAM_RD 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_IRAM_RD_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_IRAM_RD_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_IRAM_PC 26:15 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_DEBUG_IRAM_PC_INIT 0x000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS 0x0040a7d4 /* RWE4R */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS__PRIV_LEVEL_MASK 0x0040a7cc /* */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_REQ 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_REQ_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_REQ_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_OP 5:1 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_OP_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_SRC0 10:6 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_SRC0_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_SRC1 15:11 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_SRC1_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_IMMED 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_IMMED_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS2 0x0040a7d8 /* RWE4R */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS2__PRIV_LEVEL_MASK 0x0040a7cc /* */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS2_DST 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS2_DST_INIT_REG_ZERO 0x18 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS2_MTHD 18:16 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS2_MTHD_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS2_EMIT 22:19 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS2_EMIT_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_CAPT 0x0040a7dc /* R--4R */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_INS_CAPT_DATA 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_MME_FE1_PERFMON_OPCODE 0x0040a7e0 /* RWE4R */ #define NV_PGRAPH_PRI_MME_FE1_PERFMON_OPCODE_OP_MATCH 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_PERFMON_OPCODE_OP_MATCH_JAL 0x18 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_PERFMON_OPCODE_OP_MASK 9:5 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_PERFMON_OPCODE_OP_MASK_INIT 0x1f /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_PERFMON_OPCODE_IMMED_MASK 13:10 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_PERFMON_OPCODE_IMMED_MASK_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_PERFMON_OPCODE_IMMED_MATCH 17:14 /* RWEVF */ #define NV_PGRAPH_PRI_MME_FE1_PERFMON_OPCODE_IMMED_MATCH_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_RAM_GFX_VEID_CONFIG 0x0040a7ec /* RWI4R */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_RAM_GFX_VEID_CONFIG_WR_DISABLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_RAM_GFX_VEID_CONFIG_WR_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_RAM_GFX_VEID_CONFIG_WR_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_RAM_GFX_VEID_CONFIG_WR_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_RAM_COMPUTE_VEID_CONFIG(i) (0x0040a7f0+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_RAM_COMPUTE_VEID_CONFIG__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_RAM_COMPUTE_VEID_CONFIG_WR_DISABLE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_RAM_COMPUTE_VEID_CONFIG_WR_DISABLE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_RAM_COMPUTE_VEID_CONFIG_WR_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGRAPH_PRI_MME_FE1_INSTR_RAM_COMPUTE_VEID_CONFIG_WR_DISABLE_FALSE 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x00404600 /* RWE4R */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EXTRA_INLINE_DATA 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EXTRA_INLINE_DATA_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EXTRA_INLINE_DATA_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_MISSING_INLINE_DATA 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_MISSING_INLINE_DATA_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_MISSING_INLINE_DATA_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_FEPIPE 19:19 /* R-EVF */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_FEPIPE_FE0 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_FEPIPE_FE1 0x1 /* R---V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_VEID 25:20 /* R-EVF */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_VEID_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_V_0 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO 0x00404634 /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO_PACKET_TYPE 2:0 /* R-EVF */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO_PACKET_TYPE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO_PACKET_TYPE_ROUTE_BUNDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO_PACKET_TYPE_ROUTE_BUNDLE64 0x1 /* R---V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO_PACKET_TYPE_VTX_IDX 0x2 /* R---V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO_PACKET_TYPE_LD_CONST 0x3 /* R---V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO_PACKET_TYPE_LD_ROOT_TABLE 0x4 /* R---V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO_PACKET_TYPE_M2M_INLINE_128 0x5 /* R---V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO_PACKET_TYPE_QMD_INLINE 0x6 /* R---V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO_PACKET_ADDR 31:16 /* R-EVF */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO_PACKET_ADDR_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO2 0x00404638 /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO2_DATA 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_INFO2_DATA_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_MEMFMT_L2_EVICT_POLICY 0x00404604 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_L2_EVICT_POLICY_MEMFMT_WRITE 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_L2_EVICT_POLICY_MEMFMT_WRITE_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_L2_EVICT_POLICY_MEMFMT_WRITE_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_L2_EVICT_POLICY_MEMFMT_WRITE_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_L2_EVICT_POLICY_MEMFMT_SEMAPHORE 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_L2_EVICT_POLICY_MEMFMT_SEMAPHORE_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_L2_EVICT_POLICY_MEMFMT_SEMAPHORE_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_L2_EVICT_POLICY_MEMFMT_SEMAPHORE_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_WATERMARK 0x0040460c /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WATERMARK_V 13:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WATERMARK_V_0 0x3fff /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG 0x00404610 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_FLUSH_COMPLETE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_FLUSH_COMPLETE_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_NOTIFY_OVERWRITE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_NOTIFY_OVERWRITE_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_FLUSH_IS_DEFERRED 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_FLUSH_IS_DEFERRED_NO 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_FLUSH_IS_DEFERRED_YES 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_DEFERRED_FLUSH_PEND 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_DEFERRED_FLUSH_PEND_NO 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_DEFERRED_FLUSH_PEND_YES 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_DMA_FEPIPE 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_DMA_FEPIPE_FE0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_DMA_FEPIPE_FE1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_DMA_COMPLETE_FILT 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_DMA_COMPLETE_FILT_0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_DMA_COMPLETE_FILT_MIN 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_DMA_VEID 21:16 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_DEBUG_DMA_VEID_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_LAUNCH_DMA 0x00404618 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_LAUNCH_DMA_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_LAUNCH_DMA_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_SM 0x0040461c /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_SM_V 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_SM_V_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_SM_DBUF_ROLL 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_SM_DBUF_ROLL_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_SOFS 0x00404620 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_SOFS_V 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_SOFS_V_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_SOFS_PACK 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_SOFS_PACK_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_RA 0x00404624 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_RA_V 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_UNPACK_RA_V_0 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_NTL 0x0040462c /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_NTL_TIMESTAMP 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_NTL_TIMESTAMP_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_NTH 0x00404630 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_NTH_TIMESTAMP 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_NTH_TIMESTAMP_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_RDC_LINECNT 0x00404640 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_RDC_LINECNT_V 17:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_RDC_LINECNT_V_0 0x00000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_RDC_LINECNT_RUNNING 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_RDC_LINECNT_RUNNING_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_RDC_REMAINDER 0x00404654 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_RDC_REMAINDER_V 24:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_RDC_REMAINDER_V_0 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_RDC_REMAINDER_LAST 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_RDC_REMAINDER_LAST_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_RDC_TRIGGER 0x00404660 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_RDC_TRIGGER_V 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_RDC_TRIGGER_V_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_SM 0x00404678 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_SM_LSM 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_SM_LSM_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_SM_FSM 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_SM_FSM_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_SM_BSM 18:16 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_SM_BSM_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL 0x0040467c /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL_BUSY 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL_BUSY_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL_BLOCK_LIN 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL_BLOCK_LIN_NO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL_BLOCK_LIN_YES 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL_BXF 12:4 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL_BXF_0 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL_BBUSY 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL_BBUSY_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_RA 0x00404680 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_RA_MIU 13:8 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_RA_MIU_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_RA_UNPACK 21:16 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_RA_UNPACK_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_RA_WA 29:24 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_RA_WA_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_LINECNT 0x00404684 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_LINECNT_V 17:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_LINECNT_V_0 0x00000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_ADDR_HI 0x00404688 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_ADDR_HI_V 16:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_ADDR_HI_V_0 0x00000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_ADDR_LO 0x0040468c /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_ADDR_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_ADDR_LO_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_NSADDR_HI 0x00404690 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_NSADDR_HI_V 16:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_NSADDR_HI_V_0 0x00000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_NSADDR_LO 0x00404694 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_NSADDR_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_NSADDR_LO_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_REMAINDER 0x00404698 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_REMAINDER_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_REMAINDER_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_REMAINDER1 0x0040469c /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_REMAINDER1_V 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_REMAINDER1_V_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_WBC 0x004046a0 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_WBC_BURST_SIZE 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_WBC_BURST_SIZE_0 0x080 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_WBC_ADDR_MASK 24:16 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_WBC_ADDR_MASK_0 0x07f /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_TRIGGER 0x004046a4 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_TRIGGER_V 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_TRIGGER_V_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_X 0x004046a8 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_X_V 21:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_X_V_0 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_Y 0x004046ac /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_Y_V 16:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_Y_V_0 0x00000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_BLINECNT 0x004046b0 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_BLINECNT_V 17:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_BLINECNT_V_0 0x00000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_BREMAINDER 0x004046b4 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_BREMAINDER_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_BREMAINDER_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_BSM_B2X 0x004046b8 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_BSM_B2X_V 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_BSM_B2X_V_0 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_TOTAL 0x004046bc /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_TOTAL_V 13:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_TOTAL_V_0 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SM 0x004046c0 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SM_V 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SM_V_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SM_SPARE 31:4 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SM_SPARE_0 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_RDC_LINELENGTH 0x004046cc /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_RDC_LINELENGTH_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_RDC_LINELENGTH_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_RDC_LINECOUNT 0x004046d0 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_RDC_LINECOUNT_V 17:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_RDC_LINECOUNT_V_0 0x00000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL1 0x00404700 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL1_STATE 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL1_STATE_IDLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL1_STATE_LOAD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL1_STATE_XFER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL1_MORE_INLINE_DATA_EXPECTED 2:2 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL1_MORE_INLINE_DATA_EXPECTED_0 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL1_XFER_BYTES 12:4 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL1_XFER_BYTES_0 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL1_DBUF_CNT 29:16 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL1_DBUF_CNT_0 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_RDC_RA2 0x004046c8 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_RDC_RA2_PACK_WA 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_RDC_RA2_PACK_WA__0 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL2 0x00404704 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL2_OLD_WE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL2_OLD_WE_NONE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL2_SAVED 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_PACK_CTRL2_SAVED_NONE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_PACK_OLD_DATA 0x00404708 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_PACK_OLD_DATA_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_PACK_OLD_DATA_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_PACK_SAVED_INLINE 0x00404608 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_PACK_SAVED_INLINE_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_PACK_SAVED_INLINE_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2 0x00404718 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_WCOUNT 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_WCOUNT_0 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_FIRST 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_FIRST_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_U_STRT_LOC 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_U_STRT_LOC_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_UBUF_VLD 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_UBUF_VLD_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_UBUF_VLD_FF 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_UBUF_VLD_FF_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_UBUF_DI 29:16 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_UBUF_DI_0 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_LAST 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL2_LAST_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRQU_DO 0x00404754 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRQU_DO_V 13:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRQU_DO_V_0 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRQU_DO_V_1 0x0001 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_PITCH_OUT 0x00404714 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_PITCH_OUT_V 22:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_PITCH_OUT_V_0 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_OFFSET_UPPER 0x0040471c /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_OFFSET_UPPER_V 16:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_OFFSET_UPPER_V_0 0x00000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_OFFSET_LOWER 0x00404720 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_OFFSET_LOWER_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_OFFSET_LOWER_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_LINE_LENGTH 0x00404724 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_LINE_LENGTH_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_LINE_LENGTH_V_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL3 0x00404728 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL3_MBUF_VLD 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL3_MBUF_VLD_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL3_MBUF_VLD_FF 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_CTRL3_MBUF_VLD_FF_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_MBUF_DI_LOWER 0x0040472c /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_MBUF_DI_LOWER_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_MBUF_DI_LOWER_VAL_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRC_MBUF_DI_UPPER 0x00404730 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRC_MBUF_DI_UPPER_VAL 26:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRC_MBUF_DI_UPPER_VAL_0 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRQM_DO_LOWER 0x00404744 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRQM_DO_LOWER_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRQM_DO_LOWER_VAL_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_WRQM_DO_UPPER 0x00404748 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_WRQM_DO_UPPER_VAL 26:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_WRQM_DO_UPPER_VAL_0 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SEMA1 0x00404734 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SEMA1_ADDR_UPPER 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SEMA1_ADDR_UPPER_0 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SEMA1_DONE 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SEMA1_DONE_NO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SEMA1_DONE_YES 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SEMA2 0x00404738 /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SEMA2_ADDR_LOWER 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SEMA2_ADDR_LOWER_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SEMA3 0x0040473c /* RWI4R */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SEMA3_PAYLOAD 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_MEMFMT_MIU_SEMA3_PAYLOAD_0 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_MEMFMT_SEMAPHORE_A 0x00404760 /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_SEMAPHORE_A_V 7:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_SEMAPHORE_A_V_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_SEMAPHORE_B 0x00404764 /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_SEMAPHORE_B_V 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_SEMAPHORE_B_V_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_SEMAPHORE_C 0x00404768 /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_SEMAPHORE_C_V 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_SEMAPHORE_C_V_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_OFFSET_OUT_UPPER 0x00404614 /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_OFFSET_OUT_UPPER_V 16:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_OFFSET_OUT_UPPER_V_INIT 0x00000 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_OFFSET_OUT 0x004046ec /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_OFFSET_OUT_V 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_OFFSET_OUT_V_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_PITCH_OUT 0x004046f8 /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_PITCH_OUT_V 22:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_PITCH_OUT_V_INIT 0x000000 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_LINE_LENGTH_IN 0x004046fc /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_LINE_LENGTH_IN_V 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_LINE_LENGTH_IN_V_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_LINE_COUNT 0x00404758 /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_LINE_COUNT_V 17:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_LINE_COUNT_V_INIT 0x00000 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_DST_BLOCK_SIZE 0x0040475c /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_DST_BLOCK_SIZE_V 5:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_DST_BLOCK_SIZE_V_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_DST_WIDTH 0x0040476c /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_DST_WIDTH_V 21:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_DST_WIDTH_V_INIT 0x000000 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_DST_HEIGHT 0x00404770 /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_DST_HEIGHT_V 17:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_DST_HEIGHT_V_INIT 0x00000 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_DST_DEPTH 0x00404774 /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_DST_DEPTH_V 11:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_DST_DEPTH_V_INIT 0x000 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_DST_LAYER 0x00404778 /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_DST_LAYER_V 10:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_DST_LAYER_V_INIT 0x000 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_DST_ORIGIN_BYTES_X 0x0040477c /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_DST_ORIGIN_BYTES_X_V 20:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_DST_ORIGIN_BYTES_X_V_INIT 0x000000 /* R-I-V */ #define NV_PGRAPH_PRI_MEMFMT_DST_ORIGIN_SAMPLES_Y 0x00404780 /* R--4R */ #define NV_PGRAPH_PRI_MEMFMT_DST_ORIGIN_SAMPLES_Y_V 16:0 /* R-IVF */ #define NV_PGRAPH_PRI_MEMFMT_DST_ORIGIN_SAMPLES_Y_V_INIT 0x00000 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK 0x00409280 /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK 0x00409284 /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK 0x00409288 /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK 0x0040928c /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK 0x00409290 /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK 0x00409294 /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK 0x004090e8 /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK 0x00409298 /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x8 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK 0x0040929c /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK 0x004093d0 /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK 0x004093f0 /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK 0x004093f4 /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK 0x004093f8 /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK 0x004093fc /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(i) (0x0040918c+(i)*16) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(i) (0x004092b0+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK 0x00409190 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK 0x00409194 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK 0x00409198 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK 0x0040919c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK 0x004091a0 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK 0x004091a4 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK 0x004091a8 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK 0x004091b0 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK 0x004091bc /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK 0x004091e0 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK 0x004091e4 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK 0x004091e8 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK 0x004091ec /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK 0x004091f0 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK 0x004091f4 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK 0x004091f8 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK 0x004091fc /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK 0x00409220 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK 0x00409224 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK 0x0040922c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET 0x00409000 /* -W-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_GPTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_WDTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_MTHD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_HALT 4:4 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_HALT_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXTERR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_SWGEN0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_SWGEN1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT 15:8 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ1 8:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ1_SET 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ2 9:9 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ2_SET 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ3 10:10 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ3_SET 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ4 11:11 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ4_SET 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ5 12:12 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ5_SET 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ6 13:13 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ6_SET 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ7 14:14 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ7_SET 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ8 15:15 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_EXT_EXTIRQ8_SET 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_DMA 16:16 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSSET_DMA_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR 0x00409004 /* -W-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_GPTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_WDTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_MTHD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_HALT_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXTERR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_SWGEN0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_SWGEN1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT 15:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCLR_DMA_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT 0x00409008 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_GPTMR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_GPTMR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_WDTMR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_WDTMR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_MTHD_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_MTHD_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_CTXSW_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_CTXSW_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_HALT_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_HALT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXTERR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXTERR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_SWGEN0_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_SWGEN0_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_SWGEN1_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_SWGEN1_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT 15:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_DMA_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT_DMA_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE 0x0040900c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE__PRIV_LEVEL_MASK 0x00409290 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_GPTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_MTHD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_MTHD_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_MTHD_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_CTXSW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_HALT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_HALT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_HALT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXTERR_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_INIT 0xfc /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ1 8:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ2 9:9 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ3 10:10 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ4 11:11 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ5 12:12 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ6 13:13 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ7 14:14 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ8 15:15 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_DMA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_DMA_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE_LVL_DMA_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK 0x004090e0 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK__PRIV_LEVEL_MASK 0x004091a4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_GPTMR_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_GPTMR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_WDTMR_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_WDTMR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_MTHD_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_MTHD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_CTXSW_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_CTXSW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_HALT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_HALT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXTERR_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXTERR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_ENABLE 0xff /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_DISABLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ1 8:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ2 9:9 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ3 10:10 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ4 11:11 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ4_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ4_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ5 12:12 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ5_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ5_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ6 13:13 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ6_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ6_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ7 14:14 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ7_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ7_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ8 15:15 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ8_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_EXT_EXTIRQ8_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_DMA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQSCMASK_DMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET 0x00409010 /* -W-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET__PRIV_LEVEL_MASK 0x00409290 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_GPTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_WDTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_MTHD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_HALT 4:4 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_HALT_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXTERR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_SWGEN0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_SWGEN1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT 15:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_DMA 16:16 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMSET_DMA_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR 0x00409014 /* -W-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR__PRIV_LEVEL_MASK 0x00409290 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_GPTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_WDTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_MTHD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_HALT_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXTERR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_SWGEN0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_SWGEN1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT 15:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_EXT_EXTIRQ8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMCLR_DMA_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK 0x00409018 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_GPTMR_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_GPTMR_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_WDTMR_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_WDTMR_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_MTHD_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_MTHD_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_CTXSW_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_CTXSW_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_HALT 4:4 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_HALT_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_HALT_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXTERR_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXTERR_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_SWGEN0_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_SWGEN0_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_SWGEN1_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_SWGEN1_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT 15:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_DMA 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_DMA_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK_DMA_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST 0x0040901c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST__PRIV_LEVEL_MASK 0x00409290 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_GPTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_GPTMR_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_WDTMR_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_MTHD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_MTHD_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_MTHD_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_CTXSW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_CTXSW_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_HALT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_HALT_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_HALT_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXTERR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXTERR_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT 15:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_MTHD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_HALT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT 31:24 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST2 0x0040903c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST2__PRIV_LEVEL_MASK 0x00409290 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST2_HOST_DMA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST2_HOST_DMA_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST2_HOST_DMA_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST2_TARGET_DMA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRINT 0x00409020 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRINT__PRIV_LEVEL_MASK 0x004091a0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRVAL 0x00409024 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRVAL__PRIV_LEVEL_MASK 0x004091a0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRCTL 0x00409028 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRCTL__PRIV_LEVEL_MASK 0x004091a0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRCTL_GPTMREN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER0 0x0040902c /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER0__PRIV_LEVEL_MASK 0x004091bc /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER0_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER1 0x00409030 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER1__PRIV_LEVEL_MASK 0x004091bc /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PTIMER1_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRVAL 0x00409034 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRVAL__PRIV_LEVEL_MASK 0x0040929c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRCTL 0x00409038 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRCTL__PRIV_LEVEL_MASK 0x0040929c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRCTL_WDTMREN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDDATA 0x00409064 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDDATA__PRIV_LEVEL_MASK 0x00409294 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDID 0x00409068 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDID__PRIV_LEVEL_MASK 0x00409294 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDID_ID 11:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDID_PRIV 15:15 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDID_PRIV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDID_PRIV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDID_WPEND 16:16 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDID_WPEND_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDID_WPEND_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDWDAT 0x0040906c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDWDAT__PRIV_LEVEL_MASK 0x00409294 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCOUNT 0x00409070 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK 0x00409294 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDCOUNT_COUNT_INIT 0x0000 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDPOP 0x00409074 /* -W-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDPOP__PRIV_LEVEL_MASK 0x00409294 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDPOP_POP 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDPOP_POP_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDPOP_POP_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDRAMSZ 0x00409078 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK 0x00409294 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX 0x00409050 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX__PRIV_LEVEL_MASK 0x00409294 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX_CTXVLD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX_CTXVLD_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX_CTXVLD_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX_CTXTGT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CURCTX_CTXPTR_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX 0x00409054 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX__PRIV_LEVEL_MASK 0x00409294 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX_CTXVLD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX_CTXVLD_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX_CTXVLD_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX_CTXTGT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX_CTXPTR_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CTXACK 0x00409058 /* -W-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CTXACK__PRIV_LEVEL_MASK 0x00409294 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CTXACK_SAVE_ACK_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CTXACK_SAVE_ACK_CLEAR 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CTXACK_REST_ACK_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CTXACK_REST_ACK_CLEAR 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x00409040 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x00409044 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN 0x00409048 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN__PRIV_LEVEL_MASK 0x00409294 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_CTXEN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_CTXEN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_CTXEN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_MTHDEN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_MTHDEN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_MTHDEN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_PRIV_POSTWR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_CTXSW_NACK_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_CTXSW_NACK_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x0040904c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE__PRIV_LEVEL_MASK 0x004091e0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_FHSTATE 0x0040905c /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_FHSTATE__PRIV_LEVEL_MASK 0x004091e4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_FHSTATE_STALL_REQ_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_FHSTATE_STALL_REQ_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE 0x00409060 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE__PRIV_LEVEL_MASK 0x004093d0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRIVSTATE_PRIV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SFTRESET 0x0040907c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SFTRESET__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SFTRESET_EXT 0:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SFTRESET_EXT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SFTRESET_EXT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x004090a4 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_STALLREQ_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_STALLREQ_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_STALLACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL_STALLACK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ADDR 0x004090ac /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ADDR__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ADDR_LSB 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ADDR_LSB_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ADDR_MSB 11:6 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ADDR_MSB_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ADDR_EXT 11:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x0040910c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x00409110 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x00409114 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS_OFFS_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x00409118 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_FULL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_FULL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IDLE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IDLE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_NOTIFY_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_NOTIFY_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE_4B 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE_8B 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE_16B 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE_32B 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE_64B 0x4 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE_128B 0x5 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE_256B 0x6 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_ERROR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_ERROR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x0040911c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB 0x00409120 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP 0x00409124 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBRD_LOW 0x004092c0 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBRD_HIGH 0x004092c4 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBWR_LOW 0x004092c8 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBWR_HIGH 0x004092cc /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBRD_LOW 0x004092d0 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBRD_HIGH 0x004092d4 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBWR_LOW 0x004092d8 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBWR_HIGH 0x004092dc /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL 0x004092e0 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_ERR_TAG_HIGH 0x004092e4 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_ERR_TAG_LOW 0x004092e8 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK 0x00409190 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x00409180+(i)*16) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC__PRIV_LEVEL_MASK NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 23:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCR 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_SECURE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_SECURE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_SEC_LOCK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_SEC_LOCK_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x00409184+(i)*16) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMD__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMD__PRIV_LEVEL_MASK NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMD_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x00409188+(i)*16) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMT__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMT__PRIV_LEVEL_MASK NV_PGRAPH_PRI_FECS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_FAULT_CORRECTED 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_FAULT_CORRECTED_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_FAULT_UNCORRECTED 17:17 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_FAULT_UNCORRECTED_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x004091c0+(i)*8) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC__PRIV_LEVEL_MASK NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_ADDRESS_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS_INIT 0x00 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 23:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK_INIT 0x0000 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCR 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_SETTAG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_SETTAG_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_SETTAG_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_SETLVL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_SETLVL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_SETLVL_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_VA 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_VA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_VA_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_VA_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_MISS 29:29 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_MISS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_MISS_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_MULTIHIT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_MULTIHIT_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_LVLERR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_LVLERR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x004091c4+(i)*8) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMD__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMD__PRIV_LEVEL_MASK NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMD_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMT(i) (0x00409210+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMT__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMT__PRIV_LEVEL_MASK NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMT_TAG 15:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMT_FAULTED 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEMT_FAULTED_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEML(i) (0x004092a0+(i)*4) /* -W-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEML__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEML__PRIV_LEVEL_MASK NV_PGRAPH_PRI_FECS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEML_LVL 2:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_DUMMY 0x00409258 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK 0x00409284 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_DUMMY 0x004091b4 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK 0x00409280 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x00409300+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK 0x004093f0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x00409310+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK 0x004093f4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x00409320+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x004093f8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x00409330+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK 0x004093fc /* */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRGNVER 0x004093d4 /* R-I4R */ #define NV_PGRAPH_PRI_FECS_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PRGNVER_MAJOR_DEFT 0x2 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PRGNVER_MINOR_DEFT 0x0000 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PRGNVER_BUGFIX_DEFT 0x0000 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x00409108 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1 0x0040912c /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_INIT 0x6 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_1_0 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_2_0 0x2 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_3_0 0x3 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_4_0 0x4 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_5_0 0x5 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_6_0 0x6 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_7_0 0x7 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x2 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x2 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x3 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x2 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x3 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_IMEM_PORTS_INIT 0x1 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_DMEM_PORTS_INIT 0x4 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_TAG_WIDTH_INIT 0x10 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x1 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2 0x004090f4 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_SHA 0:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_SHA_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_SHA_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_BMEM 1:1 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_BMEM_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_BMEM_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_PKCBOOT_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_PKCBOOT_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_DBGMODE_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_DBGMODE_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_KMEM 4:4 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_KMEM_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_KMEM_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_VHR 7:7 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_VHR_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_VHR_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_HS 8:8 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_HS_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_HS_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_SECUREBUS_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_SECUREBUS_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_RISCV 10:10 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_RISCV_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_RISCV_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG3 0x00409278 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_CGCTL 0x004090a0 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CGCTL_CG_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2 0x00409134 /* RWI4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2__PRIV_LEVEL_MASK 0x004091e8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG 17:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_ENABLED 0x00000 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_DISABLED 0x1ffff /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG__PROD 0x000a0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FBIF_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG2_SLCG_FBIF_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL 0x00409240 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL__PRIV_LEVEL_MASK 0x00409298 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_LSMODE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_LSMODE_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_LSMODE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_HSMODE 1:1 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_HSMODE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_HSMODE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_LSMODE_LEVEL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_UCODE_LEVEL 5:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_UCODE_LEVEL_INIT 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_AUTH_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL_AUTH_EN_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL1 0x00409250 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL1__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL1_CSBLVL_MASK_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SCTL1_EXTLVL_MASK_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL 0x004090e4 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL__PRIV_LEVEL_MASK 0x004090e8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_TRACEPC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_TRACEPC_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_SP_MIN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_HSCTL_SP_MIN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_ERB 0x004092ec /* -W-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_ERB_DATA 31:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_ERB_DATA_CORRECTED_ERR 0xeafe0c00 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_ERB_DATA_UNCORRECTED_ERR 0xeafe1cff /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX 0x004092f0 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_DATA 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRADDR 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRADDR_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE 31:24 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_PF 0xf0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_PF 0xf1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_SCP 0xf2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_SCP 0xf3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_SCP 0xf3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_DMA 0xf4 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_DMA 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_DMA 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_PMB 0xf6 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_PMB 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_PMB 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_LDST 0xf8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_PMB 0xf9 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_DMA 0xfa /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_SCP 0xfb /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_CORRECTED_SHA 0xfc /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_UNCORRECTED_SHA 0xfd /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_CORRECTED_RISCV 0xfe /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_UNCORRECTED_RISCV 0xff /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IROM 0xe0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IROM 0xe1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL 0x004092f4 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL__PRIV_LEVEL_MASK 0x004091b0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_FUSE_OPT_ECC_EN 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_FUSE_OPT_ECC_EN_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_IMEM_ECC_DIS 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_IMEM_ECC_DIS_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_CTRL_IMEM_ECC_DIS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_ERR_ADDR 0x004092f8 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_ERR_ADDR_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_ERR_ADDR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_ERR_ADDR_HI 0x004092fc /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_ERR_ADDR_HI_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SAFETY_ERR_ADDR_HI_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_OS 0x00409080 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_OS_VERSION 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_RM 0x00409084 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_RM_CONFIG 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SOFT_PM 0x00409088 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SOFT_PM__PRIV_LEVEL_MASK 0x004091ec /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SOFT_PM_TRIGGER_START_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SOFT_PM_TRIGGER_END_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SOFT_PM_PROBE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SOFT_MODE 0x0040908c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SOFT_MODE__PRIV_LEVEL_MASK 0x004091ec /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SOFT_MODE_PROBE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM 0x004090a8 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM__PRIV_LEVEL_MASK 0x004091ec /* */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_CODE 0x01 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x02 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x03 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x04 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x05 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_IPND 0x06 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x07 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_SB 0x08 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x09 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0a /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0b /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0c /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0d /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0e /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0f /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x10 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x11 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x4 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x5 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x6 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x7 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x9 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0xa /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0xb /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_DSTAT_SEL 19:17 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_DSTAT_SEL_RREQ 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_DSTAT_SEL_WREQ 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_DSTAT_SEL_RREQ_SC 0x4 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_DSTAT_SEL_WREQ_SC 0x5 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x4 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x5 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY 0x6 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x7 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT_SC 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x9 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0xa /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0xb /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0xd /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY_SC 0xe /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1 0x00409090 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1__PRIV_LEVEL_MASK 0x00409294 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x0040 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1_CTXSW_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x00409094 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN 0x00409270 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN__PRIV_LEVEL_MASK 0x004091f0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SP_MIN_VALUE_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI 0x004090d0 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI__PRIV_LEVEL_MASK 0x004091f4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXPC 19:0 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_TRAP0 0x00 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_TRAP1 0x01 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_TRAP2 0x02 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_TRAP3 0x03 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_ILL_INS 0x08 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_INV_INS 0x09 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_MISS_INS 0x0a /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0b /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0d /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0f /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x10 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x11 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x12 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x13 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXCAUSE_DMEM_FAULT_INS 0x14 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI2 0x004090bc /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI2__PRIV_LEVEL_MASK 0x004091f4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR 0x004090d4 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR__PRIV_LEVEL_MASK 0x004091f8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_SIGPASS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_SVEC_SPR_SIGPASS_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x00409100 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL__PRIV_LEVEL_MASK 0x00409288 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_IINVAL_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_IINVAL_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_SRESET_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_SRESET_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_HRESET_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_HRESET_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_HALTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_HALTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STOPPED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STOPPED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS 0x00409130 /* -W-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_STACKCFG 0x00409138 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_STACKCFG__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_STACKCFG_BOTTOM_INIT 0x000000 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_STACKCFG_SPEXC_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_STACKCFG_SPEXC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_STACKCFG_SPEXC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x00409104 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC__PRIV_LEVEL_MASK 0x00409194 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL 0x00409254 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL__PRIV_LEVEL_MASK 0x004091a8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_VAL 9:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_VAL_INIT 0x000 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_TRACE_MODE_FULL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_TRACE_MODE_STACK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_CYA 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_CYA_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DBGCTL_CYA_ENABLE 0x8afe /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1 0x00409098 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1__PRIV_LEVEL_MASK 0x004091fc /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT1_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2 0x0040909c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2__PRIV_LEVEL_MASK 0x004091fc /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT2_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3 0x004090b0 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3__PRIV_LEVEL_MASK 0x004091fc /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT3_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4 0x004090b4 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4__PRIV_LEVEL_MASK 0x004091fc /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT4_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5 0x004090b8 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5__PRIV_LEVEL_MASK 0x004091fc /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IBRKPT5_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD 0x00409200 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD__PRIV_LEVEL_MASK 0x00409220 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_STOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RUN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_JRUN 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RUNB 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_JRUNB 0x4 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_STEP 0x5 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_JSTEP 0x6 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_EMASK 0x7 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RREG 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_WREG 0x9 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RDM 0xa /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_WDM 0xb /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RCM 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_WCM 0xd /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RSTAT 0xe /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_SBU 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_SZ_B 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_SZ_HW 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_SZ_W 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_REG15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_IV0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_IV1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_EV 0x13 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_SP 0x14 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_PC 0x15 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_IMB 0x16 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_DMB 0x17 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_CSW 0x18 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_CCR 0x19 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_SEC 0x1a /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_CTX 0x1b /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_EXCI 0x1c /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_SEC1 0x1e /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_IMB1 0x1e /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_DMB1 0x1f /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_RSTAT0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_RSTAT1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_RSTAT2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_RSTAT3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_RSTAT4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_RSTAT5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_WB0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_WB1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_WB2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX_WB3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_FAULTED 13:13 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_FAULTED_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_FAULTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_FAULTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_ERROR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_ERROR_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_RDVLD_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_RDVLD_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_PARM 31:16 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK 31:16 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_ADDR 0x00409204 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_ADDR__PRIV_LEVEL_MASK 0x00409220 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_WDATA 0x00409208 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_WDATA__PRIV_LEVEL_MASK 0x00409220 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA 0x0040920c /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA__PRIV_LEVEL_MASK 0x00409220 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 0x2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 0x2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 0x2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 0x2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 0x2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 0x3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 0x4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 0x5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 0x6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 0x7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 0x2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 0x3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 0x2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0 0x004090d8 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0__PRIV_LEVEL_MASK 0x00409224 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_VALID 28:28 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3 0x004090dc /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEIDX 0x00409148 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEIDX__PRIV_LEVEL_MASK 0x0040919c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEIDX_CNT_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEIDX_IDX_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEPC 0x0040914c /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEPC__PRIV_LEVEL_MASK 0x0040919c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEPC_PC 23:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEINFO 0x0040917c /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEINFO__PRIV_LEVEL_MASK 0x0040919c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL 0x00409140 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_CMD 26:24 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_CMD_NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_CMD_IMINV 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_CMD_IMBLK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_CMD_IMTAG 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x4 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_DEBUG 0x0040915c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_DEBUG_CMD_NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMSTAT 0x00409144 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IMSTAT__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMSTAT_VAL 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLRNG0 0x00409150 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLRNG0_TAG_LO 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLRNG0_TAG_LO_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLRNG0_TAG_HI 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLRNG0_TAG_HI_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLRNG1 0x00409154 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLRNG1_TAG_LO 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLRNG1_TAG_LO_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLRNG1_TAG_HI 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLRNG1_TAG_HI_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLCTL 0x00409158 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLCTL__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_IMFILLCTL_NBLOCKS_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMCTL 0x00409260 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMCTL__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMCTL_CMD 26:24 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMCTL_CMD_NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMCTL_CMD_DMINV 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMCTL_CMD_DMBLK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMCTL_CMD_DMTAG 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x4 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMCTL_CMD_DMCLEAN 0x5 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMCTL_CMD_DMLVL 0x6 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_DMSTAT 0x00409264 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMSTAT__PRIV_LEVEL_MASK 0x0040928c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMSTAT_VAL 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMVACTL 0x00409268 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_DMVACTL__PRIV_LEVEL_MASK 0x00409198 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_DMVACTL_BOUND_INIT 0x00000020 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERRSTAT 0x00409244 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK 0x0040922c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERRSTAT_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERRSTAT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERRSTAT_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERRSTAT_VALID_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERRSTAT_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERRSTAT_VALID_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_ADDR 0x0040924c /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK 0x0040922c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_INFO 0x00409248 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK 0x0040922c /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x00409b00 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR_0 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_SYS_MEM_COHERENT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_SYS_MEM_NONCOHERENT 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_NEW_CTX 0x00409b04 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR_0 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET_VID_MEM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET_SYS_MEM_COHERENT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET_SYS_MEM_NONCOHERENT 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x00409500 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_METHOD_DATA_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_METHOD_DATA_V_ELPG_LIST 0x00000001 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_DATA_V_GPCRG_LIST 0x00000002 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_DATA_A 0x0040950c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_METHOD_DATA_A_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x00409504 /* -W-4R */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_PRIV 31:31 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_NOP 0x000 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_SAVE 0x001 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_RESTORE 0x002 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 0x003 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER_ONLY 0x060 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 0x004 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE_NEW 0x007 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_UNHALT_PIPELINE 0x005 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_CONTEXT_RESET 0x006 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 0x010 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_PREPARE_FOR_INITIALIZATION 0x011 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_SAVE_ONLY 0x008 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 0x009 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_SAVE_RESTORE 0x00a /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI 0x00b /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_NOCHSW_MODE 0x00c /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_ALLOW_SWDX_DIRECT_CTXSW_SKIP 0x00d /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISABLE_RAMCHAIN_SCRUB 0x00e /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISABLE_SWDX_DIRECT_CTXSW_SCRUB 0x00f /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 0x015 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 0x016 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x025 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PREEMPTION_IMAGE_SIZE 0x01a /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_INIT_MME_SHADOW_RAM 0x02a /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_INIT_BUNDLE_DECODERS 0x02b /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_LO 0x02c /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_HI 0x02d /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_SMC_LTS_MASK_INDEX 0x02e /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_ASSIGN_SMC_LTS_MASK 0x02f /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x030 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x031 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x032 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SAVE_REGLIST 0x033 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_REGLIST 0x034 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_UCODE_RECONFIG 0x035 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_CHECK_GPCCS_INIT_COMPLETE 0x036 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x038 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x039 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_CONFIGURE_INTERRUPT_COMPLETION_OPTION 0x03a /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISABLE_ACCESS_COUNTER 0x03c /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_INSTANCE 0x03d /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_VIRTUAL_ADDRESS_LO 0x03e /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_VIRTUAL_ADDRESS_HI 0x03f /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_METHOD_INIT 0x040 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BUNDLE_INIT_COMPUTE 0x041 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BUNDLE_INIT_2D 0x042 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BUNDLE_INIT_3D 0x043 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BUNDLE_INIT_MEM2MEM 0x044 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_SIZE 0x054 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_LO 0x055 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_LO 0x056 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_CRC_CHECK_CALCULATE 0x057 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_HI 0x058 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_HI 0x059 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_INJECT_STACK_CANARY_ERROR 0x070 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SHUTDOWN_UCODE 0x012 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_CONTEXT_ADDRESS 0x013 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_CONTEXT_ADDRESS_HI 0x01e /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_PRIV_OFFSET 0x014 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_GFXP_CONTEXT_ADDRESS 0x01c /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_GFXP_CONTEXT_ADDRESS_HI 0x01f /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_GFXP_RC_OFFSET 0x01d /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_ZCULL_CONTEXT_ADDRESS 0x017 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_ZCULL_CONTEXT_ADDRESS_HI 0x022 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_ZCULL_PRIV_OFFSET 0x018 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_ZCULL_MODE 0x019 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_CBC_CLEAR_ACTIVE 0x01b /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_FMODEL_TESTS 0x020 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x021 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_GFID 0x024 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_PM_CONTEXT_ADDRESS 0x026 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_PM_CONTEXT_ADDRESS_HI 0x023 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_PM_PRIV_OFFSET 0x027 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SEND_PM_MODE 0x028 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_TEST_MODE 0x029 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_CONTROL_ZBC_TABLES_SAVE 0x061 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SAVE_SM_PERF_COUNTERS_START 0x062 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SAVE_SM_PERF_COUNTERS_END 0x063 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_SM_PERF_COUNTERS 0x064 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SMPC_GLOBAL_MODE_START 0x069 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SMPC_GLOBAL_MODE_STOP 0x06a /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_HWPM_CONTROL_REGS 0x065 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_PERFORM_PRE_SAVE_TASKS 0x06b /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_PERFORM_PRE_RESTORE_TASKS 0x06c /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A 0x00409508 /* -W-4R */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_PRIV 31:31 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR 11:0 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_NOP 0x000 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_WFI_SAVE 0x001 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_WFI_RESTORE 0x002 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_BIND_POINTER 0x003 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_BIND_POINTER_ONLY 0x060 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_HALT_PIPELINE 0x004 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_HALT_PIPELINE_NEW 0x007 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_UNHALT_PIPELINE 0x005 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_CONTEXT_RESET 0x006 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_DISCOVER_IMAGE_SIZE 0x010 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_PREPARE_FOR_INITIALIZATION 0x011 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_WFI_SAVE_ONLY 0x008 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_WFI_GOLDEN_SAVE 0x009 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_WFI_SAVE_RESTORE 0x00a /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_WFI 0x00b /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_NOCHSW_MODE 0x00c /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_ALLOW_SWDX_DIRECT_CTXSW_SKIP 0x00d /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_DISABLE_RAMCHAIN_SCRUB 0x00e /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_DISABLE_SWDX_DIRECT_CTXSW_SCRUB 0x00f /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_RESTORE_GOLDEN 0x015 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_DISCOVER_ZCULL_IMAGE_SIZE 0x016 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_DISCOVER_PM_IMAGE_SIZE 0x025 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_DISCOVER_PREEMPTION_IMAGE_SIZE 0x01a /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_INIT_MME_SHADOW_RAM 0x02a /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_INIT_BUNDLE_DECODERS 0x02b /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_LO 0x02c /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_HI 0x02d /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SET_SMC_LTS_MASK_INDEX 0x02e /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_ASSIGN_SMC_LTS_MASK 0x02f /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x030 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SET_REGLIST_BIND_INSTANCE 0x031 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x032 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SAVE_REGLIST 0x033 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_RESTORE_REGLIST 0x034 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_UCODE_RECONFIG 0x035 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_CHECK_GPCCS_INIT_COMPLETE 0x036 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_STOP_CTXSW 0x038 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_START_CTXSW 0x039 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_CONFIGURE_INTERRUPT_COMPLETION_OPTION 0x03a /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_DISABLE_ACCESS_COUNTER 0x03c /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_SIZE 0x054 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_LO 0x055 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_LO 0x056 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_CRC_CHECK_CALCULATE 0x057 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_HI 0x058 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_HI 0x059 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_READ_PHYS_MEM 0x067 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_ENABLE_PHYS_MEM_READS 0x068 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SHUTDOWN_UCODE 0x012 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_CONTEXT_ADDRESS 0x013 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_CONTEXT_ADDRESS_HI 0x01e /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_PRIV_OFFSET 0x014 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_GFXP_CONTEXT_ADDRESS 0x01c /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_GFXP_CONTEXT_ADDRESS_HI 0x01f /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_GFXP_RC_OFFSET 0x01d /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_ZCULL_CONTEXT_ADDRESS 0x017 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_ZCULL_CONTEXT_ADDRESS_HI 0x022 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_ZCULL_PRIV_OFFSET 0x018 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_ZCULL_MODE 0x019 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_CBC_CLEAR_ACTIVE 0x01b /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_FMODEL_TESTS 0x020 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SET_WATCHDOG_TIMEOUT 0x021 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SET_GFID 0x024 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_PM_CONTEXT_ADDRESS 0x026 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_PM_CONTEXT_ADDRESS_HI 0x023 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_PM_PRIV_OFFSET 0x027 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SEND_PM_MODE 0x028 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_TEST_MODE 0x029 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_PCIE_TRAINING 0x050 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_CONTROL_ZBC_TABLES_SAVE 0x061 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SAVE_SM_PERF_COUNTERS_START 0x062 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_SAVE_SM_PERF_COUNTERS_END 0x063 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_RESTORE_SM_PERF_COUNTERS 0x064 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_RESTORE_HWPM_CONTROL_REGS 0x065 /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_PERFORM_PRE_SAVE_TASKS 0x06b /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_PERFORM_PRE_RESTORE_TASKS 0x06c /* -W--V */ #define NV_PGRAPH_PRI_FECS_METHOD_PUSH_A_ADR_INJECT_STACK_CANARY_ERROR 0x070 /* -W--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SM_CTL 0x00409b08 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_SM_CTL_TRIVIAL_ACK 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SM_CTL_TRIVIAL_ACK_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SM_CTL_TRIVIAL_ACK_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SM_CTL_TRIVIAL_ACK__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_ACK 0x00409b0c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_ACK_CTXSW 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_ACK_CTXSW_I 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_ACK_CTXSW_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_ACK_STALL 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_ACK_STALL_I 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_ACK_STALL_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_ACK_FE_INTERVAL_TIMER 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_ACK_FE_INTERVAL_TIMER_I 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_ACK_FE_INTERVAL_TIMER_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_HOST_ACK 0x00409b70 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_HOST_ACK_PREEMPTED 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_HOST_ACK_PREEMPTED_TRUE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_HOST_ACK_PREEMPTED_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_CURRENT_CTX_ID 0x00409b74 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_CURRENT_CTX_ID_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_CURRENT_CTX_ID_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_GFID 0x00409b78 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_GFID_V 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_GFID_V_ZERO 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_DATA 0x004098b8 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_DATA_FIELD 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG 0x004098bc /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_NONE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_ENGINE_RESET 0x01 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CONTEXT_RESET 0x02 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_INSTANCE_BIND 0x03 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_SAVE_ENGINE_REGS 0x06 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_RESTORE_ENGINE_REGS 0x07 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GOLDEN_SAVE 0x08 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_SAVE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_SAVE 0x10 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_SAVE 0x11 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_SAVE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_SAVE_ONLY 0x0a /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_SAVE_ONLY 0x05 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_SAVE_ONLY 0x12 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_SAVE_ONLY 0x13 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_RESTORE 0x0f /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_RESTORE 0x14 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_RESTORE 0x15 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_RESTORE 0x0b /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GOLDEN_RESTORE 0x0c /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_PATCH_BUFFER_END 0x0d /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_STREAM_TAG_ACTION_CTXSW_END 0x04 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL 0x00409c08 /* -W-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_PMU_SLAVE_ACK 0:0 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_PMU_SLAVE_ACK_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_PMU_SLAVE_ACK_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_PMU_MASTER_REQ 1:1 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_PMU_MASTER_REQ_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_PMU_MASTER_REQ_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_WFI_REQ 2:2 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_WFI_REQ_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_WFI_REQ_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_HALT_REQ 3:3 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_HALT_REQ_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_HALT_REQ_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_WFF_REQ 5:5 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_WFF_REQ_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_WFF_REQ_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_WFF_PREEMPT 6:6 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_WFF_PREEMPT_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_WFF_PREEMPT_ENABLED 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_GRAPHICS_PREEMPTION_CONTROL 9:8 /* -W-VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_GRAPHICS_PREEMPTION_CONTROL_WFI 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_GRAPHICS_PREEMPTION_CONTROL_GFXP 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_COMPUTE_PREEMPTION_CONTROL 13:12 /* -W-VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_COMPUTE_PREEMPTION_CONTROL_WFI 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_COMPUTE_PREEMPTION_CONTROL_CTA 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_INTERFACE_CTL_FE_COMPUTE_PREEMPTION_CONTROL_CILP 0x2 /* -W--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_FORCE_NONIDLE 0x00409424 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_FORCE_NONIDLE_OVERRIDE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_FORCE_NONIDLE_OVERRIDE_ACTIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_FORCE_NONIDLE_OVERRIDE_INACTIVE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x00409420 /* R--4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE_FALCON 0:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE_FORCED 1:1 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE_RC_LANES 2:2 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE_PRIV_SEQUENCER 3:3 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE_GPCCS 15:15 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x00409c00 /* R--4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CTXSW_REQ 0:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CTXSW_REQ_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CTXSW_REQ_REQ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CTXSW_VLD 1:1 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CTXSW_VLD_INVALID 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CTXSW_VLD_VALID 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CTXSW_ACK 2:2 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CTXSW_ACK_NOACK 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CTXSW_ACK_ACK 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CTXSW_INT 3:3 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CTXSW_INT_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CTXSW_INT_REQ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_STALL_REQ 4:4 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_STALL_REQ_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_STALL_REQ_REQ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_STALL_ACK 5:5 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_STALL_ACK_NOACK 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_STALL_ACK_ACK 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CONTEXT_PREEMPTED 6:6 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CONTEXT_PREEMPTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_CONTEXT_PREEMPTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_PMU_SLAVE_INTERRUPT_REQ 7:7 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_PMU_SLAVE_INTERRUPT_REQ_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_PMU_SLAVE_INTERRUPT_REQ_REQ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_PMU_SLAVE_INTERRUPT_ACK 8:8 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_PMU_SLAVE_INTERRUPT_ACK_NOACK 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_PMU_SLAVE_INTERRUPT_ACK_ACK 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_PMU_MASTER_INTERRUPT_REQ 9:9 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_PMU_MASTER_INTERRUPT_REQ_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_PMU_MASTER_INTERRUPT_REQ_REQ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_PMU_MASTER_INTERRUPT_ACK 10:10 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_PMU_MASTER_INTERRUPT_ACK_NOACK 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_PMU_MASTER_INTERRUPT_ACK_ACK 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FIRMWARE_METHOD_INTERRUPT 11:11 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FIRMWARE_METHOD_INTERRUPT_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FIRMWARE_METHOD_INTERRUPT_REQ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_UNIMPLEMENTED_METHOD_INTERRUPT 12:12 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_UNIMPLEMENTED_METHOD_INTERRUPT_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_UNIMPLEMENTED_METHOD_INTERRUPT_REQ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_WFI_REQ 13:13 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_WFI_REQ_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_WFI_REQ_REQ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_WFI_ACK 14:14 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_WFI_ACK_NOACK 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_WFI_ACK_ACK 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_HALT_REQ 15:15 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_HALT_REQ_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_HALT_REQ_REQ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_HALT_ACK 16:16 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_HALT_ACK_NOACK 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_HALT_ACK_ACK 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_GR_INTR 17:17 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_GR_INTR_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_GR_INTR_REQ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_DFD_INTR 18:18 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_DFD_INTR_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_DFD_INTR_REQ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_INTERVAL_TIMER_INTR 19:19 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_INTERVAL_TIMER_INTR_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_FE_INTERVAL_TIMER_INTR_REQ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_RING_MANAGE_STATUS 23:23 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_RING_MANAGE_STATUS_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_RING_MANAGE_STATUS_SUCCESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_TBCS_ABORT_CTXSW 24:24 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_TBCS_ABORT_CTXSW_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_TBCS_ABORT_CTXSW_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_TBCS_NACK_RECEIVED 25:25 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_TBCS_NACK_RECEIVED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_TBCS_NACK_RECEIVED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_TBCS_NACK_ACTION 26:26 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_TBCS_NACK_ACTION_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_TBCS_NACK_ACTION_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_TBCS_DUT_FAULTED 27:27 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_TBCS_DUT_FAULTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_TBCS_DUT_FAULTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_GFX_PREEMPTION_TYPE_ISSUED_BY_FE 29:28 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_GFX_PREEMPTION_TYPE_ISSUED_BY_FE_WFI 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_GFX_PREEMPTION_TYPE_ISSUED_BY_FE_GFXP 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_COMPUTE_PREEMPTION_TYPE_ISSUED_BY_FE 31:30 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_COMPUTE_PREEMPTION_TYPE_ISSUED_BY_FE_WFI 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_COMPUTE_PREEMPTION_TYPE_ISSUED_BY_FE_CTA 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0_COMPUTE_PREEMPTION_TYPE_ISSUED_BY_FE_CILP 0x2 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x00409400 /* R--4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_CONSTANT_0 0:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_LOCAL_PRIV_ERROR 1:1 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_RC_LANES 2:2 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_RC_LANES_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_RC_LANES_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_CONTEXT_RESET 3:3 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_CONTEXT_RESET_ACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_CONTEXT_RESET_DISABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL 4:4 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL_BUSY 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL_IDLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_SEQUENCER 5:5 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_SEQUENCER_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_SEQUENCER_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_READ 6:6 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_READ_DONE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_READ_NOT_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_WRACK 7:7 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_WRACK_DONE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_WRACK_NOT_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_COMP0 8:8 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_COMP0_DONE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_COMP0_NOT_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_COMP1 9:9 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_COMP1_DONE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_COMP1_NOT_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_DFD_TRIGGER 10:10 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_DFD_TRIGGER_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_DFD_TRIGGER_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_WATCHDOG_TRIGGER 11:11 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_WATCHDOG_TRIGGER_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_WATCHDOG_TRIGGER_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_NACK 13:13 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_HALTED 14:14 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_FLUSH_WHEN_BUSY 15:15 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_CTXSW_CHECKSUM_MISMATCH 16:16 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL 28:28 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL_VIOLATION 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_ERROR 29:29 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_DECODE_TRAP 30:30 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_WRITE_DROPPED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_UCODE_TRAP 31:31 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_UCODE_TRAP_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_PRIV_UCODE_TRAP_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG 0x00409404 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SEL0_BIT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SEL0_BIT_V0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SEL0_STATUS_REG 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_1 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SEL1_BIT 12:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SEL1_BIT_V0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SEL1_STATUS_REG 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_1 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_COMBINATION 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_COMBINATION_OR 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_COMBINATION_AND 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SENSE 18:17 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SENSE_RISING_EDGE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SENSE_FALLING_EDGE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SENSE_LEVEL_1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_CFG_SENSE_LEVEL_0 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG 0x00409c14 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SEL0_BIT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SEL0_BIT_V0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SEL0_STATUS_REG 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_1 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SEL1_BIT 12:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SEL1_BIT_V0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SEL1_STATUS_REG 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_1 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_COMBINATION 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_COMBINATION_OR 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_COMBINATION_AND 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SENSE 18:17 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SENSE_RISING_EDGE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SENSE_FALLING_EDGE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SENSE_LEVEL_1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CFG_SENSE_LEVEL_0 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x00409c18 /* R--4R */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_CTXSW_INTR 15:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_CTXSW_INTR_NONE 0x0000 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_CTXSW_INTR0 0:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_CTXSW_INTR0_NOT_ASSERTED 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_CTXSW_INTR0_ASSERTED 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_FAULT_DURING_CTXSW 16:16 /* R--VF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_FAULT_DURING_CTXSW_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_FAULT_DURING_CTXSW_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 /* R--VF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 /* R--VF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_WATCHDOG 19:19 /* R--VF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_WATCHDOG_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_WATCHDOG_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_FLUSH_WHEN_BUSY 20:20 /* R--VF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_FLUSH_WHEN_BUSY_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_FLUSH_WHEN_BUSY_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_ECC_CORRECTED 21:21 /* R--VF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_ECC_CORRECTED_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_ECC_CORRECTED_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_ECC_UNCORRECTED 22:22 /* R--VF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_ECC_UNCORRECTED_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_ECC_UNCORRECTED_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET 0x00409c1c /* -W-4R */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR0 0:0 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR0_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR1 1:1 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR1_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR2 2:2 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR2_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR3 3:3 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR3_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR4 4:4 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR4_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR5 5:5 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR5_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR6 6:6 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR6_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR7 7:7 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR7_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR8 8:8 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR8_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR9 9:9 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR9_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR9_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR10 10:10 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR10_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR10_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR11 11:11 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR11_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR11_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR12 12:12 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR12_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR12_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR13 13:13 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR13_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR13_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR14 14:14 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR14_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR14_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR15 15:15 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR15_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_CTXSW_INTR15_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_FAULT_DURING_CTXSW 16:16 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_FAULT_DURING_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_FAULT_DURING_CTXSW_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_UMIMP_FIRMWARE_METHOD 17:17 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_UMIMP_FIRMWARE_METHOD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_UMIMP_FIRMWARE_METHOD_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_UMIMP_ILLEGAL_METHOD 18:18 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_UMIMP_ILLEGAL_METHOD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_UMIMP_ILLEGAL_METHOD_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_WATCHDOG 19:19 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_WATCHDOG_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_WATCHDOG_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_FLUSH_WHEN_BUSY 20:20 /* -W-VF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_FLUSH_WHEN_BUSY_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_SET_FLUSH_WHEN_BUSY_IGNORE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x00409c20 /* -W-4R */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR0 0:0 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR0_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR0_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR1 1:1 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR1_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR1_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR2 2:2 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR2_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR2_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR3 3:3 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR3_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR3_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR4 4:4 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR4_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR4_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR5 5:5 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR5_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR5_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR6 6:6 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR6_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR6_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR7 7:7 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR7_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR7_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR8 8:8 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR8_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR8_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR9 9:9 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR9_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR9_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR10 10:10 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR10_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR10_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR11 11:11 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR11_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR11_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR12 12:12 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR12_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR12_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR13 13:13 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR13_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR13_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR14 14:14 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR14_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR14_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR15 15:15 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR15_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_CTXSW_INTR15_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_FAULT_DURING_CTXSW 16:16 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_FAULT_DURING_CTXSW_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_FAULT_DURING_CTXSW_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_UMIMP_FIRMWARE_METHOD 17:17 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_UMIMP_FIRMWARE_METHOD_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_UMIMP_FIRMWARE_METHOD_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_UMIMP_ILLEGAL_METHOD 18:18 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_UMIMP_ILLEGAL_METHOD_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_UMIMP_ILLEGAL_METHOD_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_WATCHDOG 19:19 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_WATCHDOG_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_WATCHDOG_IGNORE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_FLUSH_WHEN_BUSY 20:20 /* -W-VF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_FLUSH_WHEN_BUSY_CLEAR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR_FLUSH_WHEN_BUSY_IGNORE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x00409c24 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR0_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR1_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR2_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR3_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR4 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR4_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR5_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR6_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR7_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR8 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR8_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR8_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR9 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR9_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR9_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR10 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR10_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR10_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR11 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR11_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR11_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR12 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR12_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR12_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR13 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR13_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR13_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR14 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR14_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR14_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR15 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR15_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_CTXSW_INTR15_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FLUSH_WHEN_BUSY 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FLUSH_WHEN_BUSY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FLUSH_WHEN_BUSY_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_ECC_CORRECTED 21:21 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_ECC_CORRECTED_ENABLE 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_ECC_CORRECTED_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_ECC_UNCORRECTED 22:22 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_ECC_UNCORRECTED_ENABLE 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_ECC_UNCORRECTED_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_WATCHDOG 0x00409430 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_WATCHDOG_COUNT 29:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_WATCHDOG_COUNT_V 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_WATCHDOG_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_WATCHDOG_ENABLE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_WATCHDOG_ENABLE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK 0x00409434 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_2_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_3_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_3_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_4 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_4_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_4_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_5_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_5_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_6_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_6_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_7_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_INT_ACK_7_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x00409614 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_HALT_SEQUENCER 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_HALT_SEQUENCER_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_HALT_SEQUENCER_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_ZCULL_RT_RESET 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_ZCULL_RT_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_ZCULL_RT_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_CTL_SIGS 0x0040988c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_CTL_SIGS_CTXSW_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_CTL_SIGS_CTXSW_FREEZE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_CTL_SIGS_CTXSW_FREEZE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x0040960c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID_V_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MINOR_REV_ID 0x00409610 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MINOR_REV_ID_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MINOR_REV_ID_V_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_EMUCRC_DATA 0x00409630 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_EMUCRC_DATA_V 31:0 /* RW-VF */ #define NV_PGRAPH_PRI_FECS_EMUCRC_CFG 0x00409634 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_EMUCRC_CFG_V 31:0 /* RW-VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x00409800+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 18 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_NONE 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 0x00000001 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 0x00000002 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_BIND_POINTER_PASS 0x00000010 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_BIND_POINTER_FAIL 0x00000021 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_MAGIC 0x12345678 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_WAIT_FOR_MODS 0x0000000f /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_STOP_WAIT_FOR_MODS 0x0000000e /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SYNC_POINT_1 0x00000005 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SYNC_POINT_2 0x00000006 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SYNC_POINT_3 0x00000007 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_INIT_FAILED 0x00000008 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_INVALID_METHOD 0x00000009 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_METHOD_QUEUE_OVERFLOW 0x00000010 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_INVALID_FIRMWARE_METHOD_PARAMETER 0x00000011 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SIDEBAND_METHOD_QUEUE_OVERFLOW 0x00000012 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FIRMWARE_METHOD_QUEUE_OVERFLOW 0x00000013 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_BECS_RC_NON_ZERO 0x00000014 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_BAD_CTXSW_IMAGE 0x00000015 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SECURE_FAIL_FECS 0x00000016 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SECURE_FAIL_GPCCS 0x00000017 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SECURE_FAIL_FECS_AND_GPCCS 0x00000018 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_GFXP_WITH_VPR_CONTEXT 0x00000019 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PRI_SEQ_ERROR 0x00000020 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_CTXSW_CHECKSUM_MISMATCH 0x00000021 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FALCON_CSB_ERROR 0x00000022 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PATCH_BUFFER_ACCESS_VIOLATION 0x00000023 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FALCON_STACK_CANARY_CHECK_FAILED 0x00000024 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SCRUB_STEP_CHECK_1_FAILED 0x00000025 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SCRUB_STEP_CHECK_2_FAILED 0x00000026 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_INDEX_OOB 0x00000027 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_POINTER_OVERFLOW 0x00000028 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_OFFSET_OVERFLOW 0x00000029 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_FULL 0x00000030 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_INVALID_ARBITER_COMMANDS 0x00000031 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_NUM_GPC_MISMATCH 0x00000032 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_NUM_TPC_MISMATCH 0x00000033 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_GFXP_IN_SMC_MODE 0x00000034 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_RESTORE_SMC_IN_LEGACY 0x00000035 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_RESTORE_LEGACY_IN_SMC 0x00000036 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SMC_LTS_MASK_INDEX_OUT_OF_BOUNDS 0x00000037 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SYS_RAMCHAIN_IMAGE_SIZE_MISMATCH 0x00000038 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_GPC_RAMCHAIN_IMAGE_SIZE_MISMATCH 0x00000039 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SYS_PRI_IMAGE_SIZE_MISMATCH 0x00000040 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_GPC_PRI_IMAGE_SIZE_MISMATCH 0x00000041 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_MAX_LTS_PER_LTC 0x00000042 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_NUM_PPC_MISMATCH 0x00000043 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_TRIVIAL_ACK_WITHOUT_NOCHSW 0x00000044 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_SECOND_RESTORE_WITH_NOCHSW 0x00000045 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_INVALID_PRIV_ACCESS_MAP_CONFIG 0x00000046 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_LTC_COUNT_OVERFLOW 0x00000047 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_REV_ID_CHECK_FAILED 0x00000048 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_CHIP_ID_CHECK_FAILED 0x00000049 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_ILLEGAL_FALCON_LEVEL 0x00000050 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PRIV_SEC_NOT_ENABLED 0x00000051 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FIRMWARE_MTHD_PRIV_ACCESS_VIOLATION 0x00000002 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FIRMWARE_MTHD_VERIF_VIOLATION 0x00000003 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_OOB 0x00000001 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_NOT_IN_WHITELIST 0x00000002 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_ALLOW_NONE 0x00000003 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_KILL 0x00000004 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_OOB 0x00000005 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_NOT_IN_WHITELIST 0x00000006 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_FUNCTION_TRACING_MAILBOX_SET(i) (0x00409848+(i)*4) /* -W-4A */ #define NV_PGRAPH_PRI_FECS_CTXSW_FUNCTION_TRACING_MAILBOX_SET__SIZE_1 6 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_FUNCTION_TRACING_MAILBOX_SET_VALUE 31:0 /* -W-VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR(i) (0x00409860+(i)*4) /* -W-4A */ #define NV_PGRAPH_PRI_FECS_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR__SIZE_1 6 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR_VALUE 31:0 /* -W-VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_FUNCTION_TRACING_MAILBOX(i) (0x004098c0+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_CTXSW_FUNCTION_TRACING_MAILBOX__SIZE_1 6 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_FUNCTION_TRACING_MAILBOX_VALUE 31:0 /* -W-VF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK 0x00409878 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_LEVEL3_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_LOCAL_FALCON_ENABLED 0x80040 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1(i) (0x004098d8+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1__PRIV_LEVEL_MASK 0x00409878 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_VALUE 31:0 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP1_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK 0x0040987c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_LEVEL3_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2(i) (0x004098e4+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2__PRIV_LEVEL_MASK 0x0040987c /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_VALUE 31:0 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP2_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK 0x004098fc /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3(i) (0x004098f0+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3__PRIV_LEVEL_MASK 0x004098fc /* */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_VALUE 31:0 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_SECURE_SCRATCH_GROUP3_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK 0x00409428 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_SOURCE_FALCON_FECS_GPCCS_ENABLED 0x80174 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_FECS_COMP_FS_CONFIG 0x0040940c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_COMP_FS_CONFIG__PRIV_LEVEL_MASK 0x00409428 /* */ #define NV_PGRAPH_PRI_FECS_COMP_FS_CONFIG_EN 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_COMP_FS_CONFIG_EN_NONE 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_COMP_ACTIVE_CONFIG 0x00409410 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_COMP_ACTIVE_CONFIG__PRIV_LEVEL_MASK 0x00409428 /* */ #define NV_PGRAPH_PRI_FECS_COMP_ACTIVE_CONFIG_EN 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_COMP_ACTIVE_CONFIG_EN_NONE 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_COMP_FINISHED 0x00409414 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_COMP_FINISHED__PRIV_LEVEL_MASK 0x00409428 /* */ #define NV_PGRAPH_PRI_FECS_COMP_FINISHED_BITS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_COMP_FINISHED_BITS_RESET 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE(i) (0x00409418+(i)*4) /* -W-4A */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE__PRIV_LEVEL_MASK 0x00409428 /* */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT0 0:0 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT0_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT1 1:1 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT1_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT2 2:2 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT2_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT3 3:3 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT3_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT4 4:4 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT4_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT5 5:5 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT5_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT6 6:6 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT6_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT7 7:7 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT7_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT8 8:8 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT8_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT9 9:9 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT9_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT9_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT10 10:10 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT10_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT10_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT11 11:11 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT11_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT11_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT12 12:12 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT12_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT12_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT13 13:13 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT13_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT13_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT14 14:14 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT14_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT14_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT15 15:15 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT15_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT15_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT16 16:16 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT16_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT16_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT17 17:17 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT17_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT17_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT18 18:18 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT18_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT18_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT19 19:19 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT19_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT19_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT20 20:20 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT20_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT20_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT21 21:21 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT21_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT21_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT22 22:22 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT22_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT22_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT23 23:23 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT23_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT23_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT24 24:24 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT24_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT24_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT25 25:25 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT25_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT25_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT26 26:26 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT26_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT26_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT27 27:27 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT27_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT27_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT28 28:28 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT28_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT28_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT29 29:29 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT29_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT29_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT30 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT30_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT30_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT31 31:31 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT31_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_COMP_SET_DONE_BIT31_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_POWER_GATE_CTL 0x004098ac /* RW-4R */ #define NV_PGRAPH_PRI_FECS_CTXSW_POWER_GATE_CTL_ENABLE_POWER 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_POWER_GATE_CTL_ENABLE_POWER_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_POWER_GATE_CTL_ENABLE_POWER_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CTXSW_POWER_GATE_CTL_ENABLE_FALCON_CLK 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CTXSW_POWER_GATE_CTL_ENABLE_FALCON_CLK_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CTXSW_POWER_GATE_CTL_ENABLE_FALCON_CLK_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FS 0x00409604 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 /* R--VF */ #define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_LTCS 28:24 /* R--VF */ #define NV_PGRAPH_PRI_FECS_SMC_CONFIGURATION 0x0040961c /* R--4R */ #define NV_PGRAPH_PRI_FECS_SMC_CONFIGURATION_MODE 0:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_SMC_CONFIGURATION_MODE_LEGACY_MODE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_SMC_CONFIGURATION_MODE_SMC_MODE 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_SMC_CONFIGURATION_SMC_ENGINE_ID 20:16 /* R--VF */ #define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x00409620 /* R--4R */ #define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ_4K 0x10 /* R---V */ #define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ_6K 0x18 /* R---V */ #define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ_8K 0x20 /* R---V */ #define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ_12K 0x30 /* R---V */ #define NV_PGRAPH_PRI_FECS_CFG_FALCON_DMEM_SZ 15:8 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_CFG_FALCON_DMEM_SZ_2K 0x08 /* R---V */ #define NV_PGRAPH_PRI_FECS_CFG_FALCON_DMEM_SZ_4K 0x10 /* R---V */ #define NV_PGRAPH_PRI_FECS_CFG_FALCON_DMEM_SZ_8K 0x20 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANES 0x00409880 /* R--4R */ #define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN 0x00409884 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE0_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE0_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE1_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE1_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE2_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE2_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE3_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE3_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE4 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE4_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE4_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE5_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE5_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE6_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE6_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE7_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE7_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE8 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE8_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE8_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE9 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE9_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE9_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE10 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE10_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE10_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE11 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE11_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE11_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE12 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE12_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE12_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE13 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE13_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE13_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE14 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE14_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE14_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE15 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE15_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE15_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE16 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE16_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE16_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE17 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE17_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RUN_LANE17_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS 0x00409888 /* R--4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE0 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE0_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE0_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE1 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE1_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE1_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE2 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE2_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE2_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE3 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE3_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE3_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE4 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE4_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE4_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE5 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE5_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE5_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE6 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE6_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE6_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE7 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE7_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE7_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE8 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE8_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE8_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE9 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE9_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE9_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE10 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE10_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE10_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE11 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE11_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE11_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE12 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE12_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE12_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE13 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE13_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE13_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE14 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE14_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE14_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE15 15:15 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE15_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE15_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE16 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE16_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE16_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE17 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE17_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_STATUS_LANE17_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SCRUB 0x00409640 /* R--4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SCRUB_STATUS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SCRUB_STATUS_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SCRUB_STATUS_CLEAN 0xffffffff /* R---V */ #define NV_PGRAPH_PRI_FECS_SIMULATION_OPTIONS 0x00409644 /* R--4R */ #define NV_PGRAPH_PRI_FECS_SIMULATION_OPTIONS_MODEL 1:0 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_SIMULATION_OPTIONS_MODEL_GATES 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_SIMULATION_OPTIONS_MODEL_RTL 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_SIMULATION_OPTIONS_MODEL_FMODEL 0x2 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS 0x00409678 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_RESET 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_RESET_TASK 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_STATUS_RESET_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CORRECTED_ERR_COUNT 0x0040967c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_UNCORRECTED_ERR_COUNT 0x00409680 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_ADDRESS 0x00409684 /* R--4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_ADDRESS_INDEX 22:0 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_ADDRESS_ROW_ADDRESS 19:0 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_ADDRESS_SOURCE_RAM 22:20 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_ADDRESS_SOURCE_RAM_FALCON_IMEM 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_ADDRESS_SOURCE_RAM_FALCON_DMEM 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK 0x00409688 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWB-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CONTROL 0x0040968c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CONTROL__PRIV_LEVEL_MASK 0x00409688 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR 0:0 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR 1:1 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* -W--V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_INFO 0x00409690 /* R--4R */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_INFO_ADDRESS 25:0 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_INFO_ADDRESS_V 0x0000000 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_INFO_TRANSACTION_TYPE 30:29 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_INFO_TRANSACTION_TYPE_INVALID 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_INFO_TRANSACTION_TYPE_READ 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_INFO_TRANSACTION_TYPE_WRITE_ACK 0x2 /* R---V */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_INFO_TRANSACTION_TYPE_WRITE_NO_ACK 0x3 /* R---V */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_INFO_SOURCE 31:31 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_INFO_SOURCE_PRI_SEQ 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_INFO_SOURCE_FALCON_CSB 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_CODE 0x00409694 /* R--4R */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_CODE_VALUE 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_CODE_VALUE_V 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_SUBID_INFO 0x004096a0 /* R--4R */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_SUBID_INFO_TRANSACTION_SUBID 7:0 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_SUBID_INFO_TRANSACTION_SUBID_V 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_SUBID_INFO_RETURN_SUBID 15:8 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_PRI_ERROR_SUBID_INFO_RETURN_SUBID_V 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK 0x00409950 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_IFF_GPCCS_FECS_GSP_SEC2_FUSE1 0x8007c /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CONTROL 0x00409904 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CONTROL__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CONTROL_COMPRESSION 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CONTROL_COMPRESSION_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CONTROL_COMPRESSION_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CONTROL_BLOAT_BUDGET 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CONTROL_BLOAT_BUDGET_0 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CONTROL_COMPRESSION_SETTINGS 27:10 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CONTROL_COMPRESSION_SETTINGS__0 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SAVE_OFFSET 0x00409908 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SAVE_OFFSET__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SAVE_OFFSET_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SAVE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RESTORE_OFFSET 0x0040990c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RESTORE_OFFSET__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RESTORE_OFFSET_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RESTORE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CURRENT_OFFSET 0x0040992c /* R--4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CURRENT_OFFSET_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CURRENT_OFFSET_V_0 0x00000000 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CURRENT_SUBOFFSET 0x00409930 /* R--4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CURRENT_SUBOFFSET_V 5:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CURRENT_SUBOFFSET_V_0 0x00 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SIZE 0x00409910 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SIZE__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SIZE_V 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SIZE_V_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_PREFETCH_OFFSET 0x00409914 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_PREFETCH_OFFSET__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_PREFETCH_OFFSET_CTL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_PREFETCH_OFFSET_CTL_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_PREFETCH_OFFSET_CTL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_PREFETCH_OFFSET_V 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_PREFETCH_OFFSET_V_10 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SAVED_WORDS 0x00409934 /* R--4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SAVED_WORDS__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SAVED_WORDS_V 23:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SAVED_WORDS_V_0 0x000000 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RESTORE_WORDS 0x00409938 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RESTORE_WORDS__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RESTORE_WORDS_V 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_RESTORE_WORDS_V_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_DATA 0x00409918 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_DATA__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_DATA_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_DATA_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_LOC 0x0040991c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_LOC__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_LOC_RAMID 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_LOC_RAMID_V 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_LOC_OFFSET 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_LOC_OFFSET_V 0x000f /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_CFG 0x00409920 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_CFG__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_CFG_DELAY 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_CFG_DELAY_V 0x41 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_CFG_CREDITS 21:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_CFG_CREDITS_V 0x3f /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_CFG_AUTOSEEK 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_CFG_AUTOSEEK_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_CFG_AUTOSEEK_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_RCCLASS 0x0040993c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_RCCLASS__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_RCCLASS_V 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_RCCLASS_V_3 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_RCCLASS_V_WFI 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_RCCLASS_V_GFXP 0x4 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS 0x00409924 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD 4:0 /* RW-VF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_IDLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_SEEK 0x01 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_DISCOVER_LENGTH 0x02 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_SAVE 0x03 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_RESTORE 0x04 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_LOAD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_READ_POP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_WRITE_PUSH 0x07 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_ENABLE 0x08 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_DISABLE 0x09 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_ENABLE 0x0a /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_DISABLE 0x0b /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_ENABLE 0x0c /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_DISABLE 0x0d /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_OVERRIDE 0x0e /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_FLUSH 0x0f /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_LAST_CMD_SUSPEND 0x10 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_CURRENT 9:8 /* R--VF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_CURRENT_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_STATUS_CURRENT_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC 0x00409928 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_IDLE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_SEEK 0x01 /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_DISCOVER_LENGTH 0x02 /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_SAVE 0x03 /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_RESTORE 0x04 /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_LOAD 0x05 /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_READ_POP 0x06 /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_WRITE_PUSH 0x07 /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_RAMID_ENABLE 0x08 /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_RAMID_DISABLE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_CLASS_ENABLE 0x0a /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_CLASS_DISABLE 0x0b /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_CHAIN_ENABLE 0x0c /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_CHAIN_DISABLE 0x0d /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_CLASS_OVERRIDE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_FLUSH 0x0f /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_SUSPEND 0x10 /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CMD_EXEC_CMD_SCRUB 0x11 /* -W--T */ #define NV_PGRAPH_PRI_FECS_RC_LANE_COMPUTED_CHECKSUM 0x00409944 /* R-E4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_COMPUTED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SAVED_CHECKSUM 0x00409948 /* R-E4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SAVED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CHECKSUM 0x0040994c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CHECKSUM__PRIV_LEVEL_MASK 0x00409950 /* */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CHECKSUM_CTRL_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CHECKSUM_CTRL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CHECKSUM_STATUS_MATCH 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_RC_LANE_CHECKSUM_STATUS_MISMATCH 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK 0x00409760 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pri_sequencer_wr_secure" /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWB-V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_pri_sequencer_wr_secure" /* */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_FECS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_JTAG_IFF_SEC2_ENABLED_FUSE1 0x80144 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_SAVE_OFFSET 0x00409700 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PVS_SAVE_OFFSET__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_SAVE_OFFSET_V 31:0 /* RW-VF */ #define NV_PGRAPH_PRI_FECS_PVS_SAVE_OFFSET_V_0 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_RESTORE_OFFSET 0x00409704 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PVS_RESTORE_OFFSET__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_RESTORE_OFFSET_V 31:0 /* RW-VF */ #define NV_PGRAPH_PRI_FECS_PVS_RESTORE_OFFSET_V_0 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_SAVE_COUNT 0x00409748 /* R--4R */ #define NV_PGRAPH_PRI_FECS_PVS_SAVE_COUNT_V 15:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_PVS_SAVE_COUNT_V_0 0x0000 /* R---V */ #define NV_PGRAPH_PRI_FECS_PVS_RESTORE_COUNT 0x0040974c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PVS_RESTORE_COUNT__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_RESTORE_COUNT_V 15:0 /* RW-VF */ #define NV_PGRAPH_PRI_FECS_PVS_RESTORE_COUNT_V_0 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_CURRENT_OFFSET 0x00409708 /* R--4R */ #define NV_PGRAPH_PRI_FECS_PVS_CURRENT_OFFSET_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_PVS_CURRENT_SUBOFFSET 0x0040970c /* R--4R */ #define NV_PGRAPH_PRI_FECS_PVS_CURRENT_SUBOFFSET_V 5:0 /* R-XVF */ #define NV_PGRAPH_PRI_FECS_PVS_REGISTER_BASE_ADDR 0x00409710 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PVS_REGISTER_BASE_ADDR__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_REGISTER_BASE_ADDR_V 25:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_REGISTER_BASE_ADDR_V_0 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_REGISTER_BASE_ADDR 0x00409724 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PV_REGISTER_BASE_ADDR__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PV_REGISTER_BASE_ADDR_V 25:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_REGISTER_BASE_ADDR_V_0 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_ST_CONSTANT 0x00409744 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PVS_ST_CONSTANT__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_ST_CONSTANT_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_ST_CONSTANT_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_MODE 0x00409714 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PVS_MODE__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_FIFO_FREE_ENTRIES 4:0 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_FIFO_FREE_ENTRIES_IV 0x10 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_FIFO_TOTAL_ENTRIES 12:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_FIFO_TOTAL_ENTRIES_IV 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_DIRECTION 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_DIRECTION_SAVE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_DIRECTION_RESTORE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_START 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_START_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_START_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_FINISH 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_FINISH_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_FINISH_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_NO_ADDR_INC 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_NO_ADDR_INC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_NO_ADDR_INC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_PRIV_LEVEL 29:28 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_PRIV_LEVEL_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_LOWER_PRIV_LEVEL 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_LOWER_PRIV_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_MODE_LOWER_PRIV_LEVEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_PREFETCH_CTL 0x00409740 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PVS_PREFETCH_CTL__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_PREFETCH_CTL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_PREFETCH_CTL_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_PREFETCH_CTL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_PREFETCH_CTL_OFFSET 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_PREFETCH_CTL_OFFSET_10 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_INDEX_INCREMENT 0x00409718 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PVS_INDEX_INCREMENT__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_INDEX_INCREMENT_V 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_INDEX_INCREMENT_V_0 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_INDEX_MASK 0x0040971c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PVS_INDEX_MASK__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_INDEX_MASK_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_INDEX_MASK_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH 0x00409720 /* -W-4R */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_USE_BASE_ADDR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_USE_INDEXER 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_ADDR 25:2 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_REGISTER_COUNT 30:26 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_SPECIAL 31:31 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_SPECIAL_DATA 25:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_SPECIAL_COUNT 11:0 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_SPECIAL_CMD 30:26 /* -WXVF */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_SPECIAL_CMD_NOP 0x00 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_SPECIAL_CMD_WAIT 0x01 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_SPECIAL_CMD_STORE_CONSTANT 0x02 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_SPECIAL_CMD_SKIP_DATA 0x03 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PVS_FIFO_PUSH_SPECIAL_CMD_SET_REG_COUNT 0x04 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ 0x00409728 /* RWE4R */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_USE_BASE_ADDR_NOT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_ADDR 25:2 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_ADDR_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_LOWER_PRIV_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_LOWER_PRIV_LEVEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_TRANS_STATUS 28:27 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_TRANS_STATUS_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_TRANS_STATUS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_TRANS_STATUS_DONE 0x2 /* R---V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_TRANS_TYPE 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_TRANS_TYPE_READ 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_TRANS_TYPE_UNDEF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_TRANS_TYPE_WRITE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_TRANS_TYPE_WRITE_ACK 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_CMD 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_CMD_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_CMD_GO 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A 0x00409734 /* RWE4R */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_USE_BASE_ADDR_NOT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_ADDR 25:2 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_ADDR_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_TRANS_STATUS 28:27 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_TRANS_STATUS_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_TRANS_STATUS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_TRANS_STATUS_DONE 0x2 /* R---V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_TRANS_TYPE 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_TRANS_TYPE_READ 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_TRANS_TYPE_UNDEF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_TRANS_TYPE_WRITE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_TRANS_TYPE_WRITE_ACK 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_CMD 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_CMD_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_A_CMD_GO 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B 0x00409738 /* RWE4R */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_USE_BASE_ADDR_NOT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_ADDR 25:2 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_ADDR_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_TRANS_STATUS 28:27 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_TRANS_STATUS_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_TRANS_STATUS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_TRANS_STATUS_DONE 0x2 /* R---V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_TRANS_TYPE 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_TRANS_TYPE_READ 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_TRANS_TYPE_UNDEF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_TRANS_TYPE_WRITE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_TRANS_TYPE_WRITE_ACK 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_CMD 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_CMD_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_B_CMD_GO 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_READ_DATA 0x0040972c /* R--4R */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_READ_DATA_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_READ_DATA_A 0x00409754 /* R--4R */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_READ_DATA_A_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_READ_DATA_B 0x00409758 /* R--4R */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_READ_DATA_B_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_WRITE_DATA 0x00409730 /* RWE4R */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_WRITE_DATA__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_WRITE_DATA_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_WRITE_DATA_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_WRITE_DATA_A 0x0040973c /* RWE4R */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_WRITE_DATA_A__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_WRITE_DATA_A_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_WRITE_DATA_A_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_WRITE_DATA_B 0x00409750 /* RWE4R */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_WRITE_DATA_B__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_WRITE_DATA_B_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_WRITE_DATA_B_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_STATUS 0x00409764 /* R--4R */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_STATUS_PRIV_LEVEL 1:0 /* R--VF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_STATUS_PRIV_LEVEL_A 5:4 /* R--VF */ #define NV_PGRAPH_PRI_FECS_PV_PRIV_REQ_STATUS_PRIV_LEVEL_B 9:8 /* R--VF */ #define NV_PGRAPH_PRI_FECS_PVS_COMPUTED_CHECKSUM 0x00409774 /* RWE4R */ #define NV_PGRAPH_PRI_FECS_PVS_COMPUTED_CHECKSUM__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_COMPUTED_CHECKSUM_RESULTS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_SAVED_CHECKSUM 0x00409778 /* RWE4R */ #define NV_PGRAPH_PRI_FECS_PVS_SAVED_CHECKSUM__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_SAVED_CHECKSUM_RESULTS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_CHECKSUM 0x0040977c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PVS_CHECKSUM__PRIV_LEVEL_MASK 0x00409760 /* */ #define NV_PGRAPH_PRI_FECS_PVS_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PVS_CHECKSUM_CTRL_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PVS_CHECKSUM_CTRL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PVS_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_PGRAPH_PRI_FECS_PVS_CHECKSUM_STATUS_MATCH 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_PVS_CHECKSUM_STATUS_MISMATCH 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_ARB_LANE_CTL 0x00409a00 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES_V 0x8 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_LANE_CTL_WRR_WEIGHT 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_LANE_CTL_WRR_WEIGHT_V 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_BASE_ADDR 0x00409a04 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_BASE_ADDR_F 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_BASE_ADDR_F_V 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_HI_BASE_ADDR 0x00409a38 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_HI_BASE_ADDR_F 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_HI_BASE_ADDR_F_V 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_ENGINE_CTL 0x00409a3c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_ENGINE_CTL_ENGINE_ID 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_ENGINE_CTL_ENGINE_ID_VEID0 0x40 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_ENGINE_CTL_ENGINE_ID_BAR2_FN0 0xc0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_ENGINE_CTL_VEID 21:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_ENGINE_CTL_VEID_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_ENGINE_CTL_GFID 29:24 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_ENGINE_CTL_GFID_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_PREFETCH_CTL 0x00409a08 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_PREFETCH_CTL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_PREFETCH_CTL_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_PREFETCH_CTL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_PREFETCH_CTL_OFFSET 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_PREFETCH_CTL_OFFSET_V 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK 0x00409a28 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x00409a24 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR__PRIV_LEVEL_MASK 0x00409a28 /* */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR_LO 11:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR_LO_0 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR_L2_CLASS 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR_L2_CLASS_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR_RD 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR_RD_WR 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR_RD_RD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x00409a0c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR__PRIV_LEVEL_MASK 0x00409a28 /* */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR_0 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET_VID_MEM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET_SYS_MEM_COHERENT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET_SYS_MEM_NONCOHERENT 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x00409a10 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD__PRIV_LEVEL_MASK 0x00409a28 /* */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_IDLE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_FB_OP_FLUSH 0x05 /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_FB_OP_SOFT_FLUSH 0x06 /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_FB_OP_BIND_INST_BLK_PTR 0x07 /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_FB_OP_MMU_TLB_INVALIDATE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_PREFETCH 0x0a /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_FB_OP_PHYSICAL_L2_CACHE_MGMT 0x0b /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_CACHE_MGMT 0x0c /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_FB_OP_L2_PEER_INVALIDATE 0x0d /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_FB_OP_L2_SYSMEM_INVALIDATE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_CLEAN_COMPTAGS 0x0f /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_FLUSH_DIRTY 0x10 /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD_MEMBAR 0x01 /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_SUB_OP 8:7 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_SUB_OP_INVALIDATE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_SUB_OP_CLEAN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_SUB_OP_DEMOTE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_ACK 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_ACK_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_ACK_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_ACK_TLB 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_ACK_MEM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_ACK_NONE_REQUIRED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_ACK_GLOBALLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_ACK_INTRANODE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_HALT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_HALT_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_HALT_REQUEST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_UNHALT 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_UNHALT_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_UNHALT_REQUEST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_L2_EVICTION_CTL 0x00409a14 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_L2_EVICTION_CTL_WR 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_L2_EVICTION_CTL_WR_FIRST 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_L2_EVICTION_CTL_WR_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_L2_EVICTION_CTL_WR_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_L2_EVICTION_CTL_RD 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_L2_EVICTION_CTL_RD_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_L2_EVICTION_CTL_RD_NORMAL 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_L2_EVICTION_CTL_RD_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_PRIV 0x00409a18 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_PRIV_OVERRIDE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_PRIV_OVERRIDE_PRIV 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_PRIV_OVERRIDE_NONPRIV 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS 0x00409a1c /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_CLEAR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_CLEAR_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_CLEAR_CLEAR 0x1 /* -W--T */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_ACK 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_ACK_OK 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_ACK_NACK 0x0 /* R---V */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_SUBID 15:2 /* R--VF */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_OUTSTANDING_TRANSACTIONS 23:16 /* R--VF */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_BUFFER_NOT_EMPTY 24:24 /* R--VF */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_FLUSH_WHEN_BUSY 28:28 /* R-EVF */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_FLUSH_WHEN_BUSY_DEFAULT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_FLUSH_WHEN_BUSY_ERROR 0x1 /* R---V */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_HALTED 30:30 /* R--VF */ #define NV_PGRAPH_PRI_FECS_ARB_STATUS_BUSY 31:31 /* R--VF */ #define NV_PGRAPH_PRI_FECS_ARB_CMD_OVERRIDE 0x00409a20 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_CMD_OVERRIDE_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CMD_OVERRIDE_CMD_VIRTUAL 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CMD_OVERRIDE_CMD_PHYS_VID_MEM 0x02 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_NONCOHERENT 0x03 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_COHERENT 0x04 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_CMD_OVERRIDE_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_CMD_OVERRIDE_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_CMD_OVERRIDE_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR 0x00409a2c /* RWE4R */ #define NV_PGRAPH_PRI_FECS_ARB_WPR__PRIV_LEVEL_MASK 0x00409a28 /* */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_RC_ID 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_RC_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_RC_SECURE_LEVEL 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_RC_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PVS_ID 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PVS_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PVS_SECURE_LEVEL 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_PVS_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_CMD_ID 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_CMD_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_CMD_SECURE_LEVEL 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_CMD_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_BLOCKED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_ALLOWED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK 0x00409a30 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG 0x00409a34 /* RWE4R */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG__PRIV_LEVEL_MASK 0x00409a30 /* */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T0 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T1 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T2 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T3 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T4 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T5 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T6 27:24 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T7 31:28 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_ARB_FALCON_REGIONCFG_T7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PERFMON 0x004098a0 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_FB_CMD 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_FB_CMD2 0x01 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_FB_CMD3 0x02 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_FB_DATA 0x03 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_MISC_0 0x04 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_MISC_1 0x05 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_0 0x06 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_1 0x07 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_2 0x08 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_3 0x09 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_4 0x0a /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_5 0x0b /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_6 0x0c /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_7 0x0d /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_8 0x0e /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_9 0x0f /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_10 0x10 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_11 0x11 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_12 0x12 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_13 0x13 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_14 0x14 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_15 0x15 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_17 0x17 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_18 0x18 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_RC_0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_RC_1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_RC_2 0x1b /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_RC_3 0x1c /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_RC_4 0x1d /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_RC_5 0x1e /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_RC_6 0x1f /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_RC_7 0x20 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_RC_8 0x21 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_RC_9 0x22 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_RC_10 0x23 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_0 0x24 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_1 0x25 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_2 0x26 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_3 0x27 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_4 0x28 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_5 0x29 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_6 0x2a /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_7 0x2b /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_9 0x2d /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_10 0x2e /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PROBE_0 0x2f /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PROBE_1 0x30 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_ARB_0 0x31 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_ARB_1 0x32 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_ERR 0x33 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_MISC_2 0x34 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_MISC_3 0x35 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_MISC_4 0x36 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_MISC_5 0x37 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_MISC_6 0x38 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_19 0x39 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_20 0x3a /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_21 0x3b /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_22 0x3c /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_23 0x3d /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_24 0x3e /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_25 0x3f /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_26 0x40 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_27 0x41 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_28 0x42 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_29 0x43 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_30 0x44 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_31 0x45 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_32 0x46 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_33 0x47 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_34 0x48 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_35 0x49 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_PRI_36 0x4a /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATIC_PATTERN_55_8_GROUP 0x4b /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATIC_PATTERN_AA_8_GROUP 0x4c /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_11 0x4d /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_12 0x4e /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_13 0x4f /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_14 0x50 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_STATUS_15 0x51 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_CTXSW_0 0x52 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_SEL_ECC_ERR 0x53 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_CTRL_ENABLE 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PERFMON_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_CTRL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM 0x004098a8 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_PROBE 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_PROBE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_PROBE_TOGGLE_BIT0 0x01 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_PROBE_TOGGLE_BIT1 0x02 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_PROBE_TOGGLE_BIT2 0x04 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_PROBE_TOGGLE_BIT3 0x08 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_PROBE_TOGGLE_BIT4 0x10 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_PROBE_TOGGLE_BIT5 0x20 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_PROBE_TOGGLE_BIT6 0x40 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_PROBE_TOGGLE_BIT7 0x80 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_SET 23:16 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_SET_INIT 0x00 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_SET_BIT0 0x01 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_SET_BIT1 0x02 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_SET_BIT2 0x04 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_SET_BIT3 0x08 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_SET_BIT4 0x10 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_SET_BIT5 0x20 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_SET_BIT6 0x40 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_SET_BIT7 0x80 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_CLEAR 31:24 /* -WEVF */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_CLEAR_INIT 0x00 /* -WE-V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_CLEAR_BIT0 0x01 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_CLEAR_BIT1 0x02 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_CLEAR_BIT2 0x04 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_CLEAR_BIT3 0x08 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_CLEAR_BIT4 0x10 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_CLEAR_BIT5 0x20 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_CLEAR_BIT6 0x40 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_PM_CLEAR_BIT7 0x80 /* -W--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_MODE 0x004098a4 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PERFMON_MODE_PROBE 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PERFMON_MODE_PROBE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE 0x004096b0 /* RW-4R */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_SAVE_OVERHEAD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_SAVE_WAIT_FOR_FE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_SAVE_WFI 0x4 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_SAVE_GFXP 0x5 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_SAVE_CILP 0x6 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_SAVE_CTA 0x7 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_RESTORE_OVERHEAD 0x8 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_RESTORE_WFI 0x9 /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_RESTORE_GFXP 0xa /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_RESTORE_CILP 0xb /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_RESTORE_CTA 0xc /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_RESTORE_PATCH_BUFFER 0xd /* RW--V */ #define NV_PGRAPH_PRI_FECS_PERFMON_UCODE_STATE_SCRUB 0xe /* RW--V */ #define NV_PGRAPH_PRI_FECS_CG 0x00409890 /* RWE4R */ #define NV_PGRAPH_PRI_FECS_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CG_IDLE_CG_DLY_CNT__PROD 0x3f /* RW--V */ #define NV_PGRAPH_PRI_FECS_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_FECS_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_FECS_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_FECS_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_FECS_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_FECS_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_FECS_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_FECS_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_FECS_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_FECS_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_FECS_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_FECS_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_FECS_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FECS_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_CG1 0x00409894 /* RWE4R */ #define NV_PGRAPH_PRI_FECS_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CG1_SLCG 15:1 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_FECS_CG1_SLCG_DISABLED 0x7fff /* RWE-V */ #define NV_PGRAPH_PRI_FECS_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG 0x004098b0 /* RWE4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_IDLE_CG_DLY_CNT__PROD 0x3f /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_FECS_FALCON_CG1 0x004098b4 /* RWE4R */ #define NV_PGRAPH_PRI_FECS_FALCON_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_FECS_FALCON_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_FECS_FALCON_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CG 0x00406000 /* RWE4R */ #define NV_PGRAPH_PRI_PD_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_PD_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_PD_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_PD_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_PD_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PD_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_PD_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_PD_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_PD_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_PD_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_PD_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_PD_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PD_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_PD_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_PD_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_PD_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_PD_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PD_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_PD_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_PD_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_PD_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_PD_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_PD_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_PD_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_PD_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_PD_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_PD_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_PD_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_PD_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PD_CG1 0x00406004 /* RWE4R */ #define NV_PGRAPH_PRI_PD_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_PD_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PD_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_PD_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_PD_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_PD_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_PD_HWW_ESR 0x00406018 /* RWE4R */ #define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_NONACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_PD_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_PD_HWW_ESR_INVALID_AB_DIST_MAX_OUTPUT 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_PD_HWW_ESR_INVALID_AB_DIST_MAX_OUTPUT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_PD_HWW_ESR_INVALID_AB_DIST_MAX_OUTPUT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_PD_HWW_ESR_INVALID_AB_DIST_MAX_LODS 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_PD_HWW_ESR_INVALID_AB_DIST_MAX_LODS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_PD_HWW_ESR_INVALID_AB_DIST_MAX_LODS_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_PD_HWW_ESR_INVALID_AB_DIST_MAX_WARPS 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_PD_HWW_ESR_INVALID_AB_DIST_MAX_WARPS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_PD_HWW_ESR_INVALID_AB_DIST_MAX_WARPS_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_PD_HWW_ESR_INVALID_AB_DIST_INVALID_PAGEPOOL 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_PD_HWW_ESR_INVALID_AB_DIST_INVALID_PAGEPOOL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_PD_HWW_ESR_INVALID_AB_DIST_INVALID_PAGEPOOL_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_PD_CYA 0x00406020 /* RWI4R */ #define NV_PGRAPH_PRI_PD_CYA_ONE_PRIM_PER_BATCH 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_ONE_PRIM_PER_BATCH_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_ONE_PRIM_PER_BATCH_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_PG_PACK_PRIMS 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_PG_PACK_PRIMS_ENABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_PG_PACK_PRIMS_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_SIMPLE_SET 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_SIMPLE_SET_ENABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_SIMPLE_SET_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_DS_BYPASS 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_DS_BYPASS_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_DS_BYPASS_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_SPH_INDEX_FETCH_EVICT_CLASS 18:17 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_SPH_INDEX_FETCH_EVICT_CLASS_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_SPH_INDEX_FETCH_EVICT_CLASS_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_SPH_INDEX_FETCH_EVICT_CLASS_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_INSTANCED_DRAW_PERF_OPT 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_INSTANCED_DRAW_PERF_OPT_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_INSTANCED_DRAW_PERF_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_TIMESLICE_COUNT_BUNDLES 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_TIMESLICE_COUNT_BUNDLES_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_TIMESLICE_COUNT_BUNDLES_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_SPARE_BIT23 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_SPARE_BIT23_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_PATCH_IN_SIMPLE_SET 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_PATCH_IN_SIMPLE_SET_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_PATCH_IN_SIMPLE_SET_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_STIPPLE_WAR 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_STIPPLE_WAR_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_STIPPLE_WAR_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_IID_OPT 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_IID_OPT_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_IID_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_SPARE_BIT27 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_SPARE_BIT27_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_CPO_OPT_DIFF_ENDS_TIMESLICE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_CPO_OPT_DIFF_ENDS_TIMESLICE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_CPO_OPT_DIFF_ENDS_TIMESLICE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_GRAPHICS_TPC_MASK_ENDS_TIMESLICE 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_GRAPHICS_TPC_MASK_ENDS_TIMESLICE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_GRAPHICS_TPC_MASK_ENDS_TIMESLICE_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_SPH_ADDRESS_FETCH_FILTERING 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_SPH_ADDRESS_FETCH_FILTERING_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_SPH_ADDRESS_FETCH_FILTERING_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_SPARE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_SPARE_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_PM 0x00406024 /* RWE4R */ #define NV_PGRAPH_PRI_PD_PM_SELECT 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_PD_PM_SELECT_CG 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_HIST_VAB 0x01 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_HIST_LAT 0x02 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_HIST_BAT_ID 0x03 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_HIST_RDAT 0x04 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SA_BREAK_BATCH_REASON 0x05 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SA_BATCH_TO_GPC_INCREMENTERS 0x06 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SA_SET_TO_GPC_INCREMENTERS 0x07 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SA_INDX_IN_SET 0x08 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SA_PRIM_IN_SET 0x09 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SA_COMPLEX_BATCH_REASON 0x0a /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PD_FLOW_0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PD_FLOW_1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PD_FLOW_2 0x0d /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PD_STALL 0x0e /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_GFXP 0x0f /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_CWD_CTA_0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_CWD_CTA_1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_CWD_MAX_SLOTS 0x12 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_CWD_MIN_SLOTS 0x13 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_CWD_STATE 0x14 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_STATUS_PD_CWD 0x15 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_STATUS_CWD 0x16 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_STATUS_PS_PC 0x17 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_STATUS_FR_BR 0x18 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_STATUS_SP_VM 0x19 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_STATUS_IM_PG 0x1a /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_STATUS_AF_VAB 0x1b /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_STATUS_SA_FBI 0x1c /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_STATUS_FBI_MSG_BID 0x1d /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_STATUS_FBI_MEM 0x1e /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PRIM_TYPE_COUNTS_1 0x1f /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PRIM_TYPE_COUNTS_2 0x20 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PRIM_TYPE_COUNTS_3 0x21 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PRIM_TYPE_COUNTS_4 0x22 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FETCH_STATS1 0x26 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FETCH_STATS2 0x27 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_IM_IA_STATS 0x28 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_DRAW_CNT 0x29 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_DRAB_CNT 0x2a /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_IM_IR_STATS 0x2b /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_VI_STATS 0x2c /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_VI_CURRENT 0x2d /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_VI_LAST 0x2e /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_VI_ANCHOR_DUP_CNT 0x2f /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_LRVI_LRVI 0x30 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_LRVI_BID 0x31 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_IM_VI_STATE1 0x32 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_IM_VI_STATE2 0x33 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_IM_VI_STATE3 0x34 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_IM_VI_STATE4 0x35 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_MIMO_FREE_CNT 0x36 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_MIMO_INPUT_CNT 0x37 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_MIMO_INDX_CNT 0x38 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_MIMO_PRIM_CNT 0x39 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_IM_FLOW 0x3a /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PG_STATE1 0x3b /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PG_STATE2 0x3c /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PG_STATE3 0x3d /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_VAB_STATE 0x3e /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FBI_MEM_CMD_FLOW 0x3f /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FBI_MEM_DATA_FLOW 0x40 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FBI_MSG_FLOW 0x41 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FBI_BID_LRBI 0x42 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FBI_BID_SSYNC 0x43 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_0 0x44 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_1 0x45 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_2 0x46 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_3 0x47 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_4 0x48 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_5 0x49 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_6 0x4a /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_CWD_FLOW_0 0x4c /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_CWD_FLOW_1 0x4d /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PS_DEBUG_0 0x4f /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PS_DEBUG_1 0x50 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FR_DEBUG 0x51 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_BR_FLOW 0x52 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_BR_DEBUG_0 0x53 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_BR_DEBUG_1 0x54 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SP_STATS 0x55 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SP_DEBUG_0 0x56 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SP_DEBUG_1 0x57 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SP_DEBUG_2 0x58 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SP_DEBUG_3 0x59 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SP_DEBUG_4 0x5a /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_VM_DEBUG_0 0x5b /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_VM_DEBUG_1 0x5c /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_VM_DEBUG_2 0x5d /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_VM_DEBUG_3 0x5e /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_VM_DEBUG_4 0x5f /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_IM_DEBUG 0x60 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FBI_DEBUG_0 0x61 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FBI_DEBUG_1 0x62 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FBI_DEBUG_2 0x63 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FBI_DEBUG_3 0x64 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FBI_DEBUG_4 0x65 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FBI_DEBUG_5 0x66 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_MIW_DEBUG_0 0x67 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_MIW_DEBUG_1 0x68 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_MIW_DEBUG_2 0x69 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_PC_DEBUG 0x6a /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SA_PARTITION 0x6b /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_IM_HIST 0x6c /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_CG_PG_STATUS_P0 0x6d /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_CG_PG_STATUS_P2 0x6e /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_TIMESLICE_0 0x6f /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_TIMESLICE_1 0x70 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FR_INSTANCE_DRAW 0x73 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_FETCH_STATS3 0x74 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_STATIC_PATTERN_AA_8 0x75 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_STATIC_PATTERN_55_8 0x76 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_SINGLE_PASS 0x77 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_MESHLET 0x78 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16P_4XREAD_GRP0 0x79 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16P_4XREAD_GRP1 0x7a /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16P_4XREAD_GRP2 0x7b /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16P_4XREAD_GRP3 0x7c /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16P_4XREAD_GRP4 0x7d /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16P_4XREAD_GRP5 0x7e /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16P_2XMSG_GRP0 0x7f /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_0_RD_COUNT 0x80 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_1_RD_COUNT 0x81 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_2_RD_COUNT 0x82 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_3_RD_COUNT 0x83 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_4_RD_COUNT 0x84 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_5_RD_COUNT 0x85 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_XBAR2PD_6_RD_COUNT 0x86 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_ALPHA_TIMESLICE 0x88 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16PPC_1 0x89 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16PPC_2 0x8a /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16PPC_3 0x8b /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16P_4XREAD_GRP6 0x8c /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16P_4XREAD_GRP7 0x8d /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_SELECT_16P_4XREAD_GRP8 0x8e /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_PD_PM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_PM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x00406028+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0_1 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0_2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0_3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0_4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0_5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0_6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0_7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0_8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 /* RWEVF */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 /* RWEVF */ #define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PD_BATCH_ID_START 0x004064a8 /* RWI4R */ #define NV_PGRAPH_PRI_PD_BATCH_ID_START_VALUE 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_BATCH_ID_START_VALUE_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_PD_BATCH_ID_MASK 0x004064ac /* RWI4R */ #define NV_PGRAPH_PRI_PD_BATCH_ID_MASK_FIXED_LSB 1:0 /* C--VF */ #define NV_PGRAPH_PRI_PD_BATCH_ID_MASK_FIXED_LSB_INIT 0x3 /* C---V */ #define NV_PGRAPH_PRI_PD_BATCH_ID_MASK_VALUE 15:2 /* RWIVF */ #define NV_PGRAPH_PRI_PD_BATCH_ID_MASK_VALUE_INIT 0x1fff /* RWI-V */ #define NV_PGRAPH_PRI_PD_DEBUG 0x004064b0 /* RWI4R */ #define NV_PGRAPH_PRI_PD_DEBUG_BLKACTIVITY 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_DEBUG_BLKACTIVITY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_DEBUG_BLKACTIVITY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_DEBUG_BLKACTIVITY_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_SP_CYA_FORCE_FREQ_DIV_ENABLE 0x004064b4 /* RWI4R */ #define NV_PGRAPH_PRI_PD_SP_CYA_FORCE_FREQ_DIV_ENABLE_STREAM 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_SP_CYA_FORCE_FREQ_DIV_ENABLE_STREAM_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_PD_SP_CYA_FORCE_FREQ_DIV_OVERRIDE 0x004064b8 /* RWI4R */ #define NV_PGRAPH_PRI_PD_SP_CYA_FORCE_FREQ_DIV_OVERRIDE_VALUE 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_SP_CYA_FORCE_FREQ_DIV_OVERRIDE_VALUE_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x004064c0 /* RWI4R */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_RESERVED_0 15:10 #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_RESERVED_1 30:24 #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_MAX_LODS 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_MAX_LODS_INIT 0x280 /* RWI-V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_MAX_WARPS 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_MAX_WARPS_INIT 0x40 /* RWI-V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x004064c4 /* RWI4R */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff /* RWI-V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_INIT 0x0200 /* RWI-V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x0080 /* RW--V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x004064c8 /* RWI4R */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_RESERVED_0 15:14 #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_RESERVED_1 31:30 #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 13:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x1140 /* RWI-V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 29:16 /* RWIVF */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 0x0020 /* RW--V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x1140 /* RW--V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_INIT 0x0180 /* RWI-V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_4 0x004064cc /* RWI4R */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_4_INFLIGHT_TRANSITIONS_LIMIT 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_4_INFLIGHT_TRANSITIONS_LIMIT_INIT 0x001 /* RWI-V */ #define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x004064d0+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK_NONE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK_NONE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK_NONE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK_NONE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_PD_PERF_ANALYSIS 0x004064fc /* RWI4R */ #define NV_PGRAPH_PRI_PD_PERF_ANALYSIS_LOOKBACK_SIZE 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_PERF_ANALYSIS_LOOKBACK_SIZE_INIT 0x2a /* RWI-V */ #define NV_PGRAPH_PRI_PD_PERF_ANALYSIS_SA_PACKER_ITERATIONS 14:8 /* RWIVF */ #define NV_PGRAPH_PRI_PD_PERF_ANALYSIS_SA_PACKER_ITERATIONS_INIT 0x02 /* RWI-V */ #define NV_PGRAPH_PRI_PD_PERF_ANALYSIS_SPARE 30:15 /* RWIVF */ #define NV_PGRAPH_PRI_PD_PERF_ANALYSIS_SPARE_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_PD_PERF_ANALYSIS_ENABLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_PD_PERF_ANALYSIS_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_3 0x00406500 /* RWI4R */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_3_BALANCED_PRIMITIVE_WORKLOAD_FORCED 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_3_BALANCED_PRIMITIVE_WORKLOAD_FORCED_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CONST_LIMITS 0x00406504 /* RWI4R */ #define NV_PGRAPH_PRI_PD_CONST_LIMITS_PPOOL 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CONST_LIMITS_PPOOL_INIT 0x030 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CONST_LIMITS_CBTBL 25:16 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CONST_LIMITS_CBTBL_INIT 0x030 /* RWI-V */ #define NV_PGRAPH_PRI_PD_TIMESLICE_FLUSH_ON_BUNDLE 0x00406508 /* RWI4R */ #define NV_PGRAPH_PRI_PD_TIMESLICE_FLUSH_ON_BUNDLE_ADDR_0 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_TIMESLICE_FLUSH_ON_BUNDLE_ADDR_0_INIT_GO_IDLE 0xe100 /* RWI-V */ #define NV_PGRAPH_PRI_PD_TIMESLICE_FLUSH_ON_BUNDLE_ADDR_1 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_PD_TIMESLICE_FLUSH_ON_BUNDLE_ADDR_1_INIT_GO_IDLE 0xe100 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_2 0x0040650c /* RWI4R */ #define NV_PGRAPH_PRI_PD_CYA_2_P0_SPARE_CYA 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_2_P0_SPARE_CYA_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_2_PROVOKING_FIRST_DX_MODE 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_2_PROVOKING_FIRST_DX_MODE_NO_ROTATE_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_2_PROVOKING_FIRST_DX_MODE_ROTATE_DEPENDS_ON_BARYCENTRICS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_2_PROVOKING_FIRST_DX_MODE_ROTATE_LEGACY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_2_PROVOKING_FIRST_DX_MODE_ROTATE_RESERVED 0x3 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_2_SCC_FEEDBACK_SYNC_COUNTING 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_2_SCC_FEEDBACK_SYNC_COUNTING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_2_SCC_FEEDBACK_SYNC_COUNTING_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_2_BIND_GROUP_BUNDLE_COUNT_AS_2_BUNDLE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_2_BIND_GROUP_BUNDLE_COUNT_AS_2_BUNDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_2_BIND_GROUP_BUNDLE_COUNT_AS_2_BUNDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_2_8PPC_MODE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_2_8PPC_MODE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_2_8PPC_MODE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_2_DYN_PPC_MODE 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_2_DYN_PPC_MODE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_2_DYN_PPC_MODE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_2_STALL_ON_BATCH_ID 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_2_STALL_ON_BATCH_ID_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_2_STALL_ON_BATCH_ID_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_2_SA_SPARE_CYA 11:9 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_2_SA_SPARE_CYA_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_CYA_2_TRANSITION_ON_VTG_SHADER_CHANGES 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_PD_CYA_2_TRANSITION_ON_VTG_SHADER_CHANGES_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PD_CYA_2_TRANSITION_ON_VTG_SHADER_CHANGES_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PD_RTV_CB_MGMT 0x00406510 /* RWI4R */ #define NV_PGRAPH_PRI_PD_RTV_CB_MGMT_MAX_AGE_SKEW 13:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_RTV_CB_MGMT_MAX_AGE_SKEW_INIT 0x0080 /* RWI-V */ #define NV_PGRAPH_PRI_PD_RTV_CB_MGMT_FEEDBACK_GRANULARITY 29:14 /* RWIVF */ #define NV_PGRAPH_PRI_PD_RTV_CB_MGMT_FEEDBACK_GRANULARITY_INIT 0x0080 /* RWI-V */ #define NV_PGRAPH_PRI_PD_RM_RTV_FLUSH_THRESHOLD 0x00406514 /* RWI4R */ #define NV_PGRAPH_PRI_PD_RM_RTV_FLUSH_THRESHOLD_VALUE 14:0 /* RWIVF */ #define NV_PGRAPH_PRI_PD_RM_RTV_FLUSH_THRESHOLD_VALUE_INIT 0x0080 /* RWI-V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK 0x00406518 /* RW-4R */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_PD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_PD_OUTPUT_BATCH_STALL 0x0040651c /* RW-4R */ #define NV_PGRAPH_PRI_PD_OUTPUT_BATCH_STALL__PRIV_LEVEL_MASK 0x00406518 /* */ #define NV_PGRAPH_PRI_PD_OUTPUT_BATCH_STALL_BATCH_COUNT 15:0 /* RWBVF */ #define NV_PGRAPH_PRI_PD_OUTPUT_BATCH_STALL_BATCH_COUNT_INIT 0x0000 /* RWB-V */ #define NV_PGRAPH_PRI_PD_OUTPUT_BATCH_STALL_CLK_COUNT 31:16 /* RWBVF */ #define NV_PGRAPH_PRI_PD_OUTPUT_BATCH_STALL_CLK_COUNT_INIT 0xe100 /* RWB-V */ #define NV_PGRAPH_PRI_DS_DEBUG 0x00405800 /* RWI4R */ #define NV_PGRAPH_PRI_DS_DEBUG_EARLYZ_NOUPDATE 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_EARLYZ_NOUPDATE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_EARLYZ_NOUPDATE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_EARLYZ_NOUPDATE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_EARLYZ_IGNORE_PXCNT 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_EARLYZ_IGNORE_PXCNT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_EARLYZ_IGNORE_PXCNT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_EARLYZ_IGNORE_PXCNT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_EARLYZ 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_EARLYZ_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_EARLYZ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_EARLYZ_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_CONSIDER_STIPPLE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_CONSIDER_STIPPLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_CONSIDER_STIPPLE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_RUN_DS_NOW 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_RUN_DS_NOW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_RUN_DS_NOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ZONLY 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_ZONLY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ZONLY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ZONLY_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_FILTER_BUNDLE 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_FILTER_BUNDLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_FILTER_BUNDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_FILTER_BUNDLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_STENCIL_KEEP 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_STENCIL_KEEP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_STENCIL_KEEP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_STENCIL_KEEP_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_MPIPE_FORCE_BC_ON 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_MPIPE_FORCE_BC_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_MPIPE_FORCE_BC_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_MPIPE_FORCE_BC_ON_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_ROP_FORCE_BC_ON 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_ROP_FORCE_BC_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_ROP_FORCE_BC_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_ROP_FORCE_BC_ON_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_PROP_FORCE_BC_ON 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_PROP_FORCE_BC_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_PROP_FORCE_BC_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_PROP_FORCE_BC_ON_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_RSTR_FORCE_BC_ON 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_RSTR_FORCE_BC_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_RSTR_FORCE_BC_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_RSTR_FORCE_BC_ON_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_TGA_FORCE_BC_ON 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_TGA_FORCE_BC_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_TGA_FORCE_BC_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_TGA_FORCE_BC_ON_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_VAF_FORCE_BC_ON 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_VAF_FORCE_BC_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_VAF_FORCE_BC_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_DS_VAF_FORCE_BC_ON_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_MPIPE_ALWAYS_DIRTY 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_MPIPE_ALWAYS_DIRTY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_MPIPE_ALWAYS_DIRTY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_MPIPE_ALWAYS_DIRTY_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_MPIPE 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_MPIPE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_MPIPE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_MPIPE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_PROP 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_PROP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_PROP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_PROP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_ROP 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_ROP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_ROP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_ROP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_RSTR 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_RSTR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_RSTR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_RSTR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_TGA 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_TGA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_TGA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_TGA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_VAF 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_VAF_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_VAF_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BYPASS_VAF_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_ALLOW_FASTCLEAR_COLOR 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_ALLOW_FASTCLEAR_COLOR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ALLOW_FASTCLEAR_COLOR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ALLOW_FASTCLEAR_COLOR_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_ALLOW_FASTCLEAR_DEPTH 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_ALLOW_FASTCLEAR_DEPTH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ALLOW_FASTCLEAR_DEPTH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ALLOW_FASTCLEAR_DEPTH_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_ALLOW_FASTCLEAR_STENCIL 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_ALLOW_FASTCLEAR_STENCIL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ALLOW_FASTCLEAR_STENCIL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ALLOW_FASTCLEAR_STENCIL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_BLKACTIVITY 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_BLKACTIVITY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BLKACTIVITY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_BLKACTIVITY_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_ROP_ALWAYS_DIRTY 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_ROP_ALWAYS_DIRTY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ROP_ALWAYS_DIRTY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ROP_ALWAYS_DIRTY_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_ROP_DBG_BITS 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_ROP_DBG_BITS_SAFE_FOR_VPR 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ROP_DBG_BITS_UNSAFE_FOR_VPR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_ROP_DBG_BITS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_DEBUG_SP_SWIZZLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_DS_DEBUG_SP_SWIZZLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_SP_SWIZZLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_DEBUG_SP_SWIZZLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA 0x00405830 /* RWI4R */ #define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 21:0 /* RWIVF */ #define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE_INIT 0x000480 /* RWI-V */ #define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA 0x0040585c /* RWI4R */ #define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE_INIT 0x0800 /* RWI-V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG 0x00405834 /* RWI4R */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG_USE_DS_CT_SEL_DL_SRC_BLND 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG_USE_DS_CT_SEL_DL_SRC_BLND_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG_USE_CT_SEL_PITCH_ACTIVE 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG_USE_CT_SEL_PITCH_ACTIVE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG_DS_PROPAGATE_BDL_ENABLE 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG_DS_PROPAGATE_BDL_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG_EXTRA_PROPAGATION_CYC 31:27 /* RWIVF */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG_EXTRA_PROPAGATION_CYC_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG2 0x00405838 /* RWI4R */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG2_DS_PROPAGATE_BDL_ADDR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG2_DS_PROPAGATE_BDL_ADDR_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG2_MUTABLE_STATE_FORCE 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG2_MUTABLE_STATE_FORCE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG2_MUTABLE_STATE_FORCE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG2_MUTABLE_STATE_FORCE_LIGHT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG2_MUTABLE_STATE_FORCE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG3 0x0040583c /* RWE4R */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG3_ROP_DBG_BITS 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG3_ROP_DBG_BITS_SAFE_FOR_VPR 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG3_ROP_DBG_BITS_UNSAFE_FOR_VPR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG3_ROP_DBG_BITS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG3_ROP_DBG_SAFETY_USE_CTX 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG3_ROP_DBG_SAFETY_USE_CTX_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG3_ROP_DBG_SAFETY_USE_CTX_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_ROP_DEBUG3_ROP_DBG_SAFETY_USE_CTX_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR 0x00405840 /* RWE4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH0_ERR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH0_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH0_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH1_ERR 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH1_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH1_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH2_ERR 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH2_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH2_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH3_ERR 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH3_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH3_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH4_ERR 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH4_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH4_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH5_ERR 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH5_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH5_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH6_ERR 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH6_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH6_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH7_ERR 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH7_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH7_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH8_ERR 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH8_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH8_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH9_ERR 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH9_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH9_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH10_ERR 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH10_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH10_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH11_ERR 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH11_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH11_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH12_ERR 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH13_ERR 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH13_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH13_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH14_ERR 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH14_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH14_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH15_ERR 15:15 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH15_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH15_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH16_ERR 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH16_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH16_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH17_ERR 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH17_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH17_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH18_ERR 18:18 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH18_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH18_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH19_ERR 19:19 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH19_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH19_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH20_ERR 20:20 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH20_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH20_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH21_ERR 21:21 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH21_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH21_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH22_ERR 22:22 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH22_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH22_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH23_ERR 23:23 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH23_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH23_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_M_PIPE_STAGE 29:24 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_M_PIPE_STAGE_NONE 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_M_PIPE_STAGE_VSA 0x01 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_M_PIPE_STAGE_VSB 0x02 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_M_PIPE_STAGE_TI 0x04 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_M_PIPE_STAGE_TS 0x08 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_M_PIPE_STAGE_GS 0x10 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_M_PIPE_STAGE_PS 0x20 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x00405844 /* RWE4R */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2 0x00405848 /* RWE4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH24_ERR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH24_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH24_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH25_ERR 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH25_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH25_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH26_ERR 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH26_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH26_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH27_ERR 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH27_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH27_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH28_ERR 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH28_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH28_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH29_ERR 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH29_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH29_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH30_ERR 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH30_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_SPH30_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_RESET_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_RESET_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_2_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2 0x0040584c /* RWE4R */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH24_ERR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH24_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH24_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH25_ERR 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH25_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH25_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH26_ERR 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH26_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH26_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH27_ERR 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH27_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH27_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH28_ERR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH28_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH28_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH29_ERR 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH29_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH29_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH30_ERR 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH30_ERR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH30_ERR_REPORT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_PM 0x00405850 /* RWE4R */ #define NV_PGRAPH_PRI_DS_PM_SELECT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_DS_PM_SELECT_DS_FLOW_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_DS_FLOW_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_DS_FLOW_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_DS_FLOW_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_DS_FLOW_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_MPIPE_DEBUG_0 0x05 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_MPIPE_INSERT_0 0x06 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_MPIPE_INSERT_1 0x07 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_MPIPE_INSERT_2 0x08 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_PROP_DEBUG_0 0x09 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_PROP_INSERT_0 0x0a /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_ROP_DEBUG_0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_RSTR_DEBUG_0 0x0c /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_VAF_DEBUG_0 0x0d /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_TG_GSINST_0 0x0e /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_TG_GSINST_1 0x0f /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_CGSTATUS 0x10 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_PGSTATUS 0x11 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_BLKACT 0x12 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x13 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x14 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_DEBUG_PM_GROUP_0 0x15 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_SELECT_DEBUG_PM_GROUP_1 0x16 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_DS_PM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_PM_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_SBV_CYA 0x00405854 /* RWI4R */ #define NV_PGRAPH_PRI_DS_SBV_CYA_OVERRIDE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_DS_SBV_CYA_OVERRIDE_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_DS_SBV_CYA_OVERRIDE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x00405858 /* R--4R */ #define NV_PGRAPH_PRI_DS_MPIPE_STATUS_MPIPE_STATUS 5:0 /* R--VF */ #define NV_PGRAPH_PRI_DS_MPIPE_STATUS_PPB_STATUS 11:8 /* R--VF */ #define NV_PGRAPH_PRI_DS_MPIPE_STATUS_SM3_STATUS 13:12 /* R--VF */ #define NV_PGRAPH_PRI_DS_MPIPE_STATUS_SM_NWARPS_STATUS 19:16 /* R--VF */ #define NV_PGRAPH_PRI_DS_MPIPE_STATUS_SM_SIZE_STATUS 21:20 /* R--VF */ #define NV_PGRAPH_PRI_DS_MPIPE_STATUS_SMSPILL_STATUS 26:24 /* R--VF */ #define NV_PGRAPH_PRI_DS_CG 0x00405860 /* RWE4R */ #define NV_PGRAPH_PRI_DS_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_DS_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_DS_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_DS_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_DS_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_DS_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_DS_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_DS_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_DS_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_DS_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_DS_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_DS_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_DS_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_DS_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_DS_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_DS_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_DS_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_DS_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_DS_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_DS_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_DS_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_DS_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_DS_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_DS_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_DS_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_DS_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_DS_CG1 0x00405864 /* RWE4R */ #define NV_PGRAPH_PRI_DS_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_DS_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_DS_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_DS_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_DS_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_DS_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x00405870+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT0 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT0_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT0_1 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT0_2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT0_3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT0_4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT0_5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT0_6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT0_7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT0_8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT1 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT1_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT2 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT2_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT3 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT3_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT4 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT4_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT5 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT5_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT6 27:24 /* RWEVF */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT6_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT7 31:28 /* RWEVF */ #define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC_COUNT7_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE0_START 0x00405c00 /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE0_START_VAL 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE0_START_VAL__INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE0_START_UPPER 0x00405c24 /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE0_START_UPPER_VAL 7:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE0_START_UPPER_VAL__INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE1_START 0x00405c04 /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE1_START_VAL 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE1_START_VAL__INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE1_START_UPPER 0x00405c28 /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE1_START_UPPER_VAL 7:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE1_START_UPPER_VAL__INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE2_START 0x00405c08 /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE2_START_VAL 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE2_START_VAL__INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE2_START_UPPER 0x00405c2c /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE2_START_UPPER_VAL 7:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE2_START_UPPER_VAL__INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE3_START 0x00405c0c /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE3_START_VAL 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE3_START_VAL__INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE3_START_UPPER 0x00405c30 /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE3_START_UPPER_VAL 7:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE3_START_UPPER_VAL__INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE4_START 0x00405c10 /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE4_START_VAL 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE4_START_VAL__INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE4_START_UPPER 0x00405c34 /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE4_START_UPPER_VAL 7:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE4_START_UPPER_VAL__INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE5_START 0x00405c14 /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE5_START_VAL 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE5_START_VAL__INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE5_START_UPPER 0x00405c38 /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE5_START_UPPER_VAL 7:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_STAGE5_START_UPPER_VAL__INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_PROGRAM_REGION_A 0x00405c1c /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_PROGRAM_REGION_A_VAL 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_PROGRAM_REGION_A_VAL__INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_PROGRAM_REGION_B 0x00405c20 /* R--4R */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_PROGRAM_REGION_B_VAL 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_DS_HWW_ESR_SPH_INFO_PROGRAM_REGION_B_VAL__INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_CWD_FS 0x00405b00 /* RWE4R */ #define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_COALESCE_WAITING_PERIOD_UNIT 0x00405b04 /* RWI4R */ #define NV_PGRAPH_PRI_CWD_COALESCE_WAITING_PERIOD_UNIT_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_COALESCE_WAITING_PERIOD_UNIT_V_INIT 0x00000020 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK 0x00405b08 /* RWE4R */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "cwd_cya" /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_PL3_ENABLED_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA 0x00405b10 /* RWE4R */ #define NV_PGRAPH_PRI_CWD_CYA__PRIV_LEVEL_MASK 0x00405b08 /* */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_LAUNCH_QUOTA 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_LAUNCH_QUOTA_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_LAUNCH_QUOTA_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_LAUNCH_QUOTA_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_SINGLE_CTA_ON_SM 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_SINGLE_CTA_ON_SM_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_SINGLE_CTA_ON_SM_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_SINGLE_CTA_ON_SM_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_STATE_COALESCE 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_STATE_COALESCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_STATE_COALESCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_STATE_COALESCE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_CTA_IN_TASK_STATE_BRACKET 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_CTA_IN_TASK_STATE_BRACKET_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_CTA_IN_TASK_STATE_BRACKET_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_CTA_IN_TASK_STATE_BRACKET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_FORCE_SM_SELECT_MODE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_FORCE_SM_SELECT_MODE_LOAD_BALANCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_FORCE_SM_SELECT_MODE_ROUND_ROBIN 0x2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_FORCE_SM_SELECT_MODE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_FORCE_SM_SELECT_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_SINGLE_TASK_STATE_ON_SM 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_SINGLE_TASK_STATE_ON_SM_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_SINGLE_TASK_STATE_ON_SM_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_SINGLE_TASK_STATE_ON_SM_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_COALESCE_TIMEOUT 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_COALESCE_TIMEOUT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_COALESCE_TIMEOUT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_COALESCE_TIMEOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_IGNORE_FREE_SLOT_HINT 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_IGNORE_FREE_SLOT_HINT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_UPGRADE_TASK_FLUSH_TO_PREEMPT_LEVEL 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_UPGRADE_TASK_FLUSH_TO_PREEMPT_LEVEL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_UPGRADE_TASK_FLUSH_TO_PREEMPT_LEVEL_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_UPGRADE_TASK_FLUSH_TO_PREEMPT_LEVEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_FLUSH_SYSMEM 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_FLUSH_SYSMEM_YES 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_FLUSH_SYSMEM_NO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_FLUSH_SYSMEM_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_2XMIO 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_2XMIO_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_STATUS_FILTER_COUNT 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_STATUS_FILTER_COUNT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_NO_GO_IDLE_CANCEL 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_NO_GO_IDLE_CANCEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_RESTRICT_FREE_SLOT_HINT 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_RESTRICT_FREE_SLOT_HINT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_OLDER_TASKS_NOT_HIGHER_PRIORITY 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_OLDER_TASKS_NOT_HIGHER_PRIORITY_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_BATCH_OF_TWO 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_DISABLE_BATCH_OF_TWO_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_BATCH_OF_TWO_OFFSET 22:20 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_BATCH_OF_TWO_OFFSET_INIT 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_BUG2398931_STALL 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_BUG2398931_STALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_BUG2398931_STALL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA_BUG2398931_STALL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA_SPARE 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CYA_SPARE_INIT 0xff /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CYA2 0x00405b14 /* RWI4R */ #define NV_PGRAPH_PRI_CWD_CYA2_CONSTANT_PREFETCH0_BANK 2:0 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_CYA2_CONSTANT_PREFETCH0_BANK_INIT 0x5 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_CYA2_CONSTANT_PREFETCH1_BANK 5:3 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_CYA2_CONSTANT_PREFETCH1_BANK_INIT 0x6 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_CYA2_SMSCC_FEATURE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_CYA2_SMSCC_FEATURE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_CYA2_SMSCC_FEATURE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CYA2_SMSCC_FEATURE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_DELAY_PREEMPT 0x00405b20 /* RWI4R */ #define NV_PGRAPH_PRI_CWD_DELAY_PREEMPT_NUM_CTAS 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_DELAY_PREEMPT_NUM_CTAS_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_DELAY_PREEMPT_TIMEOUT 30:16 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_DELAY_PREEMPT_TIMEOUT_INIT 0x0400 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_DELAY_PREEMPT_ENABLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_DELAY_PREEMPT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_DELAY_PREEMPT_ENABLE_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_DELAY_CILP_PREEMPT 0x00405b24 /* RWI4R */ #define NV_PGRAPH_PRI_CWD_DELAY_CILP_PREEMPT_TIMEOUT 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_DELAY_CILP_PREEMPT_TIMEOUT_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_SCG_HYSTERESIS_TIMER 0x00405b28 /* RWI4R */ #define NV_PGRAPH_PRI_CWD_SCG_HYSTERESIS_TIMER_TIMEOUT 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_SCG_HYSTERESIS_TIMER_TIMEOUT_INIT 0x00006800 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL 0x00405b2c /* RWI4R */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_PARTITIONING_SELECT 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_PARTITIONING_SELECT_NONE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_PARTITIONING_SELECT_STATIC 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_PARTITIONING_SELECT_DYNAMIC 0x2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_SEL 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_SEL_NONE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_SEL_PARTITIONING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_SEL_PARTITIONING_LMEM_BLK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_VEID_OFFSET 21:16 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_VEID_OFFSET_ZERO 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_VEID_OFFSET_MAX 0x3f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_OFFSET 29:24 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_OFFSET_ZERO 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_OFFSET_PARTITIONING_ENABLE_MAX 0x01 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_OFFSET_PARTITIONING_LMEM_BLK_MAX 0x0a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PARTITION_DATA 0x00405b30 /* RWI4R */ #define NV_PGRAPH_PRI_CWD_PARTITION_DATA_REG 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_PARTITION_DATA_REG_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_ESR 0x00405b34 /* RWI4R */ #define NV_PGRAPH_PRI_CWD_ESR_ERROR 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_ESR_ERROR_NONE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_CWD_ESR_ERROR_CLEAR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_ESR_ERROR_CODE1 0x2 /* R---V */ #define NV_PGRAPH_PRI_CWD_ESR_ERROR_CODE2 0x3 /* R---V */ #define NV_PGRAPH_PRI_CWD_ESR_MULTIPLE_ERRORS 8:8 /* R-IVF */ #define NV_PGRAPH_PRI_CWD_ESR_MULTIPLE_ERRORS_NOT_DETECTED 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_CWD_ESR_MULTIPLE_ERRORS_DETECTED 0x1 /* R---V */ #define NV_PGRAPH_PRI_CWD_SCG_CONTROL 0x00405b38 /* RW-4R */ #define NV_PGRAPH_PRI_CWD_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 /* RWXVF */ #define NV_PGRAPH_PRI_CWD_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 /* RWXVF */ #define NV_PGRAPH_PRI_CWD_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 /* RWXVF */ #define NV_PGRAPH_PRI_CWD_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_RESTORE_TIMER 0x00405b3c /* RWI4R */ #define NV_PGRAPH_PRI_CWD_RESTORE_TIMER_TIMEOUT 30:0 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_RESTORE_TIMER_TIMEOUT_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_RESTORE_TIMER_CANCEL_ENABLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_CWD_RESTORE_TIMER_CANCEL_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS 0x00405b44 /* RWE4R */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS_ROW_SELECT 11:0 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS_ROW_SELECT_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS_WORD_SELECT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS_WORD_SELECT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS_RAM_SELECT 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS_RAM_SELECT_NMTT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS_RAM_SELECT_MTT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS_RAM_SELECT_REFCNT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS_RAM_SELECT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS_READ 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS_READ_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_RAM_READ_ADDRESS_READ_PENDING 0x1 /* -W--T */ #define NV_PGRAPH_PRI_CWD_RAM_READ_DATA 0x00405b48 /* R--4R */ #define NV_PGRAPH_PRI_CWD_RAM_READ_DATA_VALUE 31:0 /* R--VF */ #define NV_PGRAPH_PRI_CWD_PM 0x00405b50 /* RWE4R */ #define NV_PGRAPH_PRI_CWD_PM_SELECT 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_STATIC_PATTERN_0X55_8_GROUP 0x000 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_STATIC_PATTERN_0XAA_8_GROUP 0x001 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP0 0x000 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP1 0x001 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP2 0x002 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP3 0x003 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP4 0x004 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP5 0x005 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP6 0x006 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP7 0x007 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP8 0x008 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP9 0x009 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP10 0x00a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP11 0x00b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP12 0x00c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP13 0x00d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP14 0x00e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP15 0x00f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP16 0x010 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP17 0x011 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP18 0x012 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP19 0x013 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP20 0x014 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP21 0x015 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP22 0x016 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP23 0x017 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP24 0x018 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP25 0x019 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP26 0x01a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP27 0x01b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP28 0x01c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP29 0x01d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP30 0x01e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP31 0x01f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP32 0x020 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP33 0x021 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP34 0x022 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP35 0x023 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP36 0x024 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP37 0x025 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP38 0x026 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP39 0x027 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP40 0x028 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP41 0x029 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP42 0x02a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP43 0x02b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP44 0x02c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP45 0x02d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP46 0x02e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP47 0x02f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP48 0x030 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP49 0x031 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP50 0x032 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP51 0x033 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP52 0x034 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP53 0x035 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP54 0x036 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP55 0x037 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP56 0x038 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP57 0x039 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP58 0x03a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP59 0x03b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP60 0x03c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP61 0x03d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP62 0x03e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP63 0x03f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP64 0x040 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP65 0x041 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP66 0x042 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP67 0x043 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP68 0x044 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP69 0x045 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP70 0x046 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP71 0x047 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP72 0x048 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP73 0x049 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP74 0x04a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP75 0x04b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP76 0x04c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP77 0x04d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP78 0x04e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP79 0x04f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP80 0x050 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP81 0x051 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP82 0x052 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP83 0x053 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP84 0x054 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP85 0x055 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP86 0x056 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP87 0x057 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP88 0x058 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP89 0x059 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP90 0x05a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP91 0x05b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP92 0x05c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP93 0x05d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP94 0x05e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP95 0x05f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP96 0x060 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP97 0x061 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP98 0x062 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP99 0x063 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP100 0x064 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP101 0x065 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP102 0x066 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP103 0x067 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP104 0x068 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP105 0x069 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP106 0x06a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP107 0x06b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP108 0x06c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP109 0x06d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP110 0x06e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP111 0x06f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP112 0x070 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP113 0x071 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP114 0x072 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP115 0x073 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP116 0x074 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP117 0x075 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP118 0x076 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP119 0x077 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP120 0x078 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP121 0x079 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP122 0x07a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP123 0x07b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP124 0x07c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP125 0x07d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP126 0x07e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP127 0x07f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP128 0x080 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP129 0x081 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP130 0x082 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP131 0x083 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP132 0x084 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP133 0x085 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP134 0x086 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP135 0x087 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP136 0x088 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP137 0x089 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP138 0x08a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP139 0x08b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP140 0x08c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP141 0x08d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP142 0x08e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP143 0x08f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP144 0x090 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP145 0x091 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP146 0x092 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP147 0x093 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP148 0x094 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP149 0x095 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP150 0x096 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP151 0x097 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP152 0x098 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP153 0x099 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP154 0x09a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP155 0x09b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP156 0x09c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP157 0x09d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP158 0x09e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP159 0x09f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP160 0x0a0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP161 0x0a1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP162 0x0a2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP163 0x0a3 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP164 0x0a4 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP165 0x0a5 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP166 0x0a6 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP167 0x0a7 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP168 0x0a8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP169 0x0a9 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP170 0x0aa /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP171 0x0ab /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP172 0x0ac /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP173 0x0ad /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP174 0x0ae /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP175 0x0af /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP176 0x0b0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP177 0x0b1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP178 0x0b2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP179 0x0b3 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP180 0x0b4 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP181 0x0b5 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP182 0x0b6 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP183 0x0b7 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP184 0x0b8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP185 0x0b9 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP186 0x0ba /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP187 0x0bb /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP188 0x0bc /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP189 0x0bd /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP190 0x0be /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP191 0x0bf /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP192 0x0c0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP193 0x0c1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP194 0x0c2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP195 0x0c3 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP196 0x0c4 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP197 0x0c5 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP198 0x0c6 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP199 0x0c7 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP200 0x0c8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP201 0x0c9 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP202 0x0ca /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP203 0x0cb /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP204 0x0cc /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP205 0x0cd /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP206 0x0ce /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP207 0x0cf /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP208 0x0d0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP209 0x0d1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP210 0x0d2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP211 0x0d3 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP212 0x0d4 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP213 0x0d5 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP214 0x0d6 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP215 0x0d7 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP216 0x0d8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP217 0x0d9 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP218 0x0da /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP219 0x0db /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP220 0x0dc /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP221 0x0dd /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP222 0x0de /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP223 0x0df /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP224 0x0e0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP225 0x0e1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP226 0x0e2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP227 0x0e3 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP228 0x0e4 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP229 0x0e5 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP230 0x0e6 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP231 0x0e7 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP232 0x0e8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP233 0x0e9 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP234 0x0ea /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP235 0x0eb /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP236 0x0ec /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP237 0x0ed /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP238 0x0ee /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP239 0x0ef /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP240 0x0f0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP241 0x0f1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP242 0x0f2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP243 0x0f3 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP244 0x0f4 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP245 0x0f5 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP246 0x0f6 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP247 0x0f7 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP248 0x0f8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP249 0x0f9 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP250 0x0fa /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP251 0x0fb /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP252 0x0fc /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP253 0x0fd /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP254 0x0fe /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP255 0x0ff /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP256 0x100 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP257 0x101 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP258 0x102 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP259 0x103 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP260 0x104 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP261 0x105 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP262 0x106 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP263 0x107 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP264 0x108 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP265 0x109 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP266 0x10a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP267 0x10b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP268 0x10c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP269 0x10d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP270 0x10e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP271 0x10f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP272 0x110 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP273 0x111 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP274 0x112 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP275 0x113 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP276 0x114 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP277 0x115 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP278 0x116 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP279 0x117 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP280 0x118 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP281 0x119 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP282 0x11a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP283 0x11b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP284 0x11c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP285 0x11d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP286 0x11e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP287 0x11f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP288 0x120 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP289 0x121 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP290 0x122 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP291 0x123 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP292 0x124 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP293 0x125 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP294 0x126 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP295 0x127 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP296 0x128 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP297 0x129 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP298 0x12a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP299 0x12b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP300 0x12c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP301 0x12d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP302 0x12e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP303 0x12f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP304 0x130 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP305 0x131 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP306 0x132 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP307 0x133 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP308 0x134 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP309 0x135 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP310 0x136 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP311 0x137 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP312 0x138 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP313 0x139 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP314 0x13a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP315 0x13b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP316 0x13c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP317 0x13d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP318 0x13e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP319 0x13f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP320 0x140 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP321 0x141 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP322 0x142 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP323 0x143 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP324 0x144 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP325 0x145 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP326 0x146 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP327 0x147 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP328 0x148 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP329 0x149 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP330 0x14a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP331 0x14b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP332 0x14c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP333 0x14d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP334 0x14e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP335 0x14f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP336 0x150 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP337 0x151 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP338 0x152 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP339 0x153 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP340 0x154 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP341 0x155 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP342 0x156 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP343 0x157 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP344 0x158 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP345 0x159 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP346 0x15a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP347 0x15b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP348 0x15c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP349 0x15d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP350 0x15e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP351 0x15f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP352 0x160 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP353 0x161 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP354 0x162 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP355 0x163 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP356 0x164 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP357 0x165 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP358 0x166 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP359 0x167 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP360 0x168 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP361 0x169 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP362 0x16a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP363 0x16b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP364 0x16c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP365 0x16d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP366 0x16e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP367 0x16f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP368 0x170 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP369 0x171 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP370 0x172 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP371 0x173 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP372 0x174 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP373 0x175 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP374 0x176 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP375 0x177 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP376 0x178 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP377 0x179 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP378 0x17a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP379 0x17b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP380 0x17c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP381 0x17d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP382 0x17e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP383 0x17f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP384 0x180 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP385 0x181 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP386 0x182 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP387 0x183 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP388 0x184 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP389 0x185 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP390 0x186 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP391 0x187 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP392 0x188 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP393 0x189 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP394 0x18a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP395 0x18b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP396 0x18c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP397 0x18d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP398 0x18e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP399 0x18f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP400 0x190 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP401 0x191 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP402 0x192 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP403 0x193 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP404 0x194 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP405 0x195 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP406 0x196 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP407 0x197 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP408 0x198 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP409 0x199 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP410 0x19a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP411 0x19b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP412 0x19c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP413 0x19d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP414 0x19e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP415 0x19f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP416 0x1a0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP417 0x1a1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP418 0x1a2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP419 0x1a3 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP420 0x1a4 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP421 0x1a5 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP422 0x1a6 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP423 0x1a7 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP424 0x1a8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP425 0x1a9 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP426 0x1aa /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP427 0x1ab /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP428 0x1ac /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP429 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP430 0x1ae /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP431 0x1af /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP432 0x1b0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP433 0x1b1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP434 0x1b2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP435 0x1b3 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP436 0x1b4 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP437 0x1b5 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP438 0x1b6 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP439 0x1b7 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP440 0x1b8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP441 0x1b9 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP442 0x1ba /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP443 0x1bb /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP444 0x1bc /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP445 0x1bd /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP446 0x1be /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP447 0x1bf /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP448 0x1c0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP449 0x1c1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP450 0x1c2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP451 0x1c3 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP452 0x1c4 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP453 0x1c5 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP454 0x1c6 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP455 0x1c7 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP456 0x1c8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP457 0x1c9 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP458 0x1ca /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP459 0x1cb /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP460 0x1cc /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP461 0x1cd /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP462 0x1ce /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP463 0x1cf /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP464 0x1d0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP465 0x1d1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP466 0x1d2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP467 0x1d3 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP468 0x1d4 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP469 0x1d5 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP470 0x1d6 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP471 0x1d7 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP472 0x1d8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP473 0x1d9 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP474 0x1da /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP475 0x1db /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP476 0x1dc /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP477 0x1dd /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP478 0x1de /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP479 0x1df /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP480 0x1e0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP481 0x1e1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP482 0x1e2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP483 0x1e3 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP484 0x1e4 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP485 0x1e5 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP486 0x1e6 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP487 0x1e7 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP488 0x1e8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP489 0x1e9 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP490 0x1ea /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP491 0x1eb /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP492 0x1ec /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP493 0x1ed /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP494 0x1ee /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP495 0x1ef /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP496 0x1f0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP497 0x1f1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP498 0x1f2 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP499 0x1f3 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP500 0x1f4 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP501 0x1f5 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP502 0x1f6 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP503 0x1f7 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP504 0x1f8 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP505 0x1f9 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP506 0x1fa /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP507 0x1fb /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP508 0x1fc /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP509 0x1fd /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP510 0x1fe /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP511 0x1ff /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP512 0x200 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP513 0x201 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP514 0x202 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP515 0x203 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP516 0x204 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP517 0x205 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP518 0x206 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP519 0x207 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP520 0x208 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP521 0x209 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP522 0x20a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP523 0x20b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP524 0x20c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP525 0x20d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP526 0x20e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP527 0x20f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP528 0x210 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP529 0x211 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP530 0x212 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP531 0x213 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP532 0x214 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP533 0x215 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP534 0x216 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP535 0x217 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP536 0x218 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP537 0x219 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP538 0x21a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP539 0x21b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP540 0x21c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP541 0x21d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP542 0x21e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP543 0x21f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP544 0x220 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP545 0x221 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP546 0x222 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP547 0x223 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP548 0x224 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP549 0x225 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP550 0x226 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP551 0x227 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP552 0x228 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP553 0x229 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP554 0x22a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP555 0x22b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP556 0x22c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP557 0x22d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP558 0x22e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP559 0x22f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP560 0x230 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP561 0x231 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP562 0x232 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP563 0x233 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP564 0x234 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP565 0x235 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP566 0x236 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP567 0x237 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP568 0x238 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP569 0x239 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP570 0x23a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP571 0x23b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP572 0x23c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP573 0x23d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP574 0x23e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP575 0x23f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP576 0x240 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP577 0x241 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP578 0x242 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP579 0x243 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP580 0x244 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP581 0x245 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP582 0x246 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP583 0x247 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP584 0x248 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP585 0x249 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP586 0x24a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP587 0x24b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP588 0x24c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP589 0x24d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP590 0x24e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP591 0x24f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP592 0x250 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP593 0x251 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP594 0x252 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP595 0x253 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP596 0x254 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP597 0x255 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP598 0x256 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP599 0x257 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP600 0x258 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP601 0x259 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP602 0x25a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP603 0x25b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP604 0x25c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP605 0x25d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP606 0x25e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP607 0x25f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP608 0x260 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP609 0x261 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP610 0x262 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP611 0x263 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP612 0x264 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP613 0x265 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP614 0x266 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP615 0x267 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP616 0x268 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP617 0x269 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP618 0x26a /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP619 0x26b /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP620 0x26c /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP621 0x26d /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP622 0x26e /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_GROUP623 0x26f /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_SELECT_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_PM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_PM_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID(i) (0x00405b60+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID__SIZE_1 16 /* */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC0 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC0 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC1 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC1 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC2 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC2 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC3 27:24 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC3 31:28 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_SM_ID(i) (0x00405ba0+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_CWD_SM_ID__SIZE_1 16 /* */ #define NV_PGRAPH_PRI_CWD_SM_ID_TPC0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_SM_ID_TPC0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_SM_ID_TPC1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_SM_ID_TPC1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_SM_ID_TPC2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_SM_ID_TPC2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_SM_ID_TPC3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_SM_ID_TPC3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CG 0x00405bf0 /* RWE4R */ #define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_CWD_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_CWD_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_CWD_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_CWD_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_CWD_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_CWD_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_CWD_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_CWD_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_CWD_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_CWD_CG1 0x00405bf4 /* RWE4R */ #define NV_PGRAPH_PRI_CWD_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CG1_SLCG 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_CWD_CG1_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_CWD_CG1_SLCG_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_CWD_CG1_SLCG__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D 0x00407fff:0x00407800 /* RW--L */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG 0x00407804 /* RWI4R */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_PFC_DATA_MERGE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_PFC_DATA_MERGE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_BUNDLE_PACKING 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_BUNDLE_PACKING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_BUNDLE_PACKING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_BUNDLE_PACKING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_EMPTYCLIP_CYA 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_EMPTYCLIP_CYA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_EMPTYCLIP_CYA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_EMPTYCLIP_CYA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_RECT_HIDDEN_CYA 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_RECT_HIDDEN_CYA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_RECT_HIDDEN_CYA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_RECT_HIDDEN_CYA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_BDCAST_CYA 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_BDCAST_CYA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_BDCAST_CYA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_BDCAST_CYA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_FLUSHROP_CYA 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_FLUSHROP_CYA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_FLUSHROP_CYA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_FLUSHROP_CYA_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_BLKACTIVITY_DISABLE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_SAVED 31:7 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_DEBUG_SAVED_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL 0x00407808 /* RWE4R */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRP0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRPA 0xa /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRPB 0xb /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRPC 0xc /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_GRPD 0xd /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_PERF_SEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP(i) (0x0040780c+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP__SIZE_1 43 /* */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP_TILE0 4:0 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP_TILE0_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP_TILE1 9:5 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP_TILE1_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP_TILE2 14:10 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP_TILE2_INIT 0x02 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP_TILE3 19:15 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP_TILE3_INIT 0x03 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP_TILE4 24:20 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP_TILE4_INIT 0x04 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP_TILE5 29:25 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_GPC_MAP_TILE5_INIT 0x05 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x004078bc /* RWI4R */ #define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET_INIT 0x03 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_RSTR2D_CG 0x004078c0 /* RWE4R */ #define NV_PGRAPH_PRI_RSTR2D_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_RSTR2D_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_RSTR2D_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_RSTR2D_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_RSTR2D_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_RSTR2D_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_RSTR2D_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_RSTR2D_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_RSTR2D_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_RSTR2D_CG1 0x004078c4 /* RWE4R */ #define NV_PGRAPH_PRI_RSTR2D_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_RSTR2D_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_RSTR2D_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_RSTR2D_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_RSTR2D_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_RSTR2D_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PGRAPH_PRI_PDB 0x004059ff:0x00405900 /* RW--L */ #define NV_PGRAPH_PRI_PDB_CONFIG 0x00405900 /* RWI4R */ #define NV_PGRAPH_PRI_PDB_CONFIG_RESERVED 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_PDB_CONFIG_RESERVED_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_PDB_CONFIG_XBAR_PRIORITY 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_PDB_CONFIG_XBAR_PRIORITY_ROUND_ROBIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CONFIG_XBAR_PRIORITY_ALPHA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CONFIG_XBAR_PRIORITY_BETA 0x2 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CONFIG_XBAR_PRIORITY_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_PDB_CONFIG_BETA_FIFO_REDUCE_DIV32 24:19 /* RWIVF */ #define NV_PGRAPH_PRI_PDB_CONFIG_BETA_FIFO_REDUCE_DIV32_FULLSIZE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CONFIG_BETA_FIFO_REDUCE_DIV32_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_PDB_CONFIG_TOKEN_FIFO_REDUCE_DIV32 31:25 /* RWIVF */ #define NV_PGRAPH_PRI_PDB_CONFIG_TOKEN_FIFO_REDUCE_DIV32_FULLSIZE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CONFIG_TOKEN_FIFO_REDUCE_DIV32_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_PDB_STATUS 0x00405904 /* R--4R */ #define NV_PGRAPH_PRI_PDB_STATUS_DIST_FSM 2:0 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_DIST_FSM_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_PDB_PM 0x00405908 /* RWE4R */ #define NV_PGRAPH_PRI_PDB_PM_SELECT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TRAFFIC_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TRAFFIC_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TASK_FIFO_0_STATUS 0x02 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TASK_FIFO_1_STATUS 0x03 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TASK_FIFO_2_STATUS 0x04 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TASK_FIFO_3_STATUS 0x05 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TASK_FIFO_4_STATUS 0x06 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TASK_FIFO_5_STATUS 0x07 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TASK_FIFO_6_STATUS 0x08 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TASK_FIFO_7_STATUS 0x09 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_IO_0 0x0a /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_ALPHA_CREDITS_0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_ALPHA_CREDITS_1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_BETA_CREDITS_0 0x0d /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_BETA_CREDITS_1 0x0e /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_BLK_ACT 0x0f /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_STATUS 0x10 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_CG 0x11 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_PG 0x12 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_STALLS_0 0x13 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TASK_FIFOS_0 0x14 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TASK_FIFOS_1 0x15 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TRAFFIC_2 0x16 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_STALLS_1 0x17 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_IO_1 0x18 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_IO_2 0x19 /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_TRAFFIC_3 0x1a /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_COMPUTE_CREDITS_0 0x1b /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_COMPUTE_CREDITS_1 0x1c /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_XBAR_ARBITER 0x1d /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x1e /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x1f /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_SELECT_MAX 0x1f /* RW--V */ #define NV_PGRAPH_PRI_PDB_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_PDB_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PDB_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CG 0x0040590c /* RWE4R */ #define NV_PGRAPH_PRI_PDB_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_PDB_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_PDB_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_PDB_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PDB_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_PDB_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_PDB_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_PDB_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_PDB_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_PDB_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_PDB_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PDB_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_PDB_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_PDB_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_PDB_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_PDB_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PDB_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_PDB_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_PDB_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_PDB_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_PDB_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_PDB_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_PDB_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_PDB_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_PDB_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_PDB_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_PDB_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_PDB_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_PDB_CG1 0x00405910 /* RWE4R */ #define NV_PGRAPH_PRI_PDB_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_PDB_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_PDB_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_PDB_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_PDB_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_PDB_CG1_SLCG__PROD 0x7ffffff8 /* RW--V */ #define NV_PGRAPH_PRI_PDB_STATUS_SCC_IN 0x00405918 /* R--4R */ #define NV_PGRAPH_PRI_PDB_STATUS_SCC_IN_SCC_IN 2:0 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_SCC_IN_SCC_IN_PIPE 6:4 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_SCC_IN_ALPHA_FIFO 10:8 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_SCC_IN_BETA_FIFO 14:12 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_SCC_IN_NEXTGPC_SKID 18:16 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_SCC_IN_TOKEN_FIFO 22:20 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_SCC_IN_TOKEN_SKID 26:24 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_TASK_CTRL 0x0040591c /* R--4R */ #define NV_PGRAPH_PRI_PDB_STATUS_TASK_CTRL_TASK_CTRL 2:0 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_TASK_CTRL_TASK_FIFO 6:4 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_PDB 0x00405920 /* R--4R */ #define NV_PGRAPH_PRI_PDB_STATUS_PDB_SCC2PDB 2:0 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_PDB_XBAR2PDB_MSG 8:6 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_PDB_PDB2XBAR_STATE_WT 14:12 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_PDB_SCC_IN 17:15 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_PDB_TASK_CTRL 20:18 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_PDB_XBAR_ARB 23:21 /* R--VF */ #define NV_PGRAPH_PRI_PDB_STATUS_PDB_XBAR 26:24 /* R--VF */ #define NV_PGRAPH_PRI_SCC 0x004087ff:0x00408000 /* RW--L */ #define NV_PGRAPH_PRI_SCC_DEBUG 0x00408000 /* RWI4R */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGE_CACHE 2:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGE_CACHE_FULL_SIZE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGE_CACHE_THREE_QUARTERS_SIZE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGE_CACHE_HALF_SIZE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGE_CACHE_QUARTER_SIZE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGE_CACHE_DISABLE 0x4 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGE_CACHE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_LC_FEEDBACK 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_LC_FEEDBACK_NONBLOCKING 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_LC_FEEDBACK_BLOCKING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_LC_FEEDBACK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_LC_BUFFER_OPEN 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_LC_BUFFER_OPEN_FEEDBACKBASED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_LC_BUFFER_OPEN_ALWAYS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_LC_BUFFER_OPEN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_SPARE_5 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_SPARE_5_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_BUNDLE_PACKING 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_BUNDLE_PACKING_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_BUNDLE_PACKING_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_BUNDLE_PACKING_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_SYNC_HYSTERESIS 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_SYNC_HYSTERESIS_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_SYNC_HYSTERESIS_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_SYNC_HYSTERESIS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CBE_INVALIDATES 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_CBE_INVALIDATES_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CBE_INVALIDATES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CBE_INVALIDATES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGEPOOL_INVALIDATES 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGEPOOL_INVALIDATES_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGEPOOL_INVALIDATES_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGEPOOL_INVALIDATES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_FEEDBACK_VERSION_FLUSHES_CBE 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_FEEDBACK_VERSION_FLUSHES_CBE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_FEEDBACK_VERSION_FLUSHES_CBE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_FEEDBACK_VERSION_FLUSHES_CBE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_IMC_INVALIDATE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_IMC_INVALIDATE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_IMC_INVALIDATE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_IMC_INVALIDATE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_UPDATE_WRITE_COMBINER 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_UPDATE_WRITE_COMBINER_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_UPDATE_WRITE_COMBINER_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_UPDATE_WRITE_COMBINER_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_WORLD_BUNDLE_FLUSHES_CBE 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_WORLD_BUNDLE_FLUSHES_CBE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_WORLD_BUNDLE_FLUSHES_CBE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_WORLD_BUNDLE_FLUSHES_CBE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_BLOCK_WRITES_WITHOUT_GCC_CREDIT 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_BLOCK_WRITES_WITHOUT_GCC_CREDIT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_BLOCK_WRITES_WITHOUT_GCC_CREDIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_BLOCK_WRITES_WITHOUT_GCC_CREDIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_SPARE_15 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_SPARE_15_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_CACHE_COPY_SERIALIZE 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_CACHE_COPY_SERIALIZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_CACHE_COPY_SERIALIZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_CACHE_COPY_SERIALIZE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_GCC_MSG_SERIALIZE 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_GCC_MSG_SERIALIZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_GCC_MSG_SERIALIZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_GCC_MSG_SERIALIZE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_CACHE_WC_SERIALIZE 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_CACHE_WC_SERIALIZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_CACHE_WC_SERIALIZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_CACHE_WC_SERIALIZE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_LD_CONST_ALIGN_SERIALIZE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_LD_CONST_ALIGN_SERIALIZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_LD_CONST_ALIGN_SERIALIZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_LD_CONST_ALIGN_SERIALIZE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_PREFER_FEEDBACK_UNBIND 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_PREFER_FEEDBACK_UNBIND_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_PREFER_FEEDBACK_UNBIND_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_PREFER_FEEDBACK_UNBIND_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_PREFER_FEEDBACK_SYNC 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_PREFER_FEEDBACK_SYNC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_PREFER_FEEDBACK_SYNC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_PREFER_FEEDBACK_SYNC_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_BLOCK_DEALLOC_WITHOUT_GCC_CREDIT 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_BLOCK_DEALLOC_WITHOUT_GCC_CREDIT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_BLOCK_DEALLOC_WITHOUT_GCC_CREDIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_BLOCK_DEALLOC_WITHOUT_GCC_CREDIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_REDUNDANT_BIND_OPT 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_REDUNDANT_BIND_OPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_REDUNDANT_BIND_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_REDUNDANT_BIND_OPT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGE_CACHE_INVALIDATES 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGE_CACHE_INVALIDATES_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGE_CACHE_INVALIDATES_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_PAGE_CACHE_INVALIDATES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_SPARE_25 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_SPARE_25_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_BLKACTIVITY 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_BLKACTIVITY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_BLKACTIVITY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_BLKACTIVITY_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_PAGEPOOL_WRITE_CLAMPING 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_PAGEPOOL_WRITE_CLAMPING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_PAGEPOOL_WRITE_CLAMPING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_CYA_PAGEPOOL_WRITE_CLAMPING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_DEBUG_SPARE 31:28 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_SPARE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x00408004 /* RWI4R */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_BYTE_GRANULARITY 0x00000100 /* */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 0x00000008 /* */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x00408008 /* RWI4R */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x030 /* RW--V */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 /* */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x0040800c /* RWI4R */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_BYTE_GRANULARITY 0x00000100 /* */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 0x00000008 /* */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x00408010 /* RWI4R */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x200 /* RW--V */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 /* */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 19:10 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES_MAX 0x1f6 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY 0x00408014 /* RWI4R */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_CONSTBUFF 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_CONSTBUFF_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_CONSTBUFF_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_CONSTBUFF_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_PAGEPOOL 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_PAGEPOOL_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_PAGEPOOL_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_PAGEPOOL_LAST 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_CBE 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_CBE_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_CBE_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_CBE_LAST 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_RTV 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_RTV_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_RTV_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_EVICT_POLICY_RTV_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CYA_CBE_FLUSHER 0x00408018 /* RWI4R */ #define NV_PGRAPH_PRI_SCC_CYA_CBE_FLUSHER_BUNDLE_ADDR_0 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_CYA_CBE_FLUSHER_BUNDLE_ADDR_0_GO_IDLE 0xe100 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_CYA_CBE_FLUSHER_BUNDLE_ADDR_0__PROD 0x00bb /* RW--V */ #define NV_PGRAPH_PRI_SCC_CYA_CBE_FLUSHER_BUNDLE_ADDR_1 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_CYA_CBE_FLUSHER_BUNDLE_ADDR_1_GO_IDLE 0xe100 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_CYA_CBE_FLUSHER_BUNDLE_ADDR_1__PROD 0x083e /* RW--V */ #define NV_PGRAPH_PRI_SCC_GFXP_MAX_CBTBL_IN_USE 0x0040801c /* RWI4R */ #define NV_PGRAPH_PRI_SCC_GFXP_MAX_CBTBL_IN_USE_ENTRIES 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_GFXP_MAX_CBTBL_IN_USE_ENTRIES_VALUE 0x1f6 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_HWW_ESR 0x00408030 /* RWE4R */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_INTR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_INTR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_INTR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_LDCONST_OOB 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_LDCONST_OOB_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_LDCONST_OOB_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_LDROOTTABLE_OOB 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_LDROOTTABLE_OOB_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_LDROOTTABLE_OOB_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_CONSTBUFF_BASE 0x00408034 /* R--4R */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_CONSTBUFF_BASE_ADDR_DIV_256B 31:0 /* R--VF */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_CONSTBUFF 0x00408038 /* R--4R */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_CONSTBUFF_CONST_DW_OFFSET 14:0 /* R--VF */ #define NV_PGRAPH_PRI_SCC_HWW_ESR_CONSTBUFF_SIZE_IN_DW 30:16 /* R--VF */ #define NV_PGRAPH_PRI_SCC_PERFMON 0x0040803c /* RWE4R */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_16 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_STATIC_PATTERN_AA_8_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_SELECT_STATIC_PATTERN_55_8_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_SCC_PERFMON_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_PERFMON_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SCC_CG 0x00408040 /* RWE4R */ #define NV_PGRAPH_PRI_SCC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_SCC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_SCC_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_SCC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SCC_CG_IDLE_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_SCC_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_SCC_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_SCC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_SCC_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_SCC_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_SCC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SCC_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_SCC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_SCC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_SCC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SCC_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_SCC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_SCC_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_SCC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_SCC_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_SCC_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_SCC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_SCC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_SCC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_SCC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_SCC_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_SCC_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SCC_CG1 0x00408044 /* RWE4R */ #define NV_PGRAPH_PRI_SCC_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_SCC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SCC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CG1_SLCG 11:1 /* RWEVF */ #define NV_PGRAPH_PRI_SCC_CG1_SLCG_ENABLED 0x000 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CG1_SLCG_DISABLED 0x7ff /* RWE-V */ #define NV_PGRAPH_PRI_SCC_CG1_SLCG__PROD 0x000 /* RW--V */ #define NV_PGRAPH_PRI_SCC_LDCONST_DFT_TRIGGER 0x00408064 /* RWI4R */ #define NV_PGRAPH_PRI_SCC_LDCONST_DFT_TRIGGER_DW_OFFSET 15:2 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_LDCONST_DFT_TRIGGER_DW_OFFSET_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_LDCONST_DFT_TRIGGER_CBTBL_INDEX 24:16 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_LDCONST_DFT_TRIGGER_CBTBL_INDEX_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_LDCONST_DFT_TRIGGER_MODE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_LDCONST_DFT_TRIGGER_MODE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_LDCONST_DFT_TRIGGER_MODE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_RM_RTV_CB_BASE 0x00408070 /* RWI4R */ #define NV_PGRAPH_PRI_SCC_RM_RTV_CB_BASE_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_RM_RTV_CB_BASE_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_RM_RTV_CB_BASE_ADDR_39_8_ALIGN_BITS 0x00000008 /* */ #define NV_PGRAPH_PRI_SCC_RM_RTV_CB_SIZE 0x00408074 /* RWI4R */ #define NV_PGRAPH_PRI_SCC_RM_RTV_CB_SIZE_DIV_256B 14:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_RM_RTV_CB_SIZE_DIV_256B_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_RM_RTV_CB_SIZE_DIV_256B__PROD 0x0800 /* RW--V */ #define NV_PGRAPH_PRI_SCC_RM_RTV_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x0100 /* */ #define NV_PGRAPH_PRI_SCC_RM_RTV_CB_SIZE_DIV_256B_DEFAULT 0x0800 /* RW--V */ #define NV_PGRAPH_PRI_SCC_RM_RTV_CB_SIZE_DIV_256B_DB_ADDER 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_SCC_RM_RTV_CB_SIZE_DIV_256B_GFXP_ADDER 0x0020 /* RW--V */ #define NV_PGRAPH_PRI_SCC_RM_GFXP_RESERVE 0x00408078 /* RWI4R */ #define NV_PGRAPH_PRI_SCC_RM_GFXP_RESERVE_RTV_CB_SIZE_DIV_256B 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_RM_GFXP_RESERVE_RTV_CB_SIZE_DIV_256B_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_RM_GFXP_RESERVE_RTV_CB_SIZE_DIV_256B_DEFAULT 0x020 /* RW--V */ #define NV_PGRAPH_PRI_SCC_RTV_CB_MGMT 0x0040807c /* RWI4R */ #define NV_PGRAPH_PRI_SCC_RTV_CB_MGMT_MAX_AGE_SKEW 13:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_RTV_CB_MGMT_MAX_AGE_SKEW_INIT 0x0080 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_RTV_CB_MGMT_FEEDBACK_GRANULARITY 29:14 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_RTV_CB_MGMT_FEEDBACK_GRANULARITY_INIT 0x0080 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_CYA 0x00408080 /* RWI4R */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_FORCE_GROUPS_TO_SAME_RTV 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_FORCE_GROUPS_TO_SAME_RTV_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_FORCE_GROUPS_TO_SAME_RTV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_FORCE_GROUPS_TO_SAME_RTV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_FORCE_FULL_REFRESH_ON_CB_WRAP 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_FORCE_FULL_REFRESH_ON_CB_WRAP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_FORCE_FULL_REFRESH_ON_CB_WRAP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_FORCE_FULL_REFRESH_ON_CB_WRAP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_FULL_DIRTY_ON_INVALIDATE_CB 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_FULL_DIRTY_ON_INVALIDATE_CB_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_FULL_DIRTY_ON_INVALIDATE_CB_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_FULL_DIRTY_ON_INVALIDATE_CB_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_GATE_ON_WT 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_GATE_ON_WT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_GATE_ON_WT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_CYA_RTV_GATE_ON_WT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_2 0x00408084 /* RWI4R */ #define NV_PGRAPH_PRI_SCC_DEBUG_2_FB_SYNC_EMISSION 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_SCC_DEBUG_2_FB_SYNC_EMISSION_CLASSIC 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_2_FB_SYNC_EMISSION_GO_IDLE_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SCC_DEBUG_2_FB_SYNC_EMISSION_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_SSYNC 0x00405aff:0x00405a00 /* RW--L */ #define NV_PGRAPH_PRI_SSYNC_PERFMON 0x00405a00 /* RWI4R */ #define NV_PGRAPH_PRI_SSYNC_PERFMON_SELECT 2:0 /* RWIVF */ #define NV_PGRAPH_PRI_SSYNC_PERFMON_SELECT_NUM_FIRST_REQUESTS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SSYNC_PERFMON_SELECT_NUM_SECOND_REQUESTS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SSYNC_PERFMON_SELECT_SSYNC_STATUS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_SSYNC_PERFMON_SELECT_FIFOS_STATUS 0x3 /* RW--V */ #define NV_PGRAPH_PRI_SSYNC_PERFMON_SELECT_STATIC_PATTERN_0A_5_GROUP 0x4 /* RW--V */ #define NV_PGRAPH_PRI_SSYNC_PERFMON_SELECT_STATIC_PATTERN_15_5_GROUP 0x5 /* RW--V */ #define NV_PGRAPH_PRI_SSYNC_PERFMON_SELECT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_SSYNC_BATCHID 0x00405a04 /* RWI4R */ #define NV_PGRAPH_PRI_SSYNC_BATCHID_BITS 14:0 /* RWIVF */ #define NV_PGRAPH_PRI_SSYNC_BATCHID_BITS_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_SSYNC_CURR_BATCHID 0x00405a08 /* R--4R */ #define NV_PGRAPH_PRI_SSYNC_CURR_BATCHID_BITS 14:0 /* R--VF */ #define NV_PGRAPH_PRI_SSYNC_CURR_TASKID 0x00405a0c /* R--4R */ #define NV_PGRAPH_PRI_SSYNC_CURR_TASKID_BITS 22:0 /* R--VF */ #define NV_PGRAPH_PRI_SSYNC_FSM_STATES 0x00405a10 /* R--4R */ #define NV_PGRAPH_PRI_SSYNC_FSM_STATES_BATCHID_FSM 1:0 /* R--VF */ #define NV_PGRAPH_PRI_SSYNC_FSM_STATES_SECONDREQ_FSM 3:2 /* R--VF */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR 0x00405a14 /* RWE4R */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_FRT_OVERWRITE 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_FRT_OVERWRITE_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_FRT_OVERWRITE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_SRT_OVERWRITE 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_SRT_OVERWRITE_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_SRT_OVERWRITE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_OPERATIONS_FIFO_ERROR 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_OPERATIONS_FIFO_ERROR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_OPERATIONS_FIFO_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_BAD_TASK_ID 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_BAD_TASK_ID_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_BAD_TASK_ID_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_FRT_WRITE_CONFLICT 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_FRT_WRITE_CONFLICT_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_FRT_WRITE_CONFLICT_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SSYNC_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SSYNC_TASKID 0x00405a18 /* RWI4R */ #define NV_PGRAPH_PRI_SSYNC_TASKID_BITS 22:0 /* RWIVF */ #define NV_PGRAPH_PRI_SSYNC_TASKID_BITS_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_SSYNC_SLCG_EN 0x00405a1c /* RWI4R */ #define NV_PGRAPH_PRI_SSYNC_SLCG_EN_BITS 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_SSYNC_SLCG_EN_BITS_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_SKED 0x004073ff:0x00407000 /* RW--L */ #define NV_PGRAPH_PRI_SKED_CG 0x00407000 /* RWE4R */ #define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_SKED_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_SKED_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_SKED_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_SKED_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_SKED_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_SKED_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_SKED_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG_PAUSE_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_SKED_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CG1 0x00407004 /* RWE4R */ #define NV_PGRAPH_PRI_SKED_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CG1_SLCG__PROD 0x01 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM 0x00407010 /* RWE4R */ #define NV_PGRAPH_PRI_SKED_PM_SELECT 10:0 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CG 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_PG 0x001 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_PP0 0x004 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_PP1 0x005 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_PP2 0x006 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_PP3 0x007 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_PP4 0x008 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE0 0x009 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE1 0x00a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE2 0x00b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE3 0x00c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_FBI0 0x00d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_FBI1 0x00e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_FBI2 0x00f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_FBI3 0x010 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM0 0x011 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM1 0x012 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM2 0x013 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM3 0x014 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM4 0x015 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM5 0x016 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM6 0x017 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM7 0x018 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TFL0 0x019 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TFL1 0x01a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TFL2 0x01b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TFL3 0x01c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE4 0x01e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE5 0x01f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS0 0x020 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS1 0x021 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS2 0x022 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS3 0x023 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS4 0x024 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS5 0x025 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS6 0x026 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS7 0x027 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS8 0x028 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS9 0x029 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS10 0x02a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS11 0x02b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATUS12 0x02c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CACHE0 0x030 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CACHE1 0x031 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CACHE2 0x032 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CACHE3 0x033 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CACHE4 0x034 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD0 0x038 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD1 0x039 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_HINT0 0x03c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_HINT1 0x03d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS0 0x040 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS1 0x041 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS2 0x042 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS3 0x043 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS4 0x044 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS5 0x045 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS6 0x046 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS7 0x047 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS8 0x048 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS9 0x049 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS10 0x04a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS11 0x04b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS12 0x04c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS13 0x04d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS14 0x04e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS15 0x04f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS16 0x050 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS17 0x051 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS18 0x052 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS19 0x053 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS20 0x054 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS21 0x055 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS22 0x056 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS23 0x057 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS24 0x058 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS25 0x059 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS26 0x05a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS27 0x05b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS28 0x05c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS29 0x05d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS30 0x05e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS31 0x05f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CWD_SLOTS32 0x060 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_LIST_VLD0 0x061 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_LIST_VLD1 0x062 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_LIST_VLD2 0x063 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_LIST_VLD3 0x064 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_LIST_VLD4 0x065 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_LIST_VLD5 0x066 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_LIST_VLD6 0x067 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_LIST_VLD7 0x068 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE6 0x069 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE7 0x06a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM8 0x06b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM9 0x06c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM10 0x06d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_IQ0 0x070 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_IQ1 0x071 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_IQ2 0x072 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_IQ3 0x073 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_IQ4 0x074 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_IQ5 0x075 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_IQ6 0x076 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_IQ7 0x077 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_IQ8 0x078 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATIC_PATTERN_0X55_8_GROUP 0x079 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_STATIC_PATTERN_0XAA_8_GROUP 0x07a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_0 0x07b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_1 0x07c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_2 0x07d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_3 0x07e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_4 0x07f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_5 0x080 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_6 0x081 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_7 0x082 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_8 0x083 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_9 0x084 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_10 0x085 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_11 0x086 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_12 0x087 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_13 0x088 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_14 0x089 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_15 0x08a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_16 0x08b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_17 0x08c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_18 0x08d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_19 0x08e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_20 0x08f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_21 0x090 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_22 0x091 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_23 0x092 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_24 0x093 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_25 0x094 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_26 0x095 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_27 0x096 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_28 0x097 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_29 0x098 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_30 0x099 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_31 0x09a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_32 0x09b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_33 0x09c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_34 0x09d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_35 0x09e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_36 0x09f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_37 0x0a0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_38 0x0a1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_39 0x0a2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_40 0x0a3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_41 0x0a4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_42 0x0a5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_43 0x0a6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_44 0x0a7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_45 0x0a8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_46 0x0a9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_47 0x0aa /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_48 0x0ab /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_49 0x0ac /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_50 0x0ad /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_51 0x0ae /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_52 0x0af /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_53 0x0b0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_54 0x0b1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_55 0x0b2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_56 0x0b3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_57 0x0b4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_58 0x0b5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_59 0x0b6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_60 0x0b7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_61 0x0b8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_62 0x0b9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_COUNT_63 0x0ba /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_PENDS_0_7 0x0bb /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_PENDS_8_15 0x0bc /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_PENDS_16_23 0x0bd /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_PENDS_24_31 0x0be /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_PENDS_32_39 0x0bf /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_PENDS_40_47 0x0c0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_PENDS_48_55 0x0c1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_QMD_PENDS_56_63 0x0c2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID0_LIST_VLD0 0x0c3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID0_LIST_VLD1 0x0c4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID0_LIST_VLD2 0x0c5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID0_LIST_VLD3 0x0c6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID0_LIST_VLD4 0x0c7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID0_LIST_VLD5 0x0c8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID0_LIST_VLD6 0x0c9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID0_LIST_VLD7 0x0ca /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID1_LIST_VLD0 0x0cb /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID1_LIST_VLD1 0x0cc /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID1_LIST_VLD2 0x0cd /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID1_LIST_VLD3 0x0ce /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID1_LIST_VLD4 0x0cf /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID1_LIST_VLD5 0x0d0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID1_LIST_VLD6 0x0d1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID1_LIST_VLD7 0x0d2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID2_LIST_VLD0 0x0d3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID2_LIST_VLD1 0x0d4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID2_LIST_VLD2 0x0d5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID2_LIST_VLD3 0x0d6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID2_LIST_VLD4 0x0d7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID2_LIST_VLD5 0x0d8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID2_LIST_VLD6 0x0d9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID2_LIST_VLD7 0x0da /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID3_LIST_VLD0 0x0db /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID3_LIST_VLD1 0x0dc /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID3_LIST_VLD2 0x0dd /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID3_LIST_VLD3 0x0de /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID3_LIST_VLD4 0x0df /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID3_LIST_VLD5 0x0e0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID3_LIST_VLD6 0x0e1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID3_LIST_VLD7 0x0e2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID4_LIST_VLD0 0x0e3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID4_LIST_VLD1 0x0e4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID4_LIST_VLD2 0x0e5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID4_LIST_VLD3 0x0e6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID4_LIST_VLD4 0x0e7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID4_LIST_VLD5 0x0e8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID4_LIST_VLD6 0x0e9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID4_LIST_VLD7 0x0ea /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID5_LIST_VLD0 0x0eb /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID5_LIST_VLD1 0x0ec /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID5_LIST_VLD2 0x0ed /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID5_LIST_VLD3 0x0ee /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID5_LIST_VLD4 0x0ef /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID5_LIST_VLD5 0x0f0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID5_LIST_VLD6 0x0f1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID5_LIST_VLD7 0x0f2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID6_LIST_VLD0 0x0f3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID6_LIST_VLD1 0x0f4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID6_LIST_VLD2 0x0f5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID6_LIST_VLD3 0x0f6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID6_LIST_VLD4 0x0f7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID6_LIST_VLD5 0x0f8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID6_LIST_VLD6 0x0f9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID6_LIST_VLD7 0x0fa /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID7_LIST_VLD0 0x0fb /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID7_LIST_VLD1 0x0fc /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID7_LIST_VLD2 0x0fd /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID7_LIST_VLD3 0x0fe /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID7_LIST_VLD4 0x0ff /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID7_LIST_VLD5 0x100 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID7_LIST_VLD6 0x101 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID7_LIST_VLD7 0x102 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID8_LIST_VLD0 0x103 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID8_LIST_VLD1 0x104 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID8_LIST_VLD2 0x105 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID8_LIST_VLD3 0x106 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID8_LIST_VLD4 0x107 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID8_LIST_VLD5 0x108 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID8_LIST_VLD6 0x109 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID8_LIST_VLD7 0x10a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID9_LIST_VLD0 0x10b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID9_LIST_VLD1 0x10c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID9_LIST_VLD2 0x10d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID9_LIST_VLD3 0x10e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID9_LIST_VLD4 0x10f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID9_LIST_VLD5 0x110 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID9_LIST_VLD6 0x111 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID9_LIST_VLD7 0x112 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID10_LIST_VLD0 0x113 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID10_LIST_VLD1 0x114 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID10_LIST_VLD2 0x115 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID10_LIST_VLD3 0x116 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID10_LIST_VLD4 0x117 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID10_LIST_VLD5 0x118 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID10_LIST_VLD6 0x119 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID10_LIST_VLD7 0x11a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID11_LIST_VLD0 0x11b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID11_LIST_VLD1 0x11c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID11_LIST_VLD2 0x11d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID11_LIST_VLD3 0x11e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID11_LIST_VLD4 0x11f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID11_LIST_VLD5 0x120 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID11_LIST_VLD6 0x121 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID11_LIST_VLD7 0x122 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID12_LIST_VLD0 0x123 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID12_LIST_VLD1 0x124 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID12_LIST_VLD2 0x125 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID12_LIST_VLD3 0x126 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID12_LIST_VLD4 0x127 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID12_LIST_VLD5 0x128 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID12_LIST_VLD6 0x129 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID12_LIST_VLD7 0x12a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID13_LIST_VLD0 0x12b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID13_LIST_VLD1 0x12c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID13_LIST_VLD2 0x12d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID13_LIST_VLD3 0x12e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID13_LIST_VLD4 0x12f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID13_LIST_VLD5 0x130 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID13_LIST_VLD6 0x131 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID13_LIST_VLD7 0x132 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID14_LIST_VLD0 0x133 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID14_LIST_VLD1 0x134 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID14_LIST_VLD2 0x135 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID14_LIST_VLD3 0x136 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID14_LIST_VLD4 0x137 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID14_LIST_VLD5 0x138 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID14_LIST_VLD6 0x139 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID14_LIST_VLD7 0x13a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID15_LIST_VLD0 0x13b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID15_LIST_VLD1 0x13c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID15_LIST_VLD2 0x13d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID15_LIST_VLD3 0x13e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID15_LIST_VLD4 0x13f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID15_LIST_VLD5 0x140 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID15_LIST_VLD6 0x141 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID15_LIST_VLD7 0x142 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID16_LIST_VLD0 0x143 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID16_LIST_VLD1 0x144 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID16_LIST_VLD2 0x145 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID16_LIST_VLD3 0x146 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID16_LIST_VLD4 0x147 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID16_LIST_VLD5 0x148 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID16_LIST_VLD6 0x149 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID16_LIST_VLD7 0x14a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID17_LIST_VLD0 0x14b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID17_LIST_VLD1 0x14c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID17_LIST_VLD2 0x14d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID17_LIST_VLD3 0x14e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID17_LIST_VLD4 0x14f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID17_LIST_VLD5 0x150 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID17_LIST_VLD6 0x151 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID17_LIST_VLD7 0x152 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID18_LIST_VLD0 0x153 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID18_LIST_VLD1 0x154 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID18_LIST_VLD2 0x155 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID18_LIST_VLD3 0x156 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID18_LIST_VLD4 0x157 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID18_LIST_VLD5 0x158 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID18_LIST_VLD6 0x159 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID18_LIST_VLD7 0x15a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID19_LIST_VLD0 0x15b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID19_LIST_VLD1 0x15c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID19_LIST_VLD2 0x15d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID19_LIST_VLD3 0x15e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID19_LIST_VLD4 0x15f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID19_LIST_VLD5 0x160 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID19_LIST_VLD6 0x161 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID19_LIST_VLD7 0x162 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID20_LIST_VLD0 0x163 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID20_LIST_VLD1 0x164 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID20_LIST_VLD2 0x165 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID20_LIST_VLD3 0x166 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID20_LIST_VLD4 0x167 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID20_LIST_VLD5 0x168 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID20_LIST_VLD6 0x169 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID20_LIST_VLD7 0x16a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID21_LIST_VLD0 0x16b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID21_LIST_VLD1 0x16c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID21_LIST_VLD2 0x16d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID21_LIST_VLD3 0x16e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID21_LIST_VLD4 0x16f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID21_LIST_VLD5 0x170 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID21_LIST_VLD6 0x171 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID21_LIST_VLD7 0x172 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID22_LIST_VLD0 0x173 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID22_LIST_VLD1 0x174 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID22_LIST_VLD2 0x175 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID22_LIST_VLD3 0x176 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID22_LIST_VLD4 0x177 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID22_LIST_VLD5 0x178 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID22_LIST_VLD6 0x179 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID22_LIST_VLD7 0x17a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID23_LIST_VLD0 0x17b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID23_LIST_VLD1 0x17c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID23_LIST_VLD2 0x17d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID23_LIST_VLD3 0x17e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID23_LIST_VLD4 0x17f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID23_LIST_VLD5 0x180 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID23_LIST_VLD6 0x181 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID23_LIST_VLD7 0x182 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID24_LIST_VLD0 0x183 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID24_LIST_VLD1 0x184 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID24_LIST_VLD2 0x185 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID24_LIST_VLD3 0x186 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID24_LIST_VLD4 0x187 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID24_LIST_VLD5 0x188 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID24_LIST_VLD6 0x189 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID24_LIST_VLD7 0x18a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID25_LIST_VLD0 0x18b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID25_LIST_VLD1 0x18c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID25_LIST_VLD2 0x18d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID25_LIST_VLD3 0x18e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID25_LIST_VLD4 0x18f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID25_LIST_VLD5 0x190 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID25_LIST_VLD6 0x191 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID25_LIST_VLD7 0x192 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID26_LIST_VLD0 0x193 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID26_LIST_VLD1 0x194 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID26_LIST_VLD2 0x195 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID26_LIST_VLD3 0x196 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID26_LIST_VLD4 0x197 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID26_LIST_VLD5 0x198 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID26_LIST_VLD6 0x199 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID26_LIST_VLD7 0x19a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID27_LIST_VLD0 0x19b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID27_LIST_VLD1 0x19c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID27_LIST_VLD2 0x19d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID27_LIST_VLD3 0x19e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID27_LIST_VLD4 0x19f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID27_LIST_VLD5 0x1a0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID27_LIST_VLD6 0x1a1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID27_LIST_VLD7 0x1a2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID28_LIST_VLD0 0x1a3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID28_LIST_VLD1 0x1a4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID28_LIST_VLD2 0x1a5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID28_LIST_VLD3 0x1a6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID28_LIST_VLD4 0x1a7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID28_LIST_VLD5 0x1a8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID28_LIST_VLD6 0x1a9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID28_LIST_VLD7 0x1aa /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID29_LIST_VLD0 0x1ab /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID29_LIST_VLD1 0x1ac /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID29_LIST_VLD2 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID29_LIST_VLD3 0x1ae /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID29_LIST_VLD4 0x1af /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID29_LIST_VLD5 0x1b0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID29_LIST_VLD6 0x1b1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID29_LIST_VLD7 0x1b2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID30_LIST_VLD0 0x1b3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID30_LIST_VLD1 0x1b4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID30_LIST_VLD2 0x1b5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID30_LIST_VLD3 0x1b6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID30_LIST_VLD4 0x1b7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID30_LIST_VLD5 0x1b8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID30_LIST_VLD6 0x1b9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID30_LIST_VLD7 0x1ba /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID31_LIST_VLD0 0x1bb /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID31_LIST_VLD1 0x1bc /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID31_LIST_VLD2 0x1bd /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID31_LIST_VLD3 0x1be /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID31_LIST_VLD4 0x1bf /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID31_LIST_VLD5 0x1c0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID31_LIST_VLD6 0x1c1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID31_LIST_VLD7 0x1c2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID32_LIST_VLD0 0x1c3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID32_LIST_VLD1 0x1c4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID32_LIST_VLD2 0x1c5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID32_LIST_VLD3 0x1c6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID32_LIST_VLD4 0x1c7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID32_LIST_VLD5 0x1c8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID32_LIST_VLD6 0x1c9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID32_LIST_VLD7 0x1ca /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID33_LIST_VLD0 0x1cb /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID33_LIST_VLD1 0x1cc /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID33_LIST_VLD2 0x1cd /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID33_LIST_VLD3 0x1ce /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID33_LIST_VLD4 0x1cf /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID33_LIST_VLD5 0x1d0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID33_LIST_VLD6 0x1d1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID33_LIST_VLD7 0x1d2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID34_LIST_VLD0 0x1d3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID34_LIST_VLD1 0x1d4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID34_LIST_VLD2 0x1d5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID34_LIST_VLD3 0x1d6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID34_LIST_VLD4 0x1d7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID34_LIST_VLD5 0x1d8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID34_LIST_VLD6 0x1d9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID34_LIST_VLD7 0x1da /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID35_LIST_VLD0 0x1db /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID35_LIST_VLD1 0x1dc /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID35_LIST_VLD2 0x1dd /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID35_LIST_VLD3 0x1de /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID35_LIST_VLD4 0x1df /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID35_LIST_VLD5 0x1e0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID35_LIST_VLD6 0x1e1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID35_LIST_VLD7 0x1e2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID36_LIST_VLD0 0x1e3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID36_LIST_VLD1 0x1e4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID36_LIST_VLD2 0x1e5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID36_LIST_VLD3 0x1e6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID36_LIST_VLD4 0x1e7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID36_LIST_VLD5 0x1e8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID36_LIST_VLD6 0x1e9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID36_LIST_VLD7 0x1ea /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID37_LIST_VLD0 0x1eb /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID37_LIST_VLD1 0x1ec /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID37_LIST_VLD2 0x1ed /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID37_LIST_VLD3 0x1ee /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID37_LIST_VLD4 0x1ef /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID37_LIST_VLD5 0x1f0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID37_LIST_VLD6 0x1f1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID37_LIST_VLD7 0x1f2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID38_LIST_VLD0 0x1f3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID38_LIST_VLD1 0x1f4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID38_LIST_VLD2 0x1f5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID38_LIST_VLD3 0x1f6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID38_LIST_VLD4 0x1f7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID38_LIST_VLD5 0x1f8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID38_LIST_VLD6 0x1f9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID38_LIST_VLD7 0x1fa /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID39_LIST_VLD0 0x1fb /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID39_LIST_VLD1 0x1fc /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID39_LIST_VLD2 0x1fd /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID39_LIST_VLD3 0x1fe /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID39_LIST_VLD4 0x1ff /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID39_LIST_VLD5 0x200 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID39_LIST_VLD6 0x201 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID39_LIST_VLD7 0x202 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID40_LIST_VLD0 0x203 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID40_LIST_VLD1 0x204 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID40_LIST_VLD2 0x205 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID40_LIST_VLD3 0x206 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID40_LIST_VLD4 0x207 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID40_LIST_VLD5 0x208 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID40_LIST_VLD6 0x209 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID40_LIST_VLD7 0x20a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID41_LIST_VLD0 0x20b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID41_LIST_VLD1 0x20c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID41_LIST_VLD2 0x20d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID41_LIST_VLD3 0x20e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID41_LIST_VLD4 0x20f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID41_LIST_VLD5 0x210 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID41_LIST_VLD6 0x211 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID41_LIST_VLD7 0x212 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID42_LIST_VLD0 0x213 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID42_LIST_VLD1 0x214 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID42_LIST_VLD2 0x215 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID42_LIST_VLD3 0x216 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID42_LIST_VLD4 0x217 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID42_LIST_VLD5 0x218 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID42_LIST_VLD6 0x219 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID42_LIST_VLD7 0x21a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID43_LIST_VLD0 0x21b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID43_LIST_VLD1 0x21c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID43_LIST_VLD2 0x21d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID43_LIST_VLD3 0x21e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID43_LIST_VLD4 0x21f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID43_LIST_VLD5 0x220 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID43_LIST_VLD6 0x221 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID43_LIST_VLD7 0x222 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID44_LIST_VLD0 0x223 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID44_LIST_VLD1 0x224 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID44_LIST_VLD2 0x225 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID44_LIST_VLD3 0x226 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID44_LIST_VLD4 0x227 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID44_LIST_VLD5 0x228 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID44_LIST_VLD6 0x229 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID44_LIST_VLD7 0x22a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID45_LIST_VLD0 0x22b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID45_LIST_VLD1 0x22c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID45_LIST_VLD2 0x22d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID45_LIST_VLD3 0x22e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID45_LIST_VLD4 0x22f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID45_LIST_VLD5 0x230 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID45_LIST_VLD6 0x231 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID45_LIST_VLD7 0x232 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID46_LIST_VLD0 0x233 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID46_LIST_VLD1 0x234 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID46_LIST_VLD2 0x235 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID46_LIST_VLD3 0x236 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID46_LIST_VLD4 0x237 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID46_LIST_VLD5 0x238 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID46_LIST_VLD6 0x239 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID46_LIST_VLD7 0x23a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID47_LIST_VLD0 0x23b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID47_LIST_VLD1 0x23c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID47_LIST_VLD2 0x23d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID47_LIST_VLD3 0x23e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID47_LIST_VLD4 0x23f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID47_LIST_VLD5 0x240 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID47_LIST_VLD6 0x241 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID47_LIST_VLD7 0x242 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID48_LIST_VLD0 0x243 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID48_LIST_VLD1 0x244 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID48_LIST_VLD2 0x245 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID48_LIST_VLD3 0x246 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID48_LIST_VLD4 0x247 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID48_LIST_VLD5 0x248 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID48_LIST_VLD6 0x249 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID48_LIST_VLD7 0x24a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID49_LIST_VLD0 0x24b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID49_LIST_VLD1 0x24c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID49_LIST_VLD2 0x24d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID49_LIST_VLD3 0x24e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID49_LIST_VLD4 0x24f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID49_LIST_VLD5 0x250 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID49_LIST_VLD6 0x251 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID49_LIST_VLD7 0x252 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID50_LIST_VLD0 0x253 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID50_LIST_VLD1 0x254 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID50_LIST_VLD2 0x255 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID50_LIST_VLD3 0x256 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID50_LIST_VLD4 0x257 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID50_LIST_VLD5 0x258 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID50_LIST_VLD6 0x259 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID50_LIST_VLD7 0x25a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID51_LIST_VLD0 0x25b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID51_LIST_VLD1 0x25c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID51_LIST_VLD2 0x25d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID51_LIST_VLD3 0x25e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID51_LIST_VLD4 0x25f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID51_LIST_VLD5 0x260 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID51_LIST_VLD6 0x261 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID51_LIST_VLD7 0x262 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID52_LIST_VLD0 0x263 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID52_LIST_VLD1 0x264 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID52_LIST_VLD2 0x265 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID52_LIST_VLD3 0x266 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID52_LIST_VLD4 0x267 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID52_LIST_VLD5 0x268 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID52_LIST_VLD6 0x269 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID52_LIST_VLD7 0x26a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID53_LIST_VLD0 0x26b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID53_LIST_VLD1 0x26c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID53_LIST_VLD2 0x26d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID53_LIST_VLD3 0x26e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID53_LIST_VLD4 0x26f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID53_LIST_VLD5 0x270 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID53_LIST_VLD6 0x271 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID53_LIST_VLD7 0x272 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID54_LIST_VLD0 0x273 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID54_LIST_VLD1 0x274 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID54_LIST_VLD2 0x275 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID54_LIST_VLD3 0x276 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID54_LIST_VLD4 0x277 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID54_LIST_VLD5 0x278 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID54_LIST_VLD6 0x279 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID54_LIST_VLD7 0x27a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID55_LIST_VLD0 0x27b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID55_LIST_VLD1 0x27c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID55_LIST_VLD2 0x27d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID55_LIST_VLD3 0x27e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID55_LIST_VLD4 0x27f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID55_LIST_VLD5 0x280 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID55_LIST_VLD6 0x281 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID55_LIST_VLD7 0x282 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID56_LIST_VLD0 0x283 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID56_LIST_VLD1 0x284 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID56_LIST_VLD2 0x285 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID56_LIST_VLD3 0x286 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID56_LIST_VLD4 0x287 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID56_LIST_VLD5 0x288 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID56_LIST_VLD6 0x289 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID56_LIST_VLD7 0x28a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID57_LIST_VLD0 0x28b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID57_LIST_VLD1 0x28c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID57_LIST_VLD2 0x28d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID57_LIST_VLD3 0x28e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID57_LIST_VLD4 0x28f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID57_LIST_VLD5 0x290 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID57_LIST_VLD6 0x291 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID57_LIST_VLD7 0x292 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID58_LIST_VLD0 0x293 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID58_LIST_VLD1 0x294 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID58_LIST_VLD2 0x295 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID58_LIST_VLD3 0x296 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID58_LIST_VLD4 0x297 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID58_LIST_VLD5 0x298 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID58_LIST_VLD6 0x299 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID58_LIST_VLD7 0x29a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID59_LIST_VLD0 0x29b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID59_LIST_VLD1 0x29c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID59_LIST_VLD2 0x29d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID59_LIST_VLD3 0x29e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID59_LIST_VLD4 0x29f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID59_LIST_VLD5 0x2a0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID59_LIST_VLD6 0x2a1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID59_LIST_VLD7 0x2a2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID60_LIST_VLD0 0x2a3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID60_LIST_VLD1 0x2a4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID60_LIST_VLD2 0x2a5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID60_LIST_VLD3 0x2a6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID60_LIST_VLD4 0x2a7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID60_LIST_VLD5 0x2a8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID60_LIST_VLD6 0x2a9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID60_LIST_VLD7 0x2aa /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID61_LIST_VLD0 0x2ab /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID61_LIST_VLD1 0x2ac /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID61_LIST_VLD2 0x2ad /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID61_LIST_VLD3 0x2ae /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID61_LIST_VLD4 0x2af /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID61_LIST_VLD5 0x2b0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID61_LIST_VLD6 0x2b1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID61_LIST_VLD7 0x2b2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID62_LIST_VLD0 0x2b3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID62_LIST_VLD1 0x2b4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID62_LIST_VLD2 0x2b5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID62_LIST_VLD3 0x2b6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID62_LIST_VLD4 0x2b7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID62_LIST_VLD5 0x2b8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID62_LIST_VLD6 0x2b9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID62_LIST_VLD7 0x2ba /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID63_LIST_VLD0 0x2bb /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID63_LIST_VLD1 0x2bc /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID63_LIST_VLD2 0x2bd /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID63_LIST_VLD3 0x2be /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID63_LIST_VLD4 0x2bf /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID63_LIST_VLD5 0x2c0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID63_LIST_VLD6 0x2c1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID63_LIST_VLD7 0x2c2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID_IDLE_0_7 0x2c3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID_IDLE_8_15 0x2c4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID_IDLE_16_23 0x2c5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID_IDLE_24_31 0x2c6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID_IDLE_32_39 0x2c7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID_IDLE_40_47 0x2c8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID_IDLE_48_55 0x2c9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_VEID_IDLE_56_63 0x2ca /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_0 0x2cb /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_1 0x2cc /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_2 0x2cd /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_3 0x2ce /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_4 0x2cf /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_5 0x2d0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_6 0x2d1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_7 0x2d2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_8 0x2d3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_9 0x2d4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_10 0x2d5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_11 0x2d6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_12 0x2d7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_13 0x2d8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_14 0x2d9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_15 0x2da /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_16 0x2db /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_17 0x2dc /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_18 0x2dd /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_19 0x2de /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_20 0x2df /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_21 0x2e0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_22 0x2e1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_23 0x2e2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_24 0x2e3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_25 0x2e4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_26 0x2e5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_27 0x2e6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_28 0x2e7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_29 0x2e8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_30 0x2e9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_31 0x2ea /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_32 0x2eb /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_33 0x2ec /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_34 0x2ed /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_35 0x2ee /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_36 0x2ef /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_37 0x2f0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_38 0x2f1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_39 0x2f2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_40 0x2f3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_41 0x2f4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_42 0x2f5 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_43 0x2f6 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_44 0x2f7 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_45 0x2f8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_46 0x2f9 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_47 0x2fa /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_48 0x2fb /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_49 0x2fc /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_50 0x2fd /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_51 0x2fe /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_52 0x2ff /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_53 0x300 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_54 0x301 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_55 0x302 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_56 0x303 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_57 0x304 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_58 0x305 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_59 0x306 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_60 0x307 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_61 0x308 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_62 0x309 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TM_WATERMARK_COUNT_63 0x30a /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE8 0x30b /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE9 0x30c /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_L2DEMOTE 0x30d /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CPF_VPM 0x30e /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_TFL_VPM 0x30f /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SC_VPM 0x310 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_CACHE5 0x311 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE10 0x312 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE11 0x313 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_SFE12 0x314 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_PREFETCH_L15C 0x315 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_PREFETCH_L15C_VPM 0x316 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_SELECT_PREFETCH_L15C_1 0x317 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_PM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_PM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR 0x00407020 /* RWE4R */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK33_SCG_TYPE_GO_IDLE_RESTRICTION 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK33_SCG_TYPE_GO_IDLE_RESTRICTION_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK33_SCG_TYPE_GO_IDLE_RESTRICTION_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK34_CTA_STEER_REG_WARP 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK34_CTA_STEER_REG_WARP_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK34_CTA_STEER_REG_WARP_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK28_PCAS_WITH_SEM 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK28_PCAS_WITH_SEM_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK28_PCAS_WITH_SEM_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK27_VSPAN_OVERFLOW 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK27_VSPAN_OVERFLOW_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK27_VSPAN_OVERFLOW_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK32_VSPAN_NONEMPTY_PREEMPT 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK32_VSPAN_NONEMPTY_PREEMPT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK32_VSPAN_NONEMPTY_PREEMPT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK25_THROTTLED_IS_RESTRICTED 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK25_THROTTLED_IS_RESTRICTED_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK25_THROTTLED_IS_RESTRICTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK24_CTA_RESUME 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK24_CTA_RESUME_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK24_CTA_RESUME_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK23_CONSTANT_BUFFER_SIZE 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK23_CONSTANT_BUFFER_SIZE_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK23_CONSTANT_BUFFER_SIZE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK36_DEPENDENCE_COUNTER_UNDERFLOW 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK36_DEPENDENCE_COUNTER_UNDERFLOW_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK36_DEPENDENCE_COUNTER_UNDERFLOW_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK02_LOCAL_MEMORY_LOW_SIZE 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK02_LOCAL_MEMORY_LOW_SIZE_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK02_LOCAL_MEMORY_LOW_SIZE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK03_LOCAL_MEMORY_HIGH_SIZE 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK03_LOCAL_MEMORY_HIGH_SIZE_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK03_LOCAL_MEMORY_HIGH_SIZE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK04_LOCAL_MEMORY_CRS_SIZE 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK04_LOCAL_MEMORY_CRS_SIZE_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK04_LOCAL_MEMORY_CRS_SIZE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK05_LOCAL_MEMORY_TOTAL_SIZE 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK05_LOCAL_MEMORY_TOTAL_SIZE_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK05_LOCAL_MEMORY_TOTAL_SIZE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK06_REGISTER_COUNT 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK06_REGISTER_COUNT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK06_REGISTER_COUNT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK07_OUTER_PUT 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK07_OUTER_PUT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK07_OUTER_PUT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK08_INNER_PUT 15:15 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK08_INNER_PUT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK08_INNER_PUT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK09_INNER_GET 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK09_INNER_GET_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK09_INNER_GET_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK10_OUTER_GET 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK10_OUTER_GET_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK10_OUTER_GET_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK11_TOTAL_THREADS 18:18 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK11_TOTAL_THREADS_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK11_TOTAL_THREADS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK35_IGNORE_VEID_CACHE_LINE 19:19 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK35_IGNORE_VEID_CACHE_LINE_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK35_IGNORE_VEID_CACHE_LINE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK13_PROGRAM_OFFSET 20:20 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK13_PROGRAM_OFFSET_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK13_PROGRAM_OFFSET_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK14_SHARED_MEMORY_SIZE 21:21 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK14_SHARED_MEMORY_SIZE_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK14_SHARED_MEMORY_SIZE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK15_UNUSED 22:22 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK15_UNUSED_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK15_UNUSED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK16_CTA_THREAD_DIMENSION_ZERO 23:23 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK16_CTA_THREAD_DIMENSION_ZERO_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK16_CTA_THREAD_DIMENSION_ZERO_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK17_MEMORY_WINDOW_OVERLAP 24:24 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK17_MEMORY_WINDOW_OVERLAP_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK17_MEMORY_WINDOW_OVERLAP_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK18_L1_CONFIG_TOO_SMALL 25:25 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK18_L1_CONFIG_TOO_SMALL_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK18_L1_CONFIG_TOO_SMALL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION 26:26 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK20_GET_PUT_TOO_LARGE 27:27 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK20_GET_PUT_TOO_LARGE_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK20_GET_PUT_TOO_LARGE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK21_CIRCULAR_QUEUE_SIZE 28:28 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK21_CIRCULAR_QUEUE_SIZE_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK21_CIRCULAR_QUEUE_SIZE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK22_INVALIDATE_ACTIVE_QMD 29:29 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK22_INVALIDATE_ACTIVE_QMD_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK22_INVALIDATE_ACTIVE_QMD_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_NONACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECKXX_MISC 31:31 /* R-EVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECKXX_MISC_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECKXX_MISC_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN 0x00407024 /* RWE4R */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK33_SCG_TYPE_GO_IDLE_RESTRICTION 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK33_SCG_TYPE_GO_IDLE_RESTRICTION_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK33_SCG_TYPE_GO_IDLE_RESTRICTION_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK34_CTA_STEER_REG_WARP 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK34_CTA_STEER_REG_WARP_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK34_CTA_STEER_REG_WARP_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK28_PCAS_WITH_SEM 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK28_PCAS_WITH_SEM_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK28_PCAS_WITH_SEM_TRUE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK27_VSPAN_OVERFLOW 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK27_VSPAN_OVERFLOW_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK27_VSPAN_OVERFLOW_TRUE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK32_VSPAN_NONEMPTY_PREEMPT 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK32_VSPAN_NONEMPTY_PREEMPT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK32_VSPAN_NONEMPTY_PREEMPT_TRUE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK25_THROTTLED_IS_RESTRICTED 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK25_THROTTLED_IS_RESTRICTED_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK25_THROTTLED_IS_RESTRICTED_TRUE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK24_CTA_RESUME 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK24_CTA_RESUME_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK24_CTA_RESUME_TRUE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK23_CONSTANT_BUFFER_SIZE 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK23_CONSTANT_BUFFER_SIZE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK23_CONSTANT_BUFFER_SIZE_TRUE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK36_DEPENDENCE_COUNTER_UNDERFLOW 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK36_DEPENDENCE_COUNTER_UNDERFLOW_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK36_DEPENDENCE_COUNTER_UNDERFLOW_TRUE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK02_LOCAL_MEMORY_LOW_SIZE 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK02_LOCAL_MEMORY_LOW_SIZE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK02_LOCAL_MEMORY_LOW_SIZE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK03_LOCAL_MEMORY_HIGH_SIZE 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK03_LOCAL_MEMORY_HIGH_SIZE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK03_LOCAL_MEMORY_HIGH_SIZE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK04_LOCAL_MEMORY_CRS_SIZE 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK04_LOCAL_MEMORY_CRS_SIZE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK04_LOCAL_MEMORY_CRS_SIZE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK05_LOCAL_MEMORY_TOTAL_SIZE 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK05_LOCAL_MEMORY_TOTAL_SIZE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK05_LOCAL_MEMORY_TOTAL_SIZE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK06_REGISTER_COUNT 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK06_REGISTER_COUNT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK06_REGISTER_COUNT_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK07_OUTER_PUT 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK07_OUTER_PUT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK07_OUTER_PUT_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK08_INNER_PUT 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK08_INNER_PUT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK08_INNER_PUT_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK09_INNER_GET 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK09_INNER_GET_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK09_INNER_GET_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK10_OUTER_GET 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK10_OUTER_GET_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK10_OUTER_GET_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK11_TOTAL_THREADS 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK11_TOTAL_THREADS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK11_TOTAL_THREADS_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK35_IGNORE_VEID_CACHE_LINE 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK35_IGNORE_VEID_CACHE_LINE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK35_IGNORE_VEID_CACHE_LINE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK13_PROGRAM_OFFSET 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK13_PROGRAM_OFFSET_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK13_PROGRAM_OFFSET_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK14_SHARED_MEMORY_SIZE 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK14_SHARED_MEMORY_SIZE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK14_SHARED_MEMORY_SIZE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK15_UNUSED 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK15_UNUSED_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK15_UNUSED_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK16_CTA_THREAD_DIMENSION_ZERO 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK16_CTA_THREAD_DIMENSION_ZERO_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK16_CTA_THREAD_DIMENSION_ZERO_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK17_MEMORY_WINDOW_OVERLAP 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK17_MEMORY_WINDOW_OVERLAP_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK17_MEMORY_WINDOW_OVERLAP_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK18_L1_CONFIG_TOO_SMALL 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK18_L1_CONFIG_TOO_SMALL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK18_L1_CONFIG_TOO_SMALL_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK19_CTA_REGISTER_CONSUMPTION 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK20_GET_PUT_TOO_LARGE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK20_GET_PUT_TOO_LARGE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK20_GET_PUT_TOO_LARGE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK21_CIRCULAR_QUEUE_SIZE 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK21_CIRCULAR_QUEUE_SIZE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK21_CIRCULAR_QUEUE_SIZE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK22_INVALIDATE_ACTIVE_QMD 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK22_INVALIDATE_ACTIVE_QMD_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK22_INVALIDATE_ACTIVE_QMD_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECKXX_MISC 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECKXX_MISC_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECKXX_MISC_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_1 0x00407028 /* R--4R */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_1_VEID 7:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_1_VEID_0 0x00 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_1_CWD_SLOT 15:8 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_1_CWD_SLOT_0 0x00 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_2 0x0040702c /* R--4R */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_2_QMD_ID 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_2_QMD_ID_0 0x00000000 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_3 0x00407030 /* R--4R */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_3_FROM 23:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_3_FROM_0 0x000000 /* R---V */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_3_DELTA 31:24 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_HWW_INFO_3_DELTA_0 0x00 /* R---V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK 0x00407044 /* RWE4R */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sked_cya" /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_PL3_ENABLED_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000 /* RW--V */ #define NV_PGRAPH_PRI_SKED_MISC 0x00407034 /* RWE4R */ #define NV_PGRAPH_PRI_SKED_MISC__PRIV_LEVEL_MASK 0x00407044 /* */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_WRITE_BACK_SKED_CACHE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_WRITE_BACK_SKED_CACHE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_WRITE_BACK_SKED_CACHE_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_INV_SKED_CACHES_L15C 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_INV_SKED_CACHES_L15C_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_INV_SKED_CACHES_L15C_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_DRAIN_PUTPTR_ON_FAULT 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_DRAIN_PUTPTR_ON_FAULT_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_DRAIN_PUTPTR_ON_FAULT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_DIRTY_SKED_CACHE_EVICT_INVALIDATES_L15 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_DIRTY_SKED_CACHE_EVICT_INVALIDATES_L15_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_DIRTY_SKED_CACHE_EVICT_INVALIDATES_L15_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_RSVD 15:5 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_MISC_CYA_RSVD_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CPF_POOL 0x00407038 /* RWE4R */ #define NV_PGRAPH_PRI_SKED_CPF_POOL_FE_MIN_RESERVE 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CPF_POOL_FE_MIN_RESERVE_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CPF_POOL_FB_MIN_RESERVE 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CPF_POOL_FB_MIN_RESERVE_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CPF_POOL_TM_MIN_RESERVE 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CPF_POOL_TM_MIN_RESERVE_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CPF_POOL_FE_PRIORITY_WATERMARK 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CPF_POOL_FE_PRIORITY_WATERMARK_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CPF_POOL_FB_PRIORITY_WATERMARK 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CPF_POOL_FB_PRIORITY_WATERMARK_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CPF_POOL_TM_PRIORITY_WATERMARK 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CPF_POOL_TM_PRIORITY_WATERMARK_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_CONFIG 0x0040703c /* RWE4R */ #define NV_PGRAPH_PRI_SKED_CONFIG_CYA_QMD_L2DEMOTE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_CONFIG_CYA_QMD_L2DEMOTE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_CONFIG_CYA_QMD_L2DEMOTE_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1 0x00407040 /* RWE4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_1__PRIV_LEVEL_MASK 0x00407044 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_TM_LAUNCH_THROTTLE_LIMIT 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_TM_LAUNCH_THROTTLE_LIMIT_INIT 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_TM_LAUNCH_THROTTLE_LIMIT_MAX 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_CTA_STEER_AUTO_CORRECT 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_CTA_STEER_AUTO_CORRECT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_COPY_PCAS_CLEARS_RESUME_BITS 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_COPY_PCAS_CLEARS_RESUME_BITS_NO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_COPY_PCAS_CLEARS_RESUME_BITS_YES 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_SCG_TYPE_GO_IDLE_FULL 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_SCG_TYPE_GO_IDLE_FULL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_AUTO_INVALIDATE_QMD 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_AUTO_INVALIDATE_QMD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_AUTO_INVALIDATE_QMD_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_FE_CACHE_PF_SLOT_LIMIT 10:8 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_FE_CACHE_PF_SLOT_LIMIT_MAX 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_ENABLE_CWD_SLOT_COUNT 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_ENABLE_CWD_SLOT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_TFL_PREFETCH_SLOT_LIMIT 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_TFL_PREFETCH_SLOT_LIMIT_MAX 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_PCAS_CACHE_PF_SLOT_LIMIT 18:16 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_PCAS_CACHE_PF_SLOT_LIMIT_MAX 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_TM_CACHE_PF_SLOT_LIMIT 22:20 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_TM_CACHE_PF_SLOT_LIMIT_MAX 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_NUM_CACHE_LINES_LIMIT 31:23 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_NUM_CACHE_LINES_LIMIT_288 0x120 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_NUM_CACHE_LINES_LIMIT_256 0x100 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_NUM_CACHE_LINES_LIMIT_192 0x0c0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_NUM_CACHE_LINES_LIMIT_128 0x080 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_NUM_CACHE_LINES_LIMIT_64 0x040 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_NUM_CACHE_LINES_LIMIT_44 0x02c /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_1_NUM_CACHE_LINES_LIMIT_MAX 0x120 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_3 0x00407048 /* RWE4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_3__PRIV_LEVEL_MASK 0x00407044 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_3_VSPAN_RAM_LIMIT 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_3_VSPAN_RAM_LIMIT_MAX 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_3_IQ2M_L2_EVICT_POLICY 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_3_IQ2M_L2_EVICT_POLICY_WRITE_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_3_IQ2M_L2_EVICT_POLICY_WRITE_NORMAL 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_3_IQ2M_L2_EVICT_POLICY_WRITE_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_3_NUM_L15_CACHE_LINES_LIMIT 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_3_NUM_L15_CACHE_LINES_LIMIT_MAX 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_3_VSPAN_INFO_SELECT 24:16 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_3_VSPAN_INFO_SELECT_ALL_VEID 0x100 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_NUM_VSPAN_ENTRIES 0x00407050 /* R--4R */ #define NV_PGRAPH_PRI_SKED_NUM_VSPAN_ENTRIES_V 30:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_ACTIVITY 0x00407054 /* R--4R */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_SFE 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_SFE_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_PP 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_PP_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_TM 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_TM_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_TFL 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_TFL_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_CACHE 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_CACHE_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_FBI_IF 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_FBI_IF_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_FBI_CORE 20:18 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_FBI_CORE_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_IQ 23:21 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_IQ_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_SKED_FE 31:29 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_ACTIVITY_SKED_FE_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK 0x00407058 /* RWE4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sked_debug" /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_PL3_ENABLED_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0 0x00407060 /* RW-4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_SLOT 7:0 /* RWXVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_SLOT_0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_STATUS 11:8 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_STATUS_FREE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_STATUS_PREFETCH_ALLOCATED 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_STATUS_LAUNCH_PENDING 0x2 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_STATUS_ACTIVE 0x3 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_STATUS_EMPTY 0x4 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_STATUS_DEALLOC_PENDING 0x5 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_STATUS_DEALLOC_PENDING_INVALIDATE 0x6 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_STATUS_DEALLOC_PENDING_INVALIDATE_PREFETCH 0x7 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_STATUS_DEALLOC_REQUESTED_INVALIDATE 0x8 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_STATUS_DISABLED 0x9 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_DEP_STATUS 15:12 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_DEP_STATUS_NONE_OR_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_DEP_STATUS_PENDING_TASK_INCOMPLETE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_DEP_STATUS_PENDING_TASK_COMPLETE 0x2 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_AGE 23:16 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_AGE_OLDEST 0x00 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_AGE_NEWEST 0x1f /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_0_VEID 31:24 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_1 0x00407064 /* R--4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_1__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_1_QMD_ID 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_2 0x00407068 /* R--4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_2__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_2_INNER_PUT 23:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_2_EMPTY_AT_DEALLOC 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CWD_TABLE_2_INNER_PUT_PENDING 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0 0x00407070 /* RW-4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_LINE 15:0 /* RWXVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_LINE_0 0x0000 /* RWX-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_DATA_SEL 19:16 /* RWXVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_DATA_SEL_0 0x0 /* RWX-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_DATA_SEL_1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_DATA_SEL_2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_DATA_SEL_3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_DATA_SEL_4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_STATUS 27:24 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_STATUS_ALLOCATED 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_STATUS_PENDING_FILL 0x2 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_STATUS_DISABLED 0x3 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_ERR 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_ERR_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_0_ERR_ERROR 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_1 0x00407074 /* R--4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_1__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_1_QMD_ID 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_2 0x00407078 /* R--4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_2__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_2_DATA 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_3 0x0040707c /* R--4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_3__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_CACHE_3_VEID 7:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_0 0x00407080 /* RW-4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_0__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_0_GROUP 15:0 /* RWXVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_0_GROUP_0 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_0_VEID 23:16 /* RWXVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_0_VEID_0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_0_VALID 24:24 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_0_VALID_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_0_VALID_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_0_ERR 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_0_ERR_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_0_ERR_ERROR 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_1 0x00407084 /* R--4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_1__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_1_HEAD 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_2 0x00407088 /* R--4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_2__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_TASKTABLE_2_TAIL 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0 0x00407090 /* RW-4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_LINE_ADDRESS 7:0 /* RWXVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_LINE_ADDRESS_0 0x00 /* RWX-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_DATA_ADDRESS 15:8 /* RWXVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_DATA_ADDRESS_0 0x00 /* RWX-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_SEL 16:16 /* RWXVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_SEL_LINE 0x0 /* RWX-V */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_SEL_DATA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_LINE_STATUS 23:20 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_LINE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_LINE_STATUS_ALLOCATED 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_LINE_STATUS_PENDING_FILL 0x2 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_LINE_STATUS_DISABLED 0x3 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_LINE_WRITE_THROUGH_STATUS 24:24 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_LINE_WRITE_THROUGH_STATUS_PENDING 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_LINE_WRITE_THROUGH_STATUS_NOT_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_ERR 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_ERR_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_0_ERR_ERROR 0x1 /* R---V */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_1 0x00407094 /* R--4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_1__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_1_DATA 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_2 0x00407098 /* R--4R */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_2__PRIV_LEVEL_MASK 0x00407058 /* */ #define NV_PGRAPH_PRI_SKED_DEBUG_L15_CACHE_2_DATA 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK(i) (0x004070a0+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK__SIZE_1 16 /* */ #define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX0 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX0_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX1 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX1_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX2 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX2_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX3 31:24 /* RWIVF */ #define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX3_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI 0x00400000 /* RW--L */ #define NV_PGRAPH_PRI_GPC0 0x00500000 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_ATOM_SIZE 4096 #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_ATOM_SIZE_LG2 0xC #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK 0x00502280 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK 0x00502284 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK 0x00502288 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK 0x0050228c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK 0x00502290 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK 0x00502294 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK 0x005020e8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK 0x00502298 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x8 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK 0x0050229c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK 0x005023d0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK 0x005023f0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK 0x005023f4 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK 0x005023f8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK 0x005023fc /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(i) (0x0050218c+(i)*16) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(i) (0x005022b0+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK 0x00502190 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK 0x00502194 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK 0x00502198 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK 0x0050219c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK 0x005021a0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK 0x005021a4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK 0x005021a8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK 0x005021b0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK 0x005021bc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK 0x005021e0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK 0x005021e4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK 0x005021e8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK 0x005021ec /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK 0x005021f0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK 0x005021f4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK 0x005021f8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK 0x005021fc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK 0x00502220 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK 0x00502224 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK 0x0050222c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET 0x00502000 /* -W-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_GPTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_WDTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_MTHD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_HALT 4:4 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_HALT_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXTERR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_SWGEN0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_SWGEN1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT 15:8 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ1 8:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ1_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ2 9:9 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ2_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ3 10:10 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ3_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ4 11:11 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ4_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ5 12:12 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ5_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ6 13:13 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ6_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ7 14:14 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ7_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ8 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ8_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_DMA 16:16 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSSET_DMA_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR 0x00502004 /* -W-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_GPTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_WDTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_MTHD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_HALT_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXTERR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_SWGEN0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_SWGEN1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT 15:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCLR_DMA_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT 0x00502008 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_GPTMR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_GPTMR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_WDTMR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_WDTMR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_MTHD_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_MTHD_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_CTXSW_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_CTXSW_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_HALT_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_HALT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXTERR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXTERR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_SWGEN0_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_SWGEN0_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_SWGEN1_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_SWGEN1_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT 15:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_DMA_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSTAT_DMA_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE 0x0050200c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE__PRIV_LEVEL_MASK 0x00502290 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_GPTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_MTHD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_MTHD_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_MTHD_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_CTXSW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_HALT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_HALT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_HALT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXTERR_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_INIT 0xfc /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ1 8:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ2 9:9 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ3 10:10 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ4 11:11 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ5 12:12 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ6 13:13 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ7 14:14 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ8 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_DMA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_DMA_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMODE_LVL_DMA_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK 0x005020e0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK__PRIV_LEVEL_MASK 0x005021a4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_GPTMR_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_GPTMR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_WDTMR_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_WDTMR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_MTHD_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_MTHD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_CTXSW_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_CTXSW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_HALT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_HALT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXTERR_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXTERR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_ENABLE 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_DISABLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ1 8:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ2 9:9 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ3 10:10 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ4 11:11 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ4_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ4_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ5 12:12 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ5_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ5_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ6 13:13 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ6_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ6_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ7 14:14 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ7_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ7_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ8 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ8_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ8_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_DMA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQSCMASK_DMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET 0x00502010 /* -W-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET__PRIV_LEVEL_MASK 0x00502290 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_GPTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_WDTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_MTHD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_HALT 4:4 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_HALT_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXTERR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_SWGEN0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_SWGEN1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT 15:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_DMA 16:16 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMSET_DMA_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR 0x00502014 /* -W-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR__PRIV_LEVEL_MASK 0x00502290 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_GPTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_WDTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_MTHD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_HALT_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXTERR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_SWGEN0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_SWGEN1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT 15:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMCLR_DMA_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK 0x00502018 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_GPTMR_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_GPTMR_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_WDTMR_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_WDTMR_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_MTHD_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_MTHD_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_CTXSW_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_CTXSW_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_HALT 4:4 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_HALT_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_HALT_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXTERR_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXTERR_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_SWGEN0_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_SWGEN0_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_SWGEN1_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_SWGEN1_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT 15:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_DMA 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_DMA_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQMASK_DMA_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST 0x0050201c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST__PRIV_LEVEL_MASK 0x00502290 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_GPTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_GPTMR_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_WDTMR_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_MTHD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_MTHD_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_MTHD_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_CTXSW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_CTXSW_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_HALT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_HALT_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_HALT_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXTERR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXTERR_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT 15:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_MTHD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_HALT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT 31:24 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST2 0x0050203c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST2__PRIV_LEVEL_MASK 0x00502290 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST2_HOST_DMA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST2_HOST_DMA_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST2_HOST_DMA_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST2_TARGET_DMA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRINT 0x00502020 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRINT__PRIV_LEVEL_MASK 0x005021a0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRVAL 0x00502024 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRVAL__PRIV_LEVEL_MASK 0x005021a0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRCTL 0x00502028 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRCTL__PRIV_LEVEL_MASK 0x005021a0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRCTL_GPTMREN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER0 0x0050202c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER0__PRIV_LEVEL_MASK 0x005021bc /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER0_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER1 0x00502030 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER1__PRIV_LEVEL_MASK 0x005021bc /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PTIMER1_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRVAL 0x00502034 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRVAL__PRIV_LEVEL_MASK 0x0050229c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRCTL 0x00502038 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRCTL__PRIV_LEVEL_MASK 0x0050229c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRCTL_WDTMREN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDDATA 0x00502064 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDDATA__PRIV_LEVEL_MASK 0x00502294 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDID 0x00502068 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDID__PRIV_LEVEL_MASK 0x00502294 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDID_ID 11:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDID_PRIV 15:15 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDID_PRIV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDID_PRIV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDID_WPEND 16:16 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDID_WPEND_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDID_WPEND_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDWDAT 0x0050206c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDWDAT__PRIV_LEVEL_MASK 0x00502294 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCOUNT 0x00502070 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK 0x00502294 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDCOUNT_COUNT_INIT 0x0000 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDPOP 0x00502074 /* -W-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDPOP__PRIV_LEVEL_MASK 0x00502294 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDPOP_POP 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDPOP_POP_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDPOP_POP_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDRAMSZ 0x00502078 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK 0x00502294 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX 0x00502050 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX__PRIV_LEVEL_MASK 0x00502294 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX_CTXVLD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX_CTXVLD_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX_CTXVLD_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX_CTXTGT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CURCTX_CTXPTR_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX 0x00502054 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX__PRIV_LEVEL_MASK 0x00502294 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX_CTXVLD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX_CTXVLD_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX_CTXVLD_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX_CTXTGT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_NXTCTX_CTXPTR_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CTXACK 0x00502058 /* -W-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CTXACK__PRIV_LEVEL_MASK 0x00502294 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CTXACK_SAVE_ACK_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CTXACK_SAVE_ACK_CLEAR 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CTXACK_REST_ACK_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CTXACK_REST_ACK_CLEAR 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MAILBOX0 0x00502040 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MAILBOX1 0x00502044 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN 0x00502048 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN__PRIV_LEVEL_MASK 0x00502294 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_CTXEN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_CTXEN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_CTXEN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_MTHDEN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_MTHDEN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_MTHDEN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_PRIV_POSTWR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_CTXSW_NACK_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_CTXSW_NACK_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE 0x0050204c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE__PRIV_LEVEL_MASK 0x005021e0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_FHSTATE 0x0050205c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_FHSTATE__PRIV_LEVEL_MASK 0x005021e4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_FHSTATE_STALL_REQ_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_FHSTATE_STALL_REQ_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE 0x00502060 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE__PRIV_LEVEL_MASK 0x005023d0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRIVSTATE_PRIV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SFTRESET 0x0050207c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SFTRESET__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SFTRESET_EXT 0:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SFTRESET_EXT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SFTRESET_EXT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL 0x005020a4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_STALLREQ_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_STALLREQ_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_STALLACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ENGCTL_STALLACK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ADDR 0x005020ac /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ADDR__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ADDR_LSB 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ADDR_LSB_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ADDR_MSB 11:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ADDR_MSB_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ADDR_EXT 11:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL 0x0050210c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL_REQUIRE_CTX_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFBASE 0x00502110 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFBASE__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFMOFFS 0x00502114 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFMOFFS_OFFS_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD 0x00502118 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_FULL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_FULL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_IDLE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_IDLE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_IMEM_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_IMEM_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_WRITE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_WRITE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_NOTIFY_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_NOTIFY_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SIZE_4B 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SIZE_8B 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SIZE_16B 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SIZE_32B 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SIZE_64B 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SIZE_128B 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SIZE_256B 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_ERROR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_ERROR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFFBOFFS 0x0050211c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB 0x00502120 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP 0x00502124 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_LOW 0x005022c0 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_HIGH 0x005022c4 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_LOW 0x005022c8 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_HIGH 0x005022cc /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_LOW 0x005022d0 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_HIGH 0x005022d4 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_LOW 0x005022d8 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_HIGH 0x005022dc /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL 0x005022e0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_ERR_TAG_HIGH 0x005022e4 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_ERR_TAG_LOW 0x005022e8 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK 0x00502190 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC(i) (0x00502180+(i)*16) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_OFFS 7:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_OFFS_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_BLK 23:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_BLK_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_AINCW 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_AINCW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_AINCW_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_AINCW_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_AINCR 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_AINCR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_AINCR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_AINCR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_SECURE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_SECURE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_SEC_LOCK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMC_SEC_LOCK_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMD(i) (0x00502184+(i)*16) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMD__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMD__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMD_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMT(i) (0x00502188+(i)*16) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMT__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMT__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMT_TAG 15:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMT_FAULT_CORRECTED 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMT_FAULT_CORRECTED_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMT_FAULT_UNCORRECTED 17:17 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEMT_FAULT_UNCORRECTED_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC(i) (0x005021c0+(i)*8) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_ADDRESS_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_OFFS 7:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_OFFS_INIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_BLK 23:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_BLK_INIT 0x0000 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_AINCW 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_AINCW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_AINCW_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_AINCW_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_AINCR 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_AINCR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_AINCR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_AINCR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_SETTAG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_SETTAG_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_SETTAG_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_SETLVL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_SETLVL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_SETLVL_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_VA 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_VA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_VA_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_VA_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_MISS 29:29 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_MISS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_MISS_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_MULTIHIT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_MULTIHIT_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_LVLERR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMC_LVLERR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMD(i) (0x005021c4+(i)*8) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMD__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMD__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMD_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMT(i) (0x00502210+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMT__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMT__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMT_TAG 15:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMT_FAULTED 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEMT_FAULTED_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEML(i) (0x005022a0+(i)*4) /* -W-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEML__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEML__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEML_LVL 2:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_DUMMY 0x00502258 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK 0x00502284 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_DUMMY 0x005021b4 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK 0x00502280 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x00502300+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK 0x005023f0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x00502310+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK 0x005023f4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x00502320+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x005023f8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x00502330+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK 0x005023fc /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRGNVER 0x005023d4 /* R-I4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRGNVER_MAJOR_DEFT 0x2 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRGNVER_MINOR_DEFT 0x0000 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PRGNVER_BUGFIX_DEFT 0x0000 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG 0x00502108 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1 0x0050212c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_INIT 0x6 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_1_0 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_2_0 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_3_0 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_4_0 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_5_0 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_6_0 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_7_0 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x2 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_IMEM_PORTS_INIT 0x1 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_DMEM_PORTS_INIT 0x4 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_TAG_WIDTH_INIT 0x10 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x1 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2 0x005020f4 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_SHA 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_SHA_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_SHA_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_BMEM 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_BMEM_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_BMEM_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_PKCBOOT_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_PKCBOOT_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_DBGMODE_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_DBGMODE_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_KMEM 4:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_KMEM_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_KMEM_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_VHR 7:7 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_VHR_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_VHR_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_HS 8:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_HS_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_HS_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_SECUREBUS_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_SECUREBUS_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_RISCV 10:10 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_RISCV_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_RISCV_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG3 0x00502278 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CGCTL 0x005020a0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CGCTL_CG_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2 0x00502134 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2__PRIV_LEVEL_MASK 0x005021e8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG 17:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_ENABLED 0x00000 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_DISABLED 0x1ffff /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG__PROD 0x000a0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FBIF_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG2_SLCG_FBIF_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL 0x00502240 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL__PRIV_LEVEL_MASK 0x00502298 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_LSMODE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_LSMODE_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_LSMODE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_HSMODE 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_HSMODE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_HSMODE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_LSMODE_LEVEL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_UCODE_LEVEL 5:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_UCODE_LEVEL_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_AUTH_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL_AUTH_EN_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL1 0x00502250 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL1__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL1_CSBLVL_MASK_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SCTL1_EXTLVL_MASK_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL 0x005020e4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL__PRIV_LEVEL_MASK 0x005020e8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_TRACEPC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_TRACEPC_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_SP_MIN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_HSCTL_SP_MIN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_ERB 0x005022ec /* -W-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_ERB_DATA 31:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_ERB_DATA_CORRECTED_ERR 0xeafe0c00 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_ERB_DATA_UNCORRECTED_ERR 0xeafe1cff /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX 0x005022f0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_DATA 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRADDR 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRADDR_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE 31:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_PF 0xf0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_PF 0xf1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_SCP 0xf2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_SCP 0xf3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_SCP 0xf3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_DMA 0xf4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_DMA 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_DMA 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_PMB 0xf6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_PMB 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_PMB 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_LDST 0xf8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_PMB 0xf9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_DMA 0xfa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_SCP 0xfb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_CORRECTED_SHA 0xfc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_UNCORRECTED_SHA 0xfd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_CORRECTED_RISCV 0xfe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_UNCORRECTED_RISCV 0xff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IROM 0xe0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IROM 0xe1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL 0x005022f4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL__PRIV_LEVEL_MASK 0x005021b0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_FUSE_OPT_ECC_EN 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_FUSE_OPT_ECC_EN_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_IMEM_ECC_DIS 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_IMEM_ECC_DIS_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_CTRL_IMEM_ECC_DIS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_ERR_ADDR 0x005022f8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_ERR_ADDR_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_ERR_ADDR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_ERR_ADDR_HI 0x005022fc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_ERR_ADDR_HI_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SAFETY_ERR_ADDR_HI_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_OS 0x00502080 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_OS_VERSION 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RM 0x00502084 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RM_CONFIG 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SOFT_PM 0x00502088 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SOFT_PM__PRIV_LEVEL_MASK 0x005021ec /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SOFT_PM_TRIGGER_START_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SOFT_PM_TRIGGER_END_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SOFT_PM_PROBE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SOFT_MODE 0x0050208c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SOFT_MODE__PRIV_LEVEL_MASK 0x005021ec /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SOFT_MODE_PROBE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM 0x005020a8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM__PRIV_LEVEL_MASK 0x005021ec /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_CODE 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_IPND 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_SB 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL 19:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_RREQ 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_WREQ 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_RREQ_SC 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_WREQ_SC 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT_SC 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY_SC 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1 0x00502090 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1__PRIV_LEVEL_MASK 0x00502294 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x0040 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1_CTXSW_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUGINFO 0x00502094 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN 0x00502270 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN__PRIV_LEVEL_MASK 0x005021f0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SP_MIN_VALUE_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI 0x005020d0 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI__PRIV_LEVEL_MASK 0x005021f4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXPC 19:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_TRAP0 0x00 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_TRAP1 0x01 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_TRAP2 0x02 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_TRAP3 0x03 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_ILL_INS 0x08 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_INV_INS 0x09 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_MISS_INS 0x0a /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0b /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0d /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0f /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x10 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x11 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x12 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x13 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_FAULT_INS 0x14 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI2 0x005020bc /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI2__PRIV_LEVEL_MASK 0x005021f4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR 0x005020d4 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR__PRIV_LEVEL_MASK 0x005021f8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_SIGPASS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_SVEC_SPR_SIGPASS_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL 0x00502100 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL__PRIV_LEVEL_MASK 0x00502288 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_IINVAL_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_IINVAL_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_STARTCPU_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_STARTCPU_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_SRESET_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_SRESET_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_HRESET_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_HRESET_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_HALTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_HALTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_STOPPED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_STOPPED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_ALIAS_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_ALIAS_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_ALIAS_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_ALIAS 0x00502130 /* -W-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_STACKCFG 0x00502138 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_STACKCFG__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_STACKCFG_BOTTOM_INIT 0x000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_STACKCFG_SPEXC_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_STACKCFG_SPEXC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_STACKCFG_SPEXC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC 0x00502104 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC__PRIV_LEVEL_MASK 0x00502194 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL 0x00502254 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL__PRIV_LEVEL_MASK 0x005021a8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_VAL 9:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_VAL_INIT 0x000 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_TRACE_MODE_FULL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_TRACE_MODE_STACK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_CYA 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_CYA_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DBGCTL_CYA_ENABLE 0x8afe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1 0x00502098 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1__PRIV_LEVEL_MASK 0x005021fc /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT1_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2 0x0050209c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2__PRIV_LEVEL_MASK 0x005021fc /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT2_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3 0x005020b0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3__PRIV_LEVEL_MASK 0x005021fc /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT3_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4 0x005020b4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4__PRIV_LEVEL_MASK 0x005021fc /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT4_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5 0x005020b8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5__PRIV_LEVEL_MASK 0x005021fc /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IBRKPT5_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD 0x00502200 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD__PRIV_LEVEL_MASK 0x00502220 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_STOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_RUN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_JRUN 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_RUNB 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_JRUNB 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_STEP 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_JSTEP 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_EMASK 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_RREG 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_WREG 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_RDM 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_WDM 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_RCM 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_WCM 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_RSTAT 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_OPC_SBU 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_SZ_B 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_SZ_HW 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_SZ_W 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_REG15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_IV0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_IV1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_EV 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_SP 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_PC 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_IMB 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_DMB 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_CSW 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_CCR 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_SEC 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_CTX 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_EXCI 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_SEC1 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_IMB1 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_DMB1 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_RSTAT0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_RSTAT1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_RSTAT2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_RSTAT3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_RSTAT4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_RSTAT5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_WB0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_WB1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_WB2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_IDX_WB3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_FAULTED 13:13 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_FAULTED_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_FAULTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_FAULTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_ERROR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_ERROR_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_RDVLD_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_RDVLD_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_PARM 31:16 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK 31:16 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_ADDR 0x00502204 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_ADDR__PRIV_LEVEL_MASK 0x00502220 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_WDATA 0x00502208 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_WDATA__PRIV_LEVEL_MASK 0x00502220 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA 0x0050220c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA__PRIV_LEVEL_MASK 0x00502220 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 0x2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 0x2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 0x2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 0x2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 0x2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 0x3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 0x4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 0x5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 0x6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 0x7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 0x2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 0x3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 0x2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0 0x005020d8 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0__PRIV_LEVEL_MASK 0x00502224 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_VALID 28:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3 0x005020dc /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEIDX 0x00502148 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEIDX__PRIV_LEVEL_MASK 0x0050219c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEIDX_CNT_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEIDX_IDX_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEPC 0x0050214c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEPC__PRIV_LEVEL_MASK 0x0050219c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEPC_PC 23:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEINFO 0x0050217c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEINFO__PRIV_LEVEL_MASK 0x0050219c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL 0x00502140 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_CMD 26:24 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_CMD_NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_CMD_IMINV 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_CMD_IMBLK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_CMD_IMTAG 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_DEBUG 0x0050215c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_DEBUG_CMD_NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMSTAT 0x00502144 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMSTAT__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMSTAT_VAL 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLRNG0 0x00502150 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLRNG0_TAG_LO 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLRNG0_TAG_LO_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLRNG0_TAG_HI 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLRNG0_TAG_HI_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLRNG1 0x00502154 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLRNG1_TAG_LO 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLRNG1_TAG_LO_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLRNG1_TAG_HI 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLRNG1_TAG_HI_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLCTL 0x00502158 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLCTL__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_IMFILLCTL_NBLOCKS_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMCTL 0x00502260 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMCTL__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMCTL_CMD 26:24 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMCTL_CMD_NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMCTL_CMD_DMINV 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMCTL_CMD_DMBLK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMCTL_CMD_DMTAG 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMCTL_CMD_DMCLEAN 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMCTL_CMD_DMLVL 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMSTAT 0x00502264 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMSTAT__PRIV_LEVEL_MASK 0x0050228c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMSTAT_VAL 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMVACTL 0x00502268 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMVACTL__PRIV_LEVEL_MASK 0x00502198 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_DMVACTL_BOUND_INIT 0x00000014 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERRSTAT 0x00502244 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK 0x0050222c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERRSTAT_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERRSTAT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERRSTAT_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERRSTAT_VALID_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERRSTAT_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERRSTAT_VALID_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_ADDR 0x0050224c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK 0x0050222c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_INFO 0x00502248 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK 0x0050222c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_DATA 0x00502500 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_DATA_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_DATA_V_ELPG_LIST 0x00000001 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_DATA_V_GPCRG_LIST 0x00000002 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_DATA_A 0x0050250c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_DATA_A_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH 0x00502504 /* -W-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_PRIV 31:31 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR 11:0 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_NOP 0x000 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_WFI_SAVE 0x001 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_WFI_RESTORE 0x002 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_BIND_POINTER 0x003 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_BIND_POINTER_ONLY 0x060 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_HALT_PIPELINE 0x004 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_HALT_PIPELINE_NEW 0x007 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_UNHALT_PIPELINE 0x005 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_CONTEXT_RESET 0x006 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 0x010 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_PREPARE_FOR_INITIALIZATION 0x011 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_WFI_SAVE_ONLY 0x008 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 0x009 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_WFI_SAVE_RESTORE 0x00a /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_WFI 0x00b /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_NOCHSW_MODE 0x00c /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_ALLOW_SWDX_DIRECT_CTXSW_SKIP 0x00d /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_DISABLE_RAMCHAIN_SCRUB 0x00e /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_DISABLE_SWDX_DIRECT_CTXSW_SCRUB 0x00f /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_RESTORE_GOLDEN 0x015 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 0x016 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x025 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_DISCOVER_PREEMPTION_IMAGE_SIZE 0x01a /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_INIT_MME_SHADOW_RAM 0x02a /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_INIT_BUNDLE_DECODERS 0x02b /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_LO 0x02c /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_HI 0x02d /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SET_SMC_LTS_MASK_INDEX 0x02e /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_ASSIGN_SMC_LTS_MASK 0x02f /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x030 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x031 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x032 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SAVE_REGLIST 0x033 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_RESTORE_REGLIST 0x034 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_UCODE_RECONFIG 0x035 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_CHECK_GPCCS_INIT_COMPLETE 0x036 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_STOP_CTXSW 0x038 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_START_CTXSW 0x039 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_CONFIGURE_INTERRUPT_COMPLETION_OPTION 0x03a /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_DISABLE_ACCESS_COUNTER 0x03c /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_INSTANCE 0x03d /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_VIRTUAL_ADDRESS_LO 0x03e /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_VIRTUAL_ADDRESS_HI 0x03f /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_METHOD_INIT 0x040 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_BUNDLE_INIT_COMPUTE 0x041 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_BUNDLE_INIT_2D 0x042 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_BUNDLE_INIT_3D 0x043 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_BUNDLE_INIT_MEM2MEM 0x044 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_SIZE 0x054 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_LO 0x055 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_LO 0x056 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_CALCULATE 0x057 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_HI 0x058 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_HI 0x059 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_INJECT_STACK_CANARY_ERROR 0x070 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SHUTDOWN_UCODE 0x012 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_CONTEXT_ADDRESS 0x013 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_CONTEXT_ADDRESS_HI 0x01e /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_PRIV_OFFSET 0x014 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_GFXP_CONTEXT_ADDRESS 0x01c /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_GFXP_CONTEXT_ADDRESS_HI 0x01f /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_GFXP_RC_OFFSET 0x01d /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_ZCULL_CONTEXT_ADDRESS 0x017 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_ZCULL_CONTEXT_ADDRESS_HI 0x022 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_ZCULL_PRIV_OFFSET 0x018 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_ZCULL_MODE 0x019 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_CBC_CLEAR_ACTIVE 0x01b /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_FMODEL_TESTS 0x020 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x021 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SET_GFID 0x024 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_PM_CONTEXT_ADDRESS 0x026 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_PM_CONTEXT_ADDRESS_HI 0x023 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_PM_PRIV_OFFSET 0x027 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SEND_PM_MODE 0x028 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_TEST_MODE 0x029 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_CONTROL_ZBC_TABLES_SAVE 0x061 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SAVE_SM_PERF_COUNTERS_START 0x062 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SAVE_SM_PERF_COUNTERS_END 0x063 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_RESTORE_SM_PERF_COUNTERS 0x064 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SMPC_GLOBAL_MODE_START 0x069 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_SMPC_GLOBAL_MODE_STOP 0x06a /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_RESTORE_HWPM_CONTROL_REGS 0x065 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_PERFORM_PRE_SAVE_TASKS 0x06b /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_ADR_PERFORM_PRE_RESTORE_TASKS 0x06c /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A 0x00502508 /* -W-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_PRIV 31:31 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR 11:0 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_NOP 0x000 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_WFI_SAVE 0x001 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_WFI_RESTORE 0x002 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_BIND_POINTER 0x003 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_BIND_POINTER_ONLY 0x060 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_HALT_PIPELINE 0x004 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_HALT_PIPELINE_NEW 0x007 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_UNHALT_PIPELINE 0x005 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_CONTEXT_RESET 0x006 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_IMAGE_SIZE 0x010 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_PREPARE_FOR_INITIALIZATION 0x011 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_WFI_SAVE_ONLY 0x008 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_WFI_GOLDEN_SAVE 0x009 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_WFI_SAVE_RESTORE 0x00a /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_WFI 0x00b /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_NOCHSW_MODE 0x00c /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_ALLOW_SWDX_DIRECT_CTXSW_SKIP 0x00d /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_DISABLE_RAMCHAIN_SCRUB 0x00e /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_DISABLE_SWDX_DIRECT_CTXSW_SCRUB 0x00f /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_RESTORE_GOLDEN 0x015 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_ZCULL_IMAGE_SIZE 0x016 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_PM_IMAGE_SIZE 0x025 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_PREEMPTION_IMAGE_SIZE 0x01a /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_INIT_MME_SHADOW_RAM 0x02a /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_INIT_BUNDLE_DECODERS 0x02b /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_LO 0x02c /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_HI 0x02d /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SET_SMC_LTS_MASK_INDEX 0x02e /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_ASSIGN_SMC_LTS_MASK 0x02f /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x030 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SET_REGLIST_BIND_INSTANCE 0x031 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x032 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SAVE_REGLIST 0x033 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_RESTORE_REGLIST 0x034 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_UCODE_RECONFIG 0x035 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_CHECK_GPCCS_INIT_COMPLETE 0x036 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_STOP_CTXSW 0x038 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_START_CTXSW 0x039 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_CONFIGURE_INTERRUPT_COMPLETION_OPTION 0x03a /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_DISABLE_ACCESS_COUNTER 0x03c /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_SIZE 0x054 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_LO 0x055 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_LO 0x056 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_CALCULATE 0x057 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_HI 0x058 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_HI 0x059 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_READ_PHYS_MEM 0x067 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_ENABLE_PHYS_MEM_READS 0x068 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SHUTDOWN_UCODE 0x012 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_CONTEXT_ADDRESS 0x013 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_CONTEXT_ADDRESS_HI 0x01e /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_PRIV_OFFSET 0x014 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_GFXP_CONTEXT_ADDRESS 0x01c /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_GFXP_CONTEXT_ADDRESS_HI 0x01f /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_GFXP_RC_OFFSET 0x01d /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_ZCULL_CONTEXT_ADDRESS 0x017 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_ZCULL_CONTEXT_ADDRESS_HI 0x022 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_ZCULL_PRIV_OFFSET 0x018 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_ZCULL_MODE 0x019 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_CBC_CLEAR_ACTIVE 0x01b /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_FMODEL_TESTS 0x020 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SET_WATCHDOG_TIMEOUT 0x021 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SET_GFID 0x024 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_PM_CONTEXT_ADDRESS 0x026 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_PM_CONTEXT_ADDRESS_HI 0x023 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_PM_PRIV_OFFSET 0x027 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SEND_PM_MODE 0x028 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_TEST_MODE 0x029 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_PCIE_TRAINING 0x050 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_CONTROL_ZBC_TABLES_SAVE 0x061 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SAVE_SM_PERF_COUNTERS_START 0x062 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_SAVE_SM_PERF_COUNTERS_END 0x063 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_RESTORE_SM_PERF_COUNTERS 0x064 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_RESTORE_HWPM_CONTROL_REGS 0x065 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_PERFORM_PRE_SAVE_TASKS 0x06b /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_PERFORM_PRE_RESTORE_TASKS 0x06c /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_METHOD_PUSH_A_ADR_INJECT_STACK_CANARY_ERROR 0x070 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_DATA 0x005028b8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_DATA_FIELD 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG 0x005028bc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_NONE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_ENGINE_RESET 0x01 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CONTEXT_RESET 0x02 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_INSTANCE_BIND 0x03 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_SAVE_ENGINE_REGS 0x06 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_RESTORE_ENGINE_REGS 0x07 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GOLDEN_SAVE 0x08 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_SAVE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_SAVE 0x10 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_SAVE 0x11 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_SAVE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_SAVE_ONLY 0x0a /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_SAVE_ONLY 0x05 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_SAVE_ONLY 0x12 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_SAVE_ONLY 0x13 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_RESTORE 0x0f /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_RESTORE 0x14 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_RESTORE 0x15 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_RESTORE 0x0b /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GOLDEN_RESTORE 0x0c /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_PATCH_BUFFER_END 0x0d /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_END 0x04 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FORCE_NONIDLE 0x00502424 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FORCE_NONIDLE_OVERRIDE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FORCE_NONIDLE_OVERRIDE_ACTIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FORCE_NONIDLE_OVERRIDE_INACTIVE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x00502420 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE_FALCON 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE_FORCED 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE_RC_LANES 2:2 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE_PRIV_SEQUENCER 3:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE_GPCCS 15:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x00502c04 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0_HWW 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0_CTXSW_HALT 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0_STOP_SM 2:2 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x00502400 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_CONSTANT_0 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_LOCAL_PRIV_ERROR 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_RC_LANES 2:2 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_RC_LANES_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_RC_LANES_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_CONTEXT_RESET 3:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_CONTEXT_RESET_ACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_CONTEXT_RESET_DISABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL 4:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL_BUSY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL_IDLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_SEQUENCER 5:5 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_SEQUENCER_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_SEQUENCER_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_READ 6:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_READ_DONE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_READ_NOT_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_WRACK 7:7 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_WRACK_DONE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_WRACK_NOT_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_COMP0 8:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_COMP0_DONE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_COMP0_NOT_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_COMP1 9:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_COMP1_DONE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_COMP1_NOT_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_DFD_TRIGGER 10:10 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_DFD_TRIGGER_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_DFD_TRIGGER_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_WATCHDOG_TRIGGER 11:11 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_WATCHDOG_TRIGGER_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_WATCHDOG_TRIGGER_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_ARB_BUSY 12:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_ARB_NACK 13:13 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_ARB_HALTED 14:14 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_ARB_FLUSH_WHEN_BUSY 15:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_CTXSW_CHECKSUM_MISMATCH 16:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL 28:28 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL_VIOLATION 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_ERROR 29:29 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP 30:30 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_WRITE_DROPPED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_UCODE_TRAP 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_UCODE_TRAP_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1_PRIV_UCODE_TRAP_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG 0x00502404 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SEL0_BIT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SEL0_BIT_V0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SEL0_STATUS_REG 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_1 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SEL1_BIT 12:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SEL1_BIT_V0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SEL1_STATUS_REG 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_1 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_COMBINATION 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_COMBINATION_OR 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_COMBINATION_AND 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SENSE 18:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SENSE_RISING_EDGE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SENSE_FALLING_EDGE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SENSE_LEVEL_1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_CFG_SENSE_LEVEL_0 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_WATCHDOG 0x00502430 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_WATCHDOG_COUNT 29:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_WATCHDOG_COUNT_V 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_WATCHDOG_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_WATCHDOG_ENABLE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_WATCHDOG_ENABLE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK 0x00502434 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_2_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_3_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_3_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_4 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_4_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_4_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_5_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_5_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_6_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_6_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_7_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_INT_ACK_7_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL 0x00502614 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_GPC_HALT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_GPC_HALT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_GPC_HALT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_HALT_SEQUENCER 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_HALT_SEQUENCER_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_HALT_SEQUENCER_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_ZCULL_RT_RESET 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_ZCULL_RT_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_ZCULL_RT_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ENGINE_RESET_CTL 0x00502610 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ENGINE_RESET_CTL_GPC_ENGINE_RESET 0:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ENGINE_RESET_CTL_GPC_ENGINE_RESET_ENABLED 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ENGINE_RESET_CTL_GPC_ENGINE_RESET_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_CTL_SIGS 0x0050288c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_CTL_SIGS_CTXSW_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_CTL_SIGS_CTXSW_FREEZE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_CTL_SIGS_CTXSW_FREEZE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX(i) (0x00502800+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX__SIZE_1 18 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_NONE 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_PASS 0x00000001 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_FAIL 0x00000002 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_BIND_POINTER_PASS 0x00000010 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_BIND_POINTER_FAIL 0x00000021 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_MAGIC 0x12345678 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_WAIT_FOR_MODS 0x0000000f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_STOP_WAIT_FOR_MODS 0x0000000e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SYNC_POINT_1 0x00000005 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SYNC_POINT_2 0x00000006 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SYNC_POINT_3 0x00000007 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_INIT_FAILED 0x00000008 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_INVALID_METHOD 0x00000009 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_METHOD_QUEUE_OVERFLOW 0x00000010 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_INVALID_FIRMWARE_METHOD_PARAMETER 0x00000011 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SIDEBAND_METHOD_QUEUE_OVERFLOW 0x00000012 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_FIRMWARE_METHOD_QUEUE_OVERFLOW 0x00000013 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_BECS_RC_NON_ZERO 0x00000014 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_BAD_CTXSW_IMAGE 0x00000015 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SECURE_FAIL_FECS 0x00000016 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SECURE_FAIL_GPCCS 0x00000017 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SECURE_FAIL_FECS_AND_GPCCS 0x00000018 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_GFXP_WITH_VPR_CONTEXT 0x00000019 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_PRI_SEQ_ERROR 0x00000020 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_CTXSW_CHECKSUM_MISMATCH 0x00000021 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_FALCON_CSB_ERROR 0x00000022 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_PATCH_BUFFER_ACCESS_VIOLATION 0x00000023 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_FALCON_STACK_CANARY_CHECK_FAILED 0x00000024 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SCRUB_STEP_CHECK_1_FAILED 0x00000025 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SCRUB_STEP_CHECK_2_FAILED 0x00000026 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_INDEX_OOB 0x00000027 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_POINTER_OVERFLOW 0x00000028 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_OFFSET_OVERFLOW 0x00000029 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_FULL 0x00000030 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_INVALID_ARBITER_COMMANDS 0x00000031 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_NUM_GPC_MISMATCH 0x00000032 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_NUM_TPC_MISMATCH 0x00000033 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_GFXP_IN_SMC_MODE 0x00000034 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_RESTORE_SMC_IN_LEGACY 0x00000035 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_RESTORE_LEGACY_IN_SMC 0x00000036 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SMC_LTS_MASK_INDEX_OUT_OF_BOUNDS 0x00000037 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SYS_RAMCHAIN_IMAGE_SIZE_MISMATCH 0x00000038 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_GPC_RAMCHAIN_IMAGE_SIZE_MISMATCH 0x00000039 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SYS_PRI_IMAGE_SIZE_MISMATCH 0x00000040 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_GPC_PRI_IMAGE_SIZE_MISMATCH 0x00000041 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_MAX_LTS_PER_LTC 0x00000042 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_NUM_PPC_MISMATCH 0x00000043 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_TRIVIAL_ACK_WITHOUT_NOCHSW 0x00000044 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_SECOND_RESTORE_WITH_NOCHSW 0x00000045 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_INVALID_PRIV_ACCESS_MAP_CONFIG 0x00000046 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_LTC_COUNT_OVERFLOW 0x00000047 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_REV_ID_CHECK_FAILED 0x00000048 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_CHIP_ID_CHECK_FAILED 0x00000049 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_ILLEGAL_FALCON_LEVEL 0x00000050 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_PRIV_SEC_NOT_ENABLED 0x00000051 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_FIRMWARE_MTHD_PRIV_ACCESS_VIOLATION 0x00000002 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_FIRMWARE_MTHD_VERIF_VIOLATION 0x00000003 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_OOB 0x00000001 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_NOT_IN_WHITELIST 0x00000002 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_ALLOW_NONE 0x00000003 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_KILL 0x00000004 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_OOB 0x00000005 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_NOT_IN_WHITELIST 0x00000006 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_SET(i) (0x00502848+(i)*4) /* -W-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_SET__SIZE_1 6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_SET_VALUE 31:0 /* -W-VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR(i) (0x00502860+(i)*4) /* -W-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR__SIZE_1 6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR_VALUE 31:0 /* -W-VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX(i) (0x005028c0+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX__SIZE_1 6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_VALUE 31:0 /* -W-VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK 0x00502878 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_LEVEL3_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_LOCAL_FALCON_ENABLED 0x80040 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1(i) (0x005028d8+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1__PRIV_LEVEL_MASK 0x00502878 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_VALUE 31:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK 0x0050287c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_LEVEL3_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2(i) (0x005028e4+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2__PRIV_LEVEL_MASK 0x0050287c /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_VALUE 31:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK 0x005028fc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3(i) (0x005028f0+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3__PRIV_LEVEL_MASK 0x005028fc /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_VALUE 31:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK 0x00502428 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_SOURCE_FALCON_FECS_GPCCS_ENABLED 0x80174 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_FS_CONFIG 0x0050240c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_FS_CONFIG__PRIV_LEVEL_MASK 0x00502428 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_FS_CONFIG_EN 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_FS_CONFIG_EN_NONE 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_ACTIVE_CONFIG 0x00502410 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_ACTIVE_CONFIG__PRIV_LEVEL_MASK 0x00502428 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_ACTIVE_CONFIG_EN 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_ACTIVE_CONFIG_EN_NONE 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_FINISHED 0x00502414 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_FINISHED__PRIV_LEVEL_MASK 0x00502428 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_FINISHED_BITS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_FINISHED_BITS_RESET 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE(i) (0x00502418+(i)*4) /* -W-4A */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE__PRIV_LEVEL_MASK 0x00502428 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT0 0:0 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT0_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT1 1:1 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT1_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT2 2:2 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT2_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT3 3:3 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT3_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT4 4:4 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT4_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT5 5:5 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT5_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT6 6:6 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT6_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT7 7:7 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT7_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT8 8:8 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT8_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT9 9:9 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT9_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT9_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT10 10:10 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT10_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT10_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT11 11:11 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT11_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT11_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT12 12:12 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT12_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT12_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT13 13:13 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT13_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT13_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT14 14:14 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT14_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT14_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT15 15:15 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT15_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT15_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT16 16:16 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT16_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT16_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT17 17:17 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT17_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT17_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT18 18:18 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT18_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT18_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT19 19:19 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT19_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT19_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT20 20:20 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT20_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT20_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT21 21:21 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT21_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT21_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT22 22:22 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT22_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT22_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT23 23:23 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT23_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT23_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT24 24:24 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT24_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT24_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT25 25:25 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT25_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT25_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT26 26:26 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT26_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT26_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT27 27:27 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT27_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT27_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT28 28:28 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT28_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT28_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT29 29:29 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT29_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT29_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT30 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT30_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT30_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT31 31:31 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT31_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_COMP_SET_DONE_BIT31_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FS 0x00502604 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FS_NUM_AVAILABLE_GPCS 4:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FS_NUM_AVAILABLE_FBPS 20:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FS_NUM_AVAILABLE_LTCS 28:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x00502608 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ROPS 25:21 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_INFO 0x00502618 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_INFO_GLOBAL_GPC_ID 4:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_INFO_SMC_LOCAL_GPC_ID 12:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_INFO_UGPU_ID 13:13 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_SMC_CONFIGURATION 0x0050261c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_SMC_CONFIGURATION_MODE 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_SMC_CONFIGURATION_MODE_LEGACY_MODE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_SMC_CONFIGURATION_MODE_SMC_MODE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_SMC_CONFIGURATION_SMC_ENGINE_ID 20:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x00502620 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ_4K 0x10 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ_6K 0x18 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ_8K 0x20 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ_12K 0x30 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_DMEM_SZ 15:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_DMEM_SZ_2K 0x08 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_DMEM_SZ_4K 0x10 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_DMEM_SZ_8K 0x20 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS 0x00502cfc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC0_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC0_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC1_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC1_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC2_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC2_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC3_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC3_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC4 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC4_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC4_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC5_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC5_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC6_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC6_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC7_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_TPCCS_STATUS_TPC7_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x00502880 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN 0x00502884 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE0_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE0_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE1_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE1_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE2_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE2_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE3_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE3_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE4 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE4_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE4_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE5_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE5_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE6_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE6_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE7_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE7_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE8 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE8_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE8_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE9 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE9_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE9_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE10 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE10_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE10_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE11 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE11_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE11_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE12 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE12_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE12_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE13 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE13_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE13_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE14 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE14_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE14_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE15 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE15_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE15_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE16 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE16_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE16_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE17 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE17_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RUN_LANE17_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS 0x00502888 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE0 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE0_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE0_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE1 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE1_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE1_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE2 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE2_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE2_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE3 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE3_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE3_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE4 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE4_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE4_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE5 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE5_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE5_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE6 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE6_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE6_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE7 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE7_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE7_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE8 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE8_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE8_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE9 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE9_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE9_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE10 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE10_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE10_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE11 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE11_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE11_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE12 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE12_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE12_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE13 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE13_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE13_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE14 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE14_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE14_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE15 15:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE15_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE15_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE16 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE16_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE16_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE17 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE17_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_STATUS_LANE17_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SCRUB 0x00502640 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SCRUB_STATUS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SCRUB_STATUS_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SCRUB_STATUS_CLEAN 0xffffffff /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_SIMULATION_OPTIONS 0x00502644 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_SIMULATION_OPTIONS_MODEL 1:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_SIMULATION_OPTIONS_MODEL_GATES 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_SIMULATION_OPTIONS_MODEL_RTL 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_SIMULATION_OPTIONS_MODEL_FMODEL 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS 0x00502678 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_RESET 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_RESET_TASK 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_STATUS_RESET_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT 0x0050267c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT 0x00502680 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_ADDRESS 0x00502684 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_ADDRESS_INDEX 22:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_ADDRESS_ROW_ADDRESS 19:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_ADDRESS_SOURCE_RAM 22:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_ADDRESS_SOURCE_RAM_FALCON_IMEM 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_ADDRESS_SOURCE_RAM_FALCON_DMEM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK 0x00502688 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CONTROL 0x0050268c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CONTROL__PRIV_LEVEL_MASK 0x00502688 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR 0:0 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR 1:1 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_INFO 0x00502690 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_INFO_ADDRESS 25:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_INFO_ADDRESS_V 0x0000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE 30:29 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE_INVALID 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE_READ 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE_WRITE_ACK 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE_WRITE_NO_ACK 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_INFO_SOURCE 31:31 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_INFO_SOURCE_PRI_SEQ 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_INFO_SOURCE_FALCON_CSB 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_CODE 0x00502694 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_CODE_VALUE 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_CODE_VALUE_V 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_SUBID_INFO 0x005026a0 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_SUBID_INFO_TRANSACTION_SUBID 7:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_SUBID_INFO_TRANSACTION_SUBID_V 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_SUBID_INFO_RETURN_SUBID 15:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PRI_ERROR_SUBID_INFO_RETURN_SUBID_V 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK 0x00502950 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_IFF_GPCCS_FECS_GSP_SEC2_FUSE1 0x8007c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CONTROL 0x00502904 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CONTROL__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CONTROL_COMPRESSION 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CONTROL_COMPRESSION_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CONTROL_COMPRESSION_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CONTROL_BLOAT_BUDGET 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CONTROL_BLOAT_BUDGET_0 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CONTROL_COMPRESSION_SETTINGS 27:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CONTROL_COMPRESSION_SETTINGS__0 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SAVE_OFFSET 0x00502908 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SAVE_OFFSET__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SAVE_OFFSET_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SAVE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RESTORE_OFFSET 0x0050290c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RESTORE_OFFSET__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RESTORE_OFFSET_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RESTORE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CURRENT_OFFSET 0x0050292c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CURRENT_OFFSET_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CURRENT_OFFSET_V_0 0x00000000 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CURRENT_SUBOFFSET 0x00502930 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CURRENT_SUBOFFSET_V 5:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CURRENT_SUBOFFSET_V_0 0x00 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE 0x00502910 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_PREFETCH_OFFSET 0x00502914 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_PREFETCH_OFFSET__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_PREFETCH_OFFSET_V 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_PREFETCH_OFFSET_V_10 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SAVED_WORDS 0x00502934 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SAVED_WORDS__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SAVED_WORDS_V 23:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SAVED_WORDS_V_0 0x000000 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RESTORE_WORDS 0x00502938 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RESTORE_WORDS__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RESTORE_WORDS_V 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_RESTORE_WORDS_V_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_DATA 0x00502918 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_DATA__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_DATA_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_DATA_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_LOC 0x0050291c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_LOC__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_LOC_RAMID 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_LOC_RAMID_V 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_LOC_OFFSET 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_LOC_OFFSET_V 0x000f /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_CFG 0x00502920 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_CFG__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_CFG_DELAY 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_CFG_DELAY_V 0x41 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_CFG_CREDITS 21:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_CFG_CREDITS_V 0x3f /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_CFG_AUTOSEEK 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_CFG_AUTOSEEK_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_CFG_AUTOSEEK_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_RCCLASS 0x0050293c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_RCCLASS__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_RCCLASS_V 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_RCCLASS_V_3 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_RCCLASS_V_WFI 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_RCCLASS_V_GFXP 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS 0x00502924 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD 4:0 /* RW-VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_IDLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SEEK 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_DISCOVER_LENGTH 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SAVE 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RESTORE 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_LOAD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_READ_POP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_WRITE_PUSH 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_ENABLE 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_DISABLE 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_ENABLE 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_DISABLE 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_ENABLE 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_DISABLE 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_OVERRIDE 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_FLUSH 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SUSPEND 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_CURRENT 9:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_CURRENT_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_STATUS_CURRENT_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC 0x00502928 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_IDLE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_SEEK 0x01 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_DISCOVER_LENGTH 0x02 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_SAVE 0x03 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_RESTORE 0x04 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_LOAD 0x05 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_READ_POP 0x06 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_WRITE_PUSH 0x07 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_RAMID_ENABLE 0x08 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_RAMID_DISABLE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_ENABLE 0x0a /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_DISABLE 0x0b /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_CHAIN_ENABLE 0x0c /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_CHAIN_DISABLE 0x0d /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_OVERRIDE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_FLUSH 0x0f /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_SUSPEND 0x10 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CMD_EXEC_CMD_SCRUB 0x11 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_COMPUTED_CHECKSUM 0x00502944 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_COMPUTED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SAVED_CHECKSUM 0x00502948 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SAVED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CHECKSUM 0x0050294c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CHECKSUM__PRIV_LEVEL_MASK 0x00502950 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CHECKSUM_CTRL_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CHECKSUM_CTRL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CHECKSUM_STATUS_MATCH 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_CHECKSUM_STATUS_MISMATCH 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK 0x00502760 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pri_sequencer_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_pri_sequencer_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_JTAG_IFF_SEC2_ENABLED_FUSE1 0x80144 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_SAVE_OFFSET 0x00502700 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_SAVE_OFFSET__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_SAVE_OFFSET_V 31:0 /* RW-VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_SAVE_OFFSET_V_0 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_RESTORE_OFFSET 0x00502704 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_RESTORE_OFFSET__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_RESTORE_OFFSET_V 31:0 /* RW-VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_RESTORE_OFFSET_V_0 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_SAVE_COUNT 0x00502748 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_SAVE_COUNT_V 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_SAVE_COUNT_V_0 0x0000 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_RESTORE_COUNT 0x0050274c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_RESTORE_COUNT__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_RESTORE_COUNT_V 15:0 /* RW-VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_RESTORE_COUNT_V_0 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_CURRENT_OFFSET 0x00502708 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_CURRENT_OFFSET_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_CURRENT_SUBOFFSET 0x0050270c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_CURRENT_SUBOFFSET_V 5:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_REGISTER_BASE_ADDR 0x00502710 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_REGISTER_BASE_ADDR__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_REGISTER_BASE_ADDR_V 25:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_REGISTER_BASE_ADDR_V_0 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_REGISTER_BASE_ADDR 0x00502724 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_REGISTER_BASE_ADDR__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_REGISTER_BASE_ADDR_V 25:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_REGISTER_BASE_ADDR_V_0 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_ST_CONSTANT 0x00502744 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_ST_CONSTANT__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_ST_CONSTANT_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_ST_CONSTANT_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE 0x00502714 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_FIFO_FREE_ENTRIES 4:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_FIFO_FREE_ENTRIES_IV 0x10 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_FIFO_TOTAL_ENTRIES 12:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_FIFO_TOTAL_ENTRIES_IV 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_DIRECTION 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_DIRECTION_SAVE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_DIRECTION_RESTORE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_START 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_START_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_START_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_FINISH 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_FINISH_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_FINISH_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_NO_ADDR_INC 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_NO_ADDR_INC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_NO_ADDR_INC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_PRIV_LEVEL 29:28 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_PRIV_LEVEL_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_LOWER_PRIV_LEVEL 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_LOWER_PRIV_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_MODE_LOWER_PRIV_LEVEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PREFETCH_CTL 0x00502740 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PREFETCH_CTL__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PREFETCH_CTL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PREFETCH_CTL_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PREFETCH_CTL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PREFETCH_CTL_OFFSET 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_PREFETCH_CTL_OFFSET_10 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_INDEX_INCREMENT 0x00502718 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_INDEX_INCREMENT__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_INDEX_INCREMENT_V 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_INDEX_INCREMENT_V_0 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_INDEX_MASK 0x0050271c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_INDEX_MASK__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_INDEX_MASK_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_INDEX_MASK_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH 0x00502720 /* -W-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_USE_BASE_ADDR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_USE_INDEXER 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_ADDR 25:2 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_REGISTER_COUNT 30:26 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_SPECIAL 31:31 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_SPECIAL_DATA 25:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_SPECIAL_COUNT 11:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD 30:26 /* -WXVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_NOP 0x00 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_WAIT 0x01 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_STORE_CONSTANT 0x02 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_SKIP_DATA 0x03 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_SET_REG_COUNT 0x04 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ 0x00502728 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_USE_BASE_ADDR_NOT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_ADDR 25:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_ADDR_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_LOWER_PRIV_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_LOWER_PRIV_LEVEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_TRANS_STATUS 28:27 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_TRANS_STATUS_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_TRANS_STATUS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_TRANS_STATUS_DONE 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_TRANS_TYPE 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_TRANS_TYPE_READ 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_TRANS_TYPE_UNDEF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_TRANS_TYPE_WRITE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_TRANS_TYPE_WRITE_ACK 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_CMD 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_CMD_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_CMD_GO 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A 0x00502734 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_USE_BASE_ADDR_NOT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_ADDR 25:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_ADDR_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_TRANS_STATUS 28:27 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_TRANS_STATUS_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_TRANS_STATUS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_TRANS_STATUS_DONE 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE_READ 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE_UNDEF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE_WRITE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE_WRITE_ACK 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_CMD 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_CMD_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_A_CMD_GO 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B 0x00502738 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_USE_BASE_ADDR_NOT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_ADDR 25:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_ADDR_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_TRANS_STATUS 28:27 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_TRANS_STATUS_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_TRANS_STATUS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_TRANS_STATUS_DONE 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE_READ 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE_UNDEF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE_WRITE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE_WRITE_ACK 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_CMD 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_CMD_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_B_CMD_GO 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_READ_DATA 0x0050272c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_READ_DATA_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_READ_DATA_A 0x00502754 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_READ_DATA_A_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_READ_DATA_B 0x00502758 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_READ_DATA_B_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_WRITE_DATA 0x00502730 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_WRITE_DATA__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_WRITE_DATA_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_WRITE_DATA_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_WRITE_DATA_A 0x0050273c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_WRITE_DATA_A__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_WRITE_DATA_A_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_WRITE_DATA_A_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_WRITE_DATA_B 0x00502750 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_WRITE_DATA_B__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_WRITE_DATA_B_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_WRITE_DATA_B_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_STATUS 0x00502764 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_STATUS_PRIV_LEVEL 1:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_STATUS_PRIV_LEVEL_A 5:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PV_PRIV_REQ_STATUS_PRIV_LEVEL_B 9:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_COMPUTED_CHECKSUM 0x00502774 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_COMPUTED_CHECKSUM__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_COMPUTED_CHECKSUM_RESULTS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_SAVED_CHECKSUM 0x00502778 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_SAVED_CHECKSUM__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_SAVED_CHECKSUM_RESULTS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_CHECKSUM 0x0050277c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_CHECKSUM__PRIV_LEVEL_MASK 0x00502760 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_CHECKSUM_CTRL_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_CHECKSUM_CTRL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_CHECKSUM_STATUS_MATCH 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PVS_CHECKSUM_STATUS_MISMATCH 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_LANE_CTL 0x00502a00 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES_V 0x8 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_LANE_CTL_WRR_WEIGHT 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_LANE_CTL_WRR_WEIGHT_V 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_BASE_ADDR 0x00502a04 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_BASE_ADDR_F 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_BASE_ADDR_F_V 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_HI_BASE_ADDR 0x00502a38 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_HI_BASE_ADDR_F 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_HI_BASE_ADDR_F_V 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_ENGINE_CTL 0x00502a3c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_ENGINE_CTL_ENGINE_ID 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_ENGINE_CTL_ENGINE_ID_VEID0 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_ENGINE_CTL_ENGINE_ID_BAR2_FN0 0xc0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_ENGINE_CTL_VEID 21:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_ENGINE_CTL_VEID_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_ENGINE_CTL_GFID 29:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_ENGINE_CTL_GFID_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_PREFETCH_CTL 0x00502a08 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_PREFETCH_CTL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_PREFETCH_CTL_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_PREFETCH_CTL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_PREFETCH_CTL_OFFSET 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_PREFETCH_CTL_OFFSET_V 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK 0x00502a28 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD 0x00502a10 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD__PRIV_LEVEL_MASK 0x00502a28 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_IDLE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_FB_OP_FLUSH 0x05 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_FB_OP_SOFT_FLUSH 0x06 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_FB_OP_BIND_INST_BLK_PTR 0x07 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_FB_OP_MMU_TLB_INVALIDATE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_PREFETCH 0x0a /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_FB_OP_PHYSICAL_L2_CACHE_MGMT 0x0b /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_CACHE_MGMT 0x0c /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_FB_OP_L2_PEER_INVALIDATE 0x0d /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_FB_OP_L2_SYSMEM_INVALIDATE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_CLEAN_COMPTAGS 0x0f /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_FLUSH_DIRTY 0x10 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_CMD_MEMBAR 0x01 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_SUB_OP 8:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_SUB_OP_INVALIDATE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_SUB_OP_CLEAN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_SUB_OP_DEMOTE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_ACK 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_ACK_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_ACK_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_ACK_TLB 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_ACK_MEM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_ACK_NONE_REQUIRED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_ACK_GLOBALLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_ACK_INTRANODE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_HALT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_HALT_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_HALT_REQUEST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_UNHALT 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_UNHALT_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CTX_CMD_UNHALT_REQUEST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_L2_EVICTION_CTL 0x00502a14 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_L2_EVICTION_CTL_WR 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_L2_EVICTION_CTL_WR_FIRST 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_L2_EVICTION_CTL_WR_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_L2_EVICTION_CTL_WR_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_L2_EVICTION_CTL_RD 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_L2_EVICTION_CTL_RD_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_L2_EVICTION_CTL_RD_NORMAL 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_L2_EVICTION_CTL_RD_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_PRIV 0x00502a18 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_PRIV_OVERRIDE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_PRIV_OVERRIDE_PRIV 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_PRIV_OVERRIDE_NONPRIV 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS 0x00502a1c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_CLEAR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_CLEAR_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_CLEAR_CLEAR 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_ACK 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_ACK_OK 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_ACK_NACK 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_SUBID 15:2 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_OUTSTANDING_TRANSACTIONS 23:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_BUFFER_NOT_EMPTY 24:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_FLUSH_WHEN_BUSY 28:28 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_FLUSH_WHEN_BUSY_DEFAULT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_FLUSH_WHEN_BUSY_ERROR 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_HALTED 30:30 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_STATUS_BUSY 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CMD_OVERRIDE 0x00502a20 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CMD_OVERRIDE_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CMD_OVERRIDE_CMD_VIRTUAL 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_VID_MEM 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_NONCOHERENT 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_COHERENT 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CMD_OVERRIDE_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CMD_OVERRIDE_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_CMD_OVERRIDE_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR 0x00502a2c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR__PRIV_LEVEL_MASK 0x00502a28 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_RC_ID 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_RC_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_RC_SECURE_LEVEL 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_RC_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PVS_ID 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PVS_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PVS_SECURE_LEVEL 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_PVS_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_CMD_ID 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_CMD_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_CMD_SECURE_LEVEL 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_CMD_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_BLOCKED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_ALLOWED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK 0x00502a30 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG 0x00502a34 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG__PRIV_LEVEL_MASK 0x00502a30 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T0 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T1 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T2 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T3 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T4 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T5 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T6 27:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T7 31:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_ARB_FALCON_REGIONCFG_T7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON 0x005028a0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_FB_CMD 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_FB_CMD2 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_FB_CMD3 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_FB_DATA 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_MISC_0 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_MISC_1 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_0 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_1 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_2 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_3 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_4 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_5 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_6 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_7 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_8 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_9 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_10 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_11 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_12 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_13 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_14 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_15 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_17 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_18 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_RC_0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_RC_1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_RC_2 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_RC_3 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_RC_4 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_RC_5 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_RC_6 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_RC_7 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_RC_8 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_RC_9 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_RC_10 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_0 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_1 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_2 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_3 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_4 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_5 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_6 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_7 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_9 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_10 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PROBE_0 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PROBE_1 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_ARB_0 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_ARB_1 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_ERR 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_MISC_2 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_MISC_3 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_MISC_4 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_MISC_5 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_MISC_6 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_19 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_20 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_21 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_22 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_23 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_24 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_25 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_26 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_27 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_28 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_29 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_30 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_31 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_32 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_33 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_34 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_35 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_PRI_36 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATIC_PATTERN_55_8_GROUP 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATIC_PATTERN_AA_8_GROUP 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_11 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_12 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_13 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_14 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_STATUS_15 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_CTXSW_0 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_SEL_ECC_ERR 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_CTRL_ENABLE 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_CTRL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM 0x005028a8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_PROBE 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_PROBE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT0 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT1 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT2 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT3 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT4 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT5 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT6 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT7 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_SET 23:16 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_SET_INIT 0x00 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_SET_BIT0 0x01 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_SET_BIT1 0x02 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_SET_BIT2 0x04 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_SET_BIT3 0x08 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_SET_BIT4 0x10 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_SET_BIT5 0x20 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_SET_BIT6 0x40 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_SET_BIT7 0x80 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_CLEAR 31:24 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_CLEAR_INIT 0x00 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_CLEAR_BIT0 0x01 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_CLEAR_BIT1 0x02 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_CLEAR_BIT2 0x04 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_CLEAR_BIT3 0x08 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_CLEAR_BIT4 0x10 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_CLEAR_BIT5 0x20 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_CLEAR_BIT6 0x40 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM_CLEAR_BIT7 0x80 /* -W--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_MODE 0x005028a4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_MODE_PROBE 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_MODE_PROBE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x00502c80 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_SETUP 2:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_SETUP_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_SETUP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_SETUP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_SETUP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_SETUP_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_SETUP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_SETUP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_SETUP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_CRSTR 5:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_CRSTR_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_CRSTR_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_CRSTR_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_CRSTR_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_CRSTR_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_CRSTR_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_CRSTR_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_CRSTR_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_ZCULL 8:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_ZCULL_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_ZCULL_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_ZCULL_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_ZCULL_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_ZCULL_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_ZCULL_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_ZCULL_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_ZCULL_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_WIDCLIP 11:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_WIDCLIP_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_WIDCLIP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_WIDCLIP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_WIDCLIP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_WIDCLIP_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_WIDCLIP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_WIDCLIP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_WIDCLIP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_FRSTR 14:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_FRSTR_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_FRSTR_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_FRSTR_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_FRSTR_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_FRSTR_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_FRSTR_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_FRSTR_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_FRSTR_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_TC 17:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_TC_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_TC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_TC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_TC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_TC_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_TC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_TC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_TC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_RASTERARB 20:18 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_RASTERARB_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_RASTERARB_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_RASTERARB_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_RASTERARB_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_RASTERARB_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_RASTERARB_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_RASTERARB_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_RASTERARB_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_PROP 23:21 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_PROP_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_PROP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_PROP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_PROP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_PROP_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_PROP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_PROP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_PROP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_GPCCS 26:24 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_GPCCS_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_GPCCS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_GPCCS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_GPCCS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_GPCCS_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_GPCCS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_GPCCS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0_GPCCS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x00502c84 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMPD 2:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMPD_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMPD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMPD_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMPD_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMPD_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMPD_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMPD_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMPD_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMSD 5:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMSD_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMSD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMSD_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMSD_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMSD_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMSD_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMSD_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMSD_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMREPORT 8:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMREPORT_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMREPORT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMREPORT_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMREPORT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMREPORT_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMREPORT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMREPORT_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPMREPORT_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_SWDX 11:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_SWDX_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_SWDX_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_SWDX_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_SWDX_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_SWDX_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_SWDX_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_SWDX_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_SWDX_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_WDXPS 14:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_WDXPS_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_WDXPS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_WDXPS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_WDXPS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_WDXPS_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_WDXPS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_WDXPS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_WDXPS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GCC 17:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GCC_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GCC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GCC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GCC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GCC_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GCC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GCC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GCC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPCMMU0 20:18 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPCMMU0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPCMMU0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPCMMU0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPCMMU0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPCMMU0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPCMMU0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPCMMU0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GPCMMU0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GNIC 23:21 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GNIC_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GNIC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GNIC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GNIC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GNIC_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GNIC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GNIC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1_GNIC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x00502c88 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES0 2:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES1 5:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES2 8:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES2_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES2_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES2_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES2_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES2_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES2_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES2_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_PES2_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR0 11:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR1 14:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR2 17:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR2_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR2_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR2_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR2_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR2_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR2_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR2_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_CBMGR2_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX0 20:18 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX1 23:21 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX2 26:24 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX2_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX2_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX2_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX2_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX2_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX2_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX2_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2_WWDX2_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x00502c8c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC0 2:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC1 5:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC2 8:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC2_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC2_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC2_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC2_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC2_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC2_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC2_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC2_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC3 11:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC3_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC3_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC3_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC3_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC3_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC3_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC3_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC3_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC4 14:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC4_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC4_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC4_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC4_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC4_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC4_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC4_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC4_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC5 17:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC5_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC5_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC5_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC5_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC5_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC5_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC5_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3_TPC5_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4 0x00502c9c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP0 2:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP1 5:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_CROP1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP0 8:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP1 11:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_ZROP1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH0 14:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH1 17:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY4_RRH1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x00502c90 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PROP 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PROP_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PROP_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZCULL 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZCULL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZCULL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_GCC 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_GCC_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_GCC_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_SETUP 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_SETUP_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_SETUP_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES0 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES0_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES0_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES1 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES1_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES1_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES2 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES2_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES2_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_GPCMMU0 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_GPCMMU0_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_GPCMMU0_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_GPCCS 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_GPCCS_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_GPCCS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC_NOT_PENDING 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC_0_NOT_PENDING 0x00 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC_0_PENDING 0x01 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_CROP0 26:26 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_CROP0_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_CROP0_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZROP0 27:27 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZROP0_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZROP0_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_RRH0 28:28 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_RRH0_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_RRH0_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_CROP1 29:29 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_CROP1_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_CROP1_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZROP1 30:30 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZROP1_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZROP1_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_RRH1 31:31 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_RRH1_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_RRH1_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x00502c94 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_PROP 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_PROP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_PROP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_ZCULL 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_ZCULL_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_ZCULL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_GCC 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_GCC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_GCC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_SETUP 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_SETUP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_SETUP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_PES0 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_PES0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_PES0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_PES1 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_PES1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_PES1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_PES2 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_PES2_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_PES2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_GPCMMU0 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_GPCMMU0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_GPCMMU0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_GPCCS 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_GPCCS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_GPCCS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_TPC_DISABLED 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_TPC_0_DISABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_TPC_0_ENABLED 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_CROP0 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_CROP0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_CROP0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_ZROP0 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_ZROP0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_ZROP0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_RRH0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_RRH0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_RRH0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_CROP1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_CROP1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_CROP1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_ZROP1 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_ZROP1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_ZROP1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_RRH1 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_RRH1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN_RRH1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_HWW_ESR 0x00502c98 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_HWW_ESR_ECC_CORRECTED 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_HWW_ESR_ECC_CORRECTED_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_HWW_ESR_ECC_CORRECTED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_HWW_ESR_ECC_UNCORRECTED 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_HWW_ESR_ECC_UNCORRECTED_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_HWW_ESR_ECC_UNCORRECTED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_DEBUG 0x00502698 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_DEBUG_STATUS_FILTER 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_DEBUG_STATUS_FILTER_INIT 0x16 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_DEBUG_STATUS_FILTER_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_DEBUG_STATUS_FILTER_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_STOP_SM 0x0050269c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_STOP_SM_BIT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_STOP_SM_BIT_CLR 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_STOP_SM_BIT_SET 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG 0x00502890 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_IDLE_CG_DLY_CNT__PROD 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG1 0x00502894 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG1_SLCG 15:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG1_SLCG_DISABLED 0x7fff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG 0x005028b0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_IDLE_CG_DLY_CNT__PROD 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG1 0x005028b4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX 0x005008c0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_ADDRESS 15:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT 20:16 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_ZNEAR0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_ZNEAR1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_ZNEAR2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_ZNEAR3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_ZFAR0 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_ZFAR1 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_ZFAR2 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_ZFAR3 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_ZFAR4 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_ZFAR5 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_ZFAR6 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_ZFAR7 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_STENCIL0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_STENCIL1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_STENCIL2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_STENCIL3 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_STENCIL4 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_STENCIL5 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_STENCIL6 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_SELECT_STENCIL7 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_WRITE 31:31 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_WRITE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_INDEX_WRITE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_DATA 0x005008c4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_DATA_VALUE 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL 0x005008c8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRPA 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRPB 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP_AGG2_OCCLUDERS 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP_AGG2_PARTIAL_FLUSH 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP_ZSLVR 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_GRP_4X2_COUNT 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_STATIC_PATTERN_15_6_GROUP 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_STATIC_PATTERN_2A_6_GROUP 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_PERF_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0 0x005008cc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT1 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT1_COARSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT1_ZCULLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT1_SCULLED 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT1_ZACCEPT 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT1_ZREJECT 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT1_DBCULLED 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT1_FCULLED 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT1_CULLED 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT1_ZFAIL_NO_CULL 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT2 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT2_ZCULL_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT2_SCULL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT2_DBCULL_ENABLE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT2_ZACCEPT_ENABLE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT2_ZSAMPLED_OUTSIDE_PRIM 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT2_8X8_INSIDE 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT2_REGION_VALID 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT3 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT3_PIPE0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT3_PIPE1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT3_PIPE2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT3_PIPE3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0_PM_SELECT3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1 0x005008d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_RESULT_NF_PASS 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_RESULT_NF_PASS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_RESULT_NF_PASS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_RESULT_DB_PASS 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_RESULT_DB_PASS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_RESULT_DB_PASS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISCARD_THRESH_SEVEN_EIGHTS 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISCARD_THRESH_SEVEN_EIGHTS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISCARD_THRESH_SEVEN_EIGHTS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_RESULT_ZFAIL 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_RESULT_ZFAIL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_RESULT_ZFAIL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_RESULT_ZPASS 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_RESULT_ZPASS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_RESULT_ZPASS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_NO_CULL 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_NO_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_NO_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_Z_CULL 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_Z_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_Z_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_S_CULL 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_S_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_S_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_DB_CULL 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_DB_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_DB_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_NF_CULL 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_NF_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_NF_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_ZNEAR_CACHE 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_ZNEAR_CACHE_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_ZNEAR_CACHE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_ZNEAR_MERGE 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_ZNEAR_MERGE_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_ZNEAR_MERGE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISCARD_THRESH_ONE_QUARTER 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISCARD_THRESH_ONE_QUARTER_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISCARD_THRESH_ONE_QUARTER_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISCARD_THRESH_THREE_QUARTER 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISCARD_THRESH_THREE_QUARTER_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISCARD_THRESH_THREE_QUARTER_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_READ_CACHE 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_READ_CACHE_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_READ_CACHE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_FORCE_Z_PER_PRIM 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_FORCE_Z_PER_PRIM_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_FORCE_Z_PER_PRIM_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_STICKY_SCULL 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_STICKY_SCULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_STICKY_SCULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_STENCIL_SUBSETS 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_STENCIL_SUBSETS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_STENCIL_SUBSETS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_OCCLUSION_QUERY_ACCEL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_OCCLUSION_QUERY_ACCEL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_OCCLUSION_QUERY_ACCEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_CULL_TO_NEAR_SIDE 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_CULL_TO_NEAR_SIDE_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_CULL_TO_NEAR_SIDE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_PER_PRIM_CLAMP 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_PER_PRIM_CLAMP_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_PER_PRIM_CLAMP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_ALWAYS_SYNCED 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_ALWAYS_SYNCED_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_ALWAYS_SYNCED_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_ZPASS_COUNT_AT_256 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_ZPASS_COUNT_AT_256_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_ZPASS_COUNT_AT_256_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_NF_CULL_IF_Z_CULL 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_NF_CULL_IF_Z_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_NF_CULL_IF_Z_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_NO_PACKET_KILL 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_NO_PACKET_KILL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_NO_PACKET_KILL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_NON_BLOCKING_BLOCK 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_NON_BLOCKING_BLOCK_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_NON_BLOCKING_BLOCK_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_Z_PER_SLIVER 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_Z_PER_SLIVER_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_Z_PER_SLIVER_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_REVERSED_ZFUNC_CULL 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_REVERSED_ZFUNC_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_REVERSED_ZFUNC_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_OCCL_OVERLAP 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_OCCL_OVERLAP_0 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_DISABLE_OCCL_OVERLAP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_INVALIDATE_UPON_WRONG_DIR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_INVALIDATE_UPON_WRONG_DIR_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_1_INVALIDATE_UPON_WRONG_DIR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2 0x005008d4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_ZNEAR_NON_MONO 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_ZNEAR_NON_MONO_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_ZNEAR_NON_MONO_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_SAVE_RESTORE_WITH_NO_ALLOCATION_PERMISSION 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_SAVE_RESTORE_WITH_NO_ALLOCATION_PERMISSION_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_SAVE_RESTORE_WITH_NO_ALLOCATION_PERMISSION_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_FORCE_Z_PER_TILE_SHADER_Z 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_FORCE_Z_PER_TILE_SHADER_Z_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_GEN_ROP_STATE_BUNDLE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_GEN_ROP_STATE_BUNDLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_GEN_SYNC_BUNDLE 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_GEN_SYNC_BUNDLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_ZFAIL_NEARER 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_ZFAIL_NEARER_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_CONSERVATIVE_Z_CLAMP 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_DISABLE_CONSERVATIVE_Z_CLAMP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_MORE_CONSERVATIVE_Z_PER_SLIVER 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_MORE_CONSERVATIVE_Z_PER_SLIVER_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_LANA_CLOCKGATE_CONTROL 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_LANA_CLOCKGATE_CONTROL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_LANA_CLOCKGATE_CONTROL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_LANA_CLOCKGATE_CONTROL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_UPDATE_WRITE_WITHOUT_READ 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_UPDATE_WRITE_WITHOUT_READ_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_UPDATE_WRITE_WITHOUT_READ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_UPDATE_WRITE_WITHOUT_READ_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_17 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_17_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_18 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_18_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_19 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_19_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_20 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_20_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_21 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_21_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_22 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_22_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_23 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_23_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_24 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_24_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_25 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_25_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_26 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_26_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_27 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_27_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_28 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_28_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_29 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_29_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_30 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_30_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_31 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_2_SPARE_31_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX1 0x005008d8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX1_PRI_ZCULL_PROC_CUR_STATE 2:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX1_PRI_ZCULL_PROC_CUR_STATE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX1_PRI_ZCULL_BETWEEN_PRIMITIVES 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX1_PRI_ZCULL_BETWEEN_PRIMITIVES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX1_PRI_ZCULL_NON_BLOCKING_STATE 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX1_PRI_ZCULL_NON_BLOCKING_STATE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX1_PRI_ZCULL_STENCIL_WRITTEN 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX1_PRI_ZCULL_STENCIL_WRITTEN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX1_PRI_ZCULL_PROC_SYNC_COUNT 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX1_PRI_ZCULL_PROC_SYNC_COUNT_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX5 0x005008e0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX5_PRI_ZCULL_UPDATE_SYNC_COUNT 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX5_PRI_ZCULL_UPDATE_SYNC_COUNT_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX5_PRI_ZCULL_SYNC_SINCE_LAST_TILE 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX5_PRI_ZCULL_SYNC_SINCE_LAST_TILE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX6 0x005008e8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX6_PRI_ZCULL_ZPASS_PIXEL_COUNT 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX6_PRI_ZCULL_ZPASS_PIXEL_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX7 0x005008ec /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX7_PRI_ZCULL_TOTAL_8X8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX7_PRI_ZCULL_TOTAL_8X8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX8 0x005008f0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX8_PRI_ZCULL_ZFAIL_4X2 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX8_PRI_ZCULL_ZFAIL_4X2_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX9 0x005008f4 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX9_PRI_ZCULL_ZPASS_8X8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX9_PRI_ZCULL_ZPASS_8X8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX10 0x005008f8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX10_PRI_ZCULL_STNCL_4X4 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX10_PRI_ZCULL_STNCL_4X4_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG 0x005008fc /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_ZPASS_CULL_AFTER_FULLY_COVERED 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_ZPASS_CULL_AFTER_FULLY_COVERED_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_ZPASS_CULL_AFTER_PARTIALLY_COVERED 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_ZPASS_CULL_AFTER_PARTIALLY_COVERED_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_ZFAIL_REPORT_NOT_EQUAL_TOTAL_COARSE_TILES 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_ZFAIL_REPORT_NOT_EQUAL_TOTAL_COARSE_TILES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_ZF32_AS_Z16 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_ZF32_AS_Z16_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_PROC_TO_UPDATE_OCCLUDERS_ENABLE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_PROC_TO_UPDATE_OCCLUDERS_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_TWO_Z_1XAA_UPDATES_DISABLE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_TWO_Z_1XAA_UPDATES_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_BLKACTIVITY_DISABLE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_GFXP_DISABLE 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_GFXP_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_SPARE_12 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_SPARE_12_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_SPARE_13 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_SPARE_13_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_SPARE_14 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_SPARE_14_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_SPARE_15 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_SPARE_15_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_OCCL_OVERLAP_THRESHOLD 20:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_OCCL_OVERLAP_THRESHOLD_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_IGNORE_INSUFF_BANKS_RAMFORMAT 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_IGNORE_INSUFF_BANKS_RAMFORMAT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_USE_Z_OUTSIDE_PRIM 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_USE_Z_OUTSIDE_PRIM_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_Z_OUTSIDE_PRIM_OFFSET 29:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CTX_DEBUG_Z_OUTSIDE_PRIM_OFFSET_INIT 0x8 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR 0x00500900 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_SAVE_RESTORE_ADDR_OOB 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_SAVE_RESTORE_ADDR_OOB_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_SAVE_RESTORE_ADDR_OOB_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_RESET_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_INFO_0 0x00500904 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_INFO_0_ADDRESS_LOW 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_INFO_1 0x00500908 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_INFO_1_ADDRESS_HIGH 7:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_INFO_1_LIMIT_ADDRESS_HIGH 15:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_INFO_2 0x0050090c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HWW_ESR_INFO_2_LIMIT_ADDRESS_LOW 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x00500910 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS_INIT 0x001 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_BANKS 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x00500914 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET_INIT 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x00500918 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE_INIT 0x800000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_REGION_PERMISSION 0x0050091c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_REGION_PERMISSION_ALLOCATION_MASK 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_REGION_PERMISSION_ALLOCATION_MASK_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_REGION_PERMISSION_MASK 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_REGION_PERMISSION_MASK_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x00500920 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS 31:16 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X16X2_4X4 0x0001 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_4X4 0x0001 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_16X16_4X4 0x0002 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_4X4 0x0002 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X16_4X2 0x0004 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_4X2 0x0004 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_2X4 0x0008 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X16_2X4 0x0008 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X8_4X4 0x0010 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_8X8_4X2 0x0020 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_8X8_2X4 0x0040 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X16_4X8 0x0080 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_4X8_2X2 0x0100 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_16X8_4X2 0x0200 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_16X8_2X4 0x0400 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_8X8_2X2 0x0800 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_4X8_1X1 0x1000 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_SPARE0 0x2000 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_SPARE1 0x4000 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_SPARE2 0x8000 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_OFFSET 0x00500924 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_OFFSET_AMOUNT 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_OFFSET_AMOUNT_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_THRESHOLD_1 0x00500928 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_THRESHOLD_1_MIN_ZCENTER 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_THRESHOLD_1_MIN_ZCENTER_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_THRESHOLD_1_MAX_ZCENTER 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_THRESHOLD_1_MAX_ZCENTER_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_THRESHOLD_1_MAX_CLIPPED_SLOPE 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_THRESHOLD_1_MAX_CLIPPED_SLOPE_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_THRESHOLD_0 0x0050092c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_THRESHOLD_0_MIN_SLOPE 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_THRESHOLD_0_MIN_SLOPE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_THRESHOLD_0_MAX_SLOPE 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_Z_GAMUT_THRESHOLD_0_MAX_SLOPE_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL 0x00500930 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL_SAVE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL_SAVE_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL_SAVE_RUN 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL_RESTORE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL_RESTORE_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL_RESTORE_RUN 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL_SCRUB 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL_SCRUB_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL_SCRUB_RUN 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL_SCRUBBED 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL_SCRUBBED_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_CTRL_SCRUBBED_TRUE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_ADDR 0x00500934 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_ADDR_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_ADDR_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_SIZE 0x00500938 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DIRECT_CTXSW_SIZE_VALUE 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HEAVY_BUNDLE_ADDITIONS 0x0050093c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HEAVY_BUNDLE_ADDITIONS_ADDRESS_0 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HEAVY_BUNDLE_ADDITIONS_ADDRESS_0_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HEAVY_BUNDLE_ADDITIONS_ADDRESS_1 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_HEAVY_BUNDLE_ADDITIONS_ADDRESS_1_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_LIMIT0 0x00500940 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_LIMIT0_CRSTR2ZCULL_VALUE 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_LIMIT0_CRSTR2ZCULL_VALUE_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_LIMIT0_WIDREQ2ZCULL_VALUE 19:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_LIMIT0_WIDREQ2ZCULL_VALUE_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC 0x00500944 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_FLUSH_PENDING_WRITES_BUNDLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_FLUSH_PENDING_WRITES_BUNDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_FLUSH_PENDING_WRITES_BUNDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_REPORT_SEMAPHORE_D_BUNDLE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_REPORT_SEMAPHORE_D_BUNDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_REPORT_SEMAPHORE_D_BUNDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_BACK_END_COPY_E_BUNDLE 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_BACK_END_COPY_E_BUNDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_BACK_END_COPY_E_BUNDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_PM_TRIGGER_END_BUNDLE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_PM_TRIGGER_END_BUNDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_PM_TRIGGER_END_BUNDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BUNDLE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BUNDLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BUNDLE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SYNC_ON_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BUNDLE__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG 0x00500970 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG1 0x00500974 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP(i) (0x00500980+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP__SIZE_1 32 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_0 2:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_0_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_1 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_1_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_2 10:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_2_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_3 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_3_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_4 18:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_4_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_5 22:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_5_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_6 26:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_6_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_7 30:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_7_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION(i) (0x00500a00+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_FAR_Z 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_FAR_Z_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT 15:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_LOW_RES_Z 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_Z_16X16_4X2 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_LOW_RES_Z_2X4 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_Z_16X16_2X4 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_HIGH_RES_Z 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_Z_16X16X2_4X4 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_LOW_RES_ZS 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_ZS_16X16_4X4 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_Z_16X8_4X4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_Z_8X8_4X2 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_Z_8X8_2X4 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_Z_16X16_4X8 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_Z_4X8_2X2 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_ZS_16X8_4X2 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_ZS_16X8_2X4 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_ZS_8X8_2X2 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_Z_4X8_1X1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_Z_NONE 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCREGION_RAMFORMAT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x00500a04+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT__MULTIPLE 0x020 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x040 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT__MAX 0x4000 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH__MULTIPLE 0x0010 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 0x0010 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH__MAX 0x4000 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCOFFSET(i) (0x00500a08+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCOFFSET__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCOFFSET_Y 11:0 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCOFFSET_Y_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCOFFSET_Y__MULTIPLE 0x010 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCOFFSET_X 27:16 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCOFFSET_X_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCOFFSET_X__MULTIPLE 0x010 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRT_ARRAY_INDEX(i) (0x00500a0c+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRT_ARRAY_INDEX__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRT_ARRAY_INDEX_OFFSET 10:0 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRT_ARRAY_INDEX_OFFSET_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRT_ARRAY_INDEX_SIZE 27:16 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRT_ARRAY_INDEX_SIZE_INIT 0x001 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTART(i) (0x00500a10+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTART__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTART_ADDR 15:0 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTART_ADDR_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTART_ADDR__MULTIPLE 0x0001 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTART_NORMALIZED_SIZE_PER_LAYER 31:16 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTART_NORMALIZED_SIZE_PER_LAYER_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_SIZE(i) (0x00500a14+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_SIZE__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_SIZE_TOTAL 15:0 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_SIZE_TOTAL_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_SIZE_PER_LAYER 31:16 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCRAM_SIZE_PER_LAYER_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS(i) (0x00500a18+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_VALID 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_VALID_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_VALID_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_ZDIR 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_ZDIR_LESS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_ZDIR_GREATER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_ZDIR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_ZFORMAT 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_ZFORMAT_MSB 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_ZFORMAT_FP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_ZFORMAT_ZTRICK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_ZFORMAT_ZF32_1 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_ZFORMAT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_FORCE_MATCH 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_FORCE_MATCH_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_FORCE_MATCH_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_FORCE_MATCH_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SUBREGION_MODE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SUBREGION_MODE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SUBREGION_MODE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SUBREGION_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SFUNC 14:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SFUNC_NEVER 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SFUNC_LESS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SFUNC_EQUAL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SFUNC_LEQUAL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SFUNC_GREATER 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SFUNC_NOTEQUAL 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SFUNC_GEQUAL 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SFUNC_ALWAYS 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SFUNC_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SREF 23:16 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SREF_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SMASK 31:24 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSTATUS_SMASK_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG 0x00500000 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ZBC_EN 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ZBC_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ZBC_EN_ENABLED 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ZBC_EN_Z_ONLY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ZBC_EN_C_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ZBC_EN_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_EARLYZ_NOUPDATE 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_EARLYZ_NOUPDATE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_EARLYZ_NOUPDATE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_EARLYZ_NOUPDATE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_EARLYZ_IGNORE_PXCNT 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_EARLYZ_IGNORE_PXCNT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_EARLYZ_IGNORE_PXCNT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_EARLYZ_IGNORE_PXCNT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_EARLYZ 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_EARLYZ_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_EARLYZ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_EARLYZ_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_RUN_DS_NOW 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_RUN_DS_NOW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_RUN_DS_NOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ZONLY 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ZONLY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ZONLY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ZONLY_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_STENCIL_KEEP 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_STENCIL_KEEP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_STENCIL_KEEP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_STENCIL_KEEP_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_DS_ROP_FORCE_BC_ON 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_DS_ROP_FORCE_BC_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_DS_ROP_FORCE_BC_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_DS_ROP_FORCE_BC_ON_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_DS_PROP_FORCE_BC_ON 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_DS_PROP_FORCE_BC_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_DS_PROP_FORCE_BC_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_DS_PROP_FORCE_BC_ON_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_DS_RSTR_FORCE_BC_ON 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_DS_RSTR_FORCE_BC_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_DS_RSTR_FORCE_BC_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_DS_RSTR_FORCE_BC_ON_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_RTL_KNOBS 17:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_RTL_KNOBS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_RTL_KNOBS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_BYPASS_PROP 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_BYPASS_PROP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_BYPASS_PROP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_BYPASS_PROP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_BYPASS_ROP 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_BYPASS_ROP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_BYPASS_ROP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_BYPASS_ROP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_BYPASS_RSTR 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_BYPASS_RSTR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_BYPASS_RSTR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_BYPASS_RSTR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_COLOR 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_COLOR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_COLOR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_COLOR_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_DEPTH 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_DEPTH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_DEPTH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_DEPTH_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_STENCIL 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_STENCIL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_STENCIL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_STENCIL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ROP_ALWAYS_DIRTY 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ROP_ALWAYS_DIRTY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ROP_ALWAYS_DIRTY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_ROP_ALWAYS_DIRTY_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_SP_SWIZZLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_SP_SWIZZLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_SP_SWIZZLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_DEBUG_SP_SWIZZLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG 0x00500004 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG_USE_DS_CT_SEL_DL_SRC_BLND 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG_USE_DS_CT_SEL_DL_SRC_BLND_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG_USE_CT_SEL_PITCH_ACTIVE 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG_USE_CT_SEL_PITCH_ACTIVE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG_DS_PROPAGATE_BDL_ENABLE 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG_DS_PROPAGATE_BDL_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG_X_CHANNEL_ONLY_MATCH_0 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG_X_CHANNEL_ONLY_MATCH_0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG_X_CHANNEL_ONLY_MATCH_0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG_X_CHANNEL_ONLY_MATCH_0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG_EXTRA_PROPAGATION_CYC 31:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG_EXTRA_PROPAGATION_CYC_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG2 0x00500008 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG2_DS_PROPAGATE_BDL_ADDR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG2_DS_PROPAGATE_BDL_ADDR_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG2_STENCIL_ZBC_EN 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG2_STENCIL_ZBC_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG2_STENCIL_ZBC_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG2_STENCIL_ZBC_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG2_SPARE 31:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ROP_DEBUG2_SPARE_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_R(i) (0x00500010+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_R__SIZE_1 15 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_R_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_R_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_G(i) (0x0050004c+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_G__SIZE_1 15 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_G_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_G_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_B(i) (0x00500088+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_B__SIZE_1 15 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_B_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_B_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_A(i) (0x005000c4+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_A__SIZE_1 15 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_A_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_COLOR_A_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT 0x00500100 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03 20:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04 27:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT 0x00500104 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07 20:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08 27:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT 0x00500108 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11 20:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12 27:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT 0x0050010c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15 20:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z(i) (0x00500110+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z__SIZE_1 15 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT 0x0050014c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_01 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_01_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_01_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_01_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_02 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_02_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_02_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_02_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_03 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_03_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_03_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_03_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_04 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_04_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_04_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_04_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT 0x00500150 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_05 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_05_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_05_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_05_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_06 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_06_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_06_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_06_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_07 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_07_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_07_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_07_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_08 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_08_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_08_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_08_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT 0x00500154 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_09 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_09_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_09_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_09_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_10 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_10_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_10_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_10_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_11 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_11_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_11_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_11_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_12 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_12_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_12_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_12_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT 0x00500158 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_13 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_13_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_13_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_13_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_14 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_14_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_14_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_14_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_15 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_15_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_15_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_15_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S(i) (0x0050015c+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S__SIZE_1 15 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_VAL 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_VAL__INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT 0x00500198 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_01 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_01_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_01_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_01_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_02 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_02_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_02_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_02_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_03 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_03_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_03_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_03_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_04 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_04_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_04_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_04_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT 0x0050019c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_05 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_05_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_05_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_05_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_06 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_06_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_06_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_06_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_07 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_07_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_07_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_07_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_08 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_08_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_08_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_08_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT 0x005001a0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_09 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_09_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_09_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_09_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_10 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_10_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_10_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_10_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_11 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_11_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_11_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_11_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_12 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_12_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_12_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_12_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT 0x005001a4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_13 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_13_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_13_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_13_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_14 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_14_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_14_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_14_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_15 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_15_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_15_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_15_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG 0x00500e00 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_TILED_CACHING 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_TILED_CACHING_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_TILED_CACHING_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_TC_LAZY_VALIDATION 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_TC_LAZY_VALIDATION_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_TC_LAZY_VALIDATION_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_SETUP_OUTPUT_LIMITER 7:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_SETUP_OUTPUT_LIMITER_DISABLE 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BTWT_FIFO_REDUCE_DIV32 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BTWT_FIFO_REDUCE_DIV32_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BTWT_FIFO_REDUCE_DIV32_FULLSIZE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY_ZERO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY_MULTI 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY_ONE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BIN_SEMAD_REPORT_NONE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BIN_SEMAD_REPORT_NONE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BIN_SEMAD_REPORT_NONE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_PM_MODE_E_BUNDLE_ADDR 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_PM_MODE_E_BUNDLE_ADDR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_PM_MODE_E_BUNDLE_ADDR_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_TREAT_NON_BINNABLE_AS_IMMEDIATE 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_TREAT_NON_BINNABLE_AS_IMMEDIATE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_TREAT_NON_BINNABLE_AS_IMMEDIATE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_SPILL_POINT_PATH 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_SPILL_POINT_PATH_AUTOMATIC 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_SPILL_POINT_PATH_SPILL_BUFFER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BUNDLE_FILTER 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BUNDLE_FILTER_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BUNDLE_FILTER_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_MULTIPLE_INTERVALS_PER_BIN 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_MULTIPLE_INTERVALS_PER_BIN_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_MULTIPLE_INTERVALS_PER_BIN_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_INSERT_DEBUG_TOKENS 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_INSERT_DEBUG_TOKENS_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_INSERT_DEBUG_TOKENS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT 29:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0010 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0020 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0040 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0080 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0100 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0180 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0200 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0300 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0400 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0600 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0800 0xb /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0A00 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0C00 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0E00 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X1000 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BIN_SCC_FEEDBACK_DATA_SYNC 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BIN_SCC_FEEDBACK_DATA_SYNC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_BIN_SCC_FEEDBACK_DATA_SYNC_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_RESERVED 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG_RESERVED_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DEBUG 0x00500e04 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DEBUG_RECEIVED_BAD_BUNDLE_DATA 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DEBUG_RESOLVED_TC_ENABLE 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DEBUG_UNEXPECTED_L0_PACKET 2:2 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DEBUG_OCCUPIED_SPILL_BUFFER_ENTRIES 26:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM 0x00500e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_USERDATA_BUNDLE_FLUSH_GROUP 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_STATIC_PATTERN_2AA_10_GROUP 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_STATIC_PATTERN_155_10_GROUP 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_SELECT_MAX 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_BUNDLE_CB_BASE 0x00500e24 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_BUNDLE_CB_SIZE 0x00500e28 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0x030 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_BUNDLE_CB_SIZE_VALID 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_BUNDLE_CB_SIZE_VALID_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_BUNDLE_CB_SIZE_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_TIMEOUT 0x00500e34 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_TIMEOUT_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_TIMEOUT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_COUNT 0x00500e38 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_COUNT_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_COUNT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO 0x00500e3c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_BUNDLE_ADDR 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON 30:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_CBE_MEMORY 0x0001 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_CBE_SLOT 0x0002 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_PAGEPOOL 0x0003 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_CBTBL 0x0004 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_BIN_MEMORY 0x0005 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_LEVEL0 0x0006 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_LEVEL1 0x0007 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_STATE_COUNT 0x0008 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_TC_FLUSH_METHOD 0x0009 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_RTV_LIMIT_HIT 0x000a /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_NON_BINNABLE_STATE 0x000b /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_TIMEOUT 0x000c /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_INTERVAL_BOUNDARY 0x000d /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_NON_BINNABLE_LINES 0x000e /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_TIMESLICE_BUNDLE 0x000f /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_REASON_Z_MODE_TRANSITION 0x0010 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_FLUSH_INFO_VALID 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL(i) (0x00500e40+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_0 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_0_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_0_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE 2:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_0_TYPE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_0_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_0_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_1 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_1_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_1_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE 6:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_1_TYPE 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_1_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_1_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_2 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_2_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_2_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE 10:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_2_TYPE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_2_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_2_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_3 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_3_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_3_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE 14:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_3_TYPE 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_3_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_3_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_4 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_4_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_4_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE 18:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_4_TYPE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_4_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_4_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_5 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_5_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_5_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE 22:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_5_TYPE 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_5_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_5_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_6 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_6_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_6_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE 26:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_6_TYPE 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_6_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_6_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_7 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_7_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_7_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE 30:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_7_TYPE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_7_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_CTRL_SLOT_7_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL(i) (0x00500e50+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_0 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_0_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_0_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_0_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_1 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_1_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_1_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_1_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_2 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_2_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_2_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_2_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_3 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_3_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_3_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_3_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_4 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_4_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_4_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_4_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_5 11:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_5_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_5_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_5_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_6 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_6_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_6_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_6_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_7 15:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_7_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_7_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_7_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_8 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_8_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_8_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_8_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_9 19:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_9_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_9_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_9_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_10 21:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_10_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_10_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_10_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_11 23:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_11_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_11_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_11_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_12 25:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_12_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_12_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_12_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_13 27:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_13_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_13_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_13_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_14 29:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_14_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_14_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_14_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_15 31:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_15_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_15_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_15_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_ADDR(i) (0x00500e58+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_ADDR__SIZE_1 16 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_ADDR_SLOT_0 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_ADDR_SLOT_0_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_ADDR_SLOT_1 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BUNDLE_ADDR_SLOT_1_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT 0x00500e9c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_READ 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_READ_EVICT_FIRST 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_READ_EVICT_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_READ_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_WRITE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_WRITE_EVICT_FIRST 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_WRITE_EVICT_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_WRITE_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_WRITE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_WRITE_EVICT_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_WRITE_EVICT_NORMAL 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_WRITE_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_READ 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_READ_EVICT_FIRST 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_READ_EVICT_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_READ_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_STATE_READ 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_STATE_READ_EVICT_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_STATE_READ_EVICT_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LINE_CLASS_STATE_READ_EVICT_LAST 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_SPILL_BUFFER_CACHE_MGMT_MODE 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_SPILL_BUFFER_CACHE_MGMT_MODE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_SPILL_BUFFER_CACHE_MGMT_MODE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_DIRECT_CTXSW_WRITE_BURST_MODE 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_DIRECT_CTXSW_WRITE_BURST_MODE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_DIRECT_CTXSW_WRITE_BURST_MODE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_TC_TIMEOUT_ENABLE_MODE 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_TC_TIMEOUT_ENABLE_MODE_A 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_TC_TIMEOUT_ENABLE_MODE_B 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_TC_TIMEOUT_DISABLE_MODE 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_TC_TIMEOUT_DISABLE_MODE_A 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_TC_TIMEOUT_DISABLE_MODE_B 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_SPILL_WRITE_BURST_MODE 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_SPILL_WRITE_BURST_MODE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_SPILL_WRITE_BURST_MODE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION 22:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION_NONE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION_HALF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION_QUARTER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION_EIGHTH 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION 24:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION_NONE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION_HALF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION_QUARTER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION_EIGHTH 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION_NONE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION_HALF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION_QUARTER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION_EIGHTH 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BETA_CB_SIZE(i) (0x00500ea0+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BETA_CB_SIZE__SIZE_1 21 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BETA_CB_SIZE_V 21:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BETA_CB_SIZE_V_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_TC_BETA_CB_SIZE_V_DEFAULT 0x000480 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG2 0x005001cc /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG2_ASYNC_TC_OVERRIDE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG2_ASYNC_TC_OVERRIDE_NONE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONFIG2_ASYNC_TC_OVERRIDE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK 0x005001d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_0 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_1 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_2 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_3 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_4 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_5 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_6 27:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_7 31:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_PES_MASK_GPC_7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_ADDR 0x005001d8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_ADDR_39_8_BYTE_GRANULARITY 0x00000100 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_ADDR_39_8_ALIGN_BITS 0x00000008 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_SIZE 0x005001dc /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_SIZE_256B 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_SIZE_256B_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_SIZE_256B_DEFAULT 0x0578 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_SIZE_256B_BYTE_GRANULARITY 0x0100 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_LWM 0x005001e0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_LWM_SIZE_256B 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_RM_SPILL_BUFFER_LWM_SIZE_256B_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_BETA_CB_CTRL 0x005001e4 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_BETA_CB_CTRL_CBES_RESERVE 11:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_BETA_CB_CTRL_CBES_RESERVE_NON_GFXP 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_BETA_CB_CTRL_CBES_RESERVE_GFXP 0x100 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL 0x005001e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_SAVE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_SAVE_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_SAVE_RUN_WFI 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_SAVE_RUN_GFXP 0x2 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_RESTORE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_RESTORE_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_RESTORE_RUN_WFI 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_RESTORE_RUN_GFXP 0x2 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_RESTORE_RUN_SCRUB 0x3 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_STATUS_SAVED 9:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_STATUS_SAVED_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_STATUS_SAVED_WFI 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_STATUS_SAVED_GFXP 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED 11:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED_WFI 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED_GFXP 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED_SCRUB 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_BINNER_RAM_STATUS 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_BINNER_RAM_STATUS_EMPTY 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_CTRL_BINNER_RAM_STATUS_NONEMPTY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_ADDR 0x005001ec /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_ADDR_39_8 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_ADDR_39_8_BYTE_GRANULARITY 0x00000100 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_ADDR_39_8_ALIGN_BITS 0x00000008 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_SIZE_WFI 0x005001f0 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_SIZE_WFI_VALUE 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_SIZE_GFXP 0x005001f4 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_DIRECT_CTXSW_SIZE_GFXP_VALUE 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONST_LIMITS_TS_ON 0x005001f8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONST_LIMITS_TS_ON_PPOOL 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONST_LIMITS_TS_ON_PPOOL_INIT 0x1c2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONST_LIMITS_TS_ON_CBTBL 25:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONST_LIMITS_TS_ON_CBTBL_INIT 0x1c2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONST_LIMITS_TS_OFF 0x005001fc /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONST_LIMITS_TS_OFF_PPOOL 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONST_LIMITS_TS_OFF_PPOOL_INIT 0x1f2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONST_LIMITS_TS_OFF_CBTBL 25:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CONST_LIMITS_TS_OFF_CBTBL_INIT 0x1f2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RTV_LIMITS 0x005001c8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_RTV_LIMITS_TS_OFF 13:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_RTV_LIMITS_TS_OFF_INIT 0x000d /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_RTV_LIMITS_TS_ON 29:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_RTV_LIMITS_TS_ON_INIT 0x000c /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG 0x00500e0c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG1 0x00500e10 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SWDX_CG1_SLCG__PROD 0x7fffffff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL 0x00500880 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_VM_PG_SIZE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_VM_PG_SIZE_128KB 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_VM_PG_SIZE_64KB 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_COMP_FAULT 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_COMP_FAULT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_COMP_FAULT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_MISS_GRAN 4:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_MISS_GRAN_FULL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_MISS_GRAN_HALF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_MISS_GRAN_QUARTER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_MISS_GRAN_NO_PTE_COMP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_CACHE_MODE 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_CACHE_MODE_ON 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_CACHE_MODE_OFF 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_PDE_CACHE_MODE 8:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_PDE_CACHE_MODE_ON 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_PDE_CACHE_MODE_EVICT_SMPG_PARTIALS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_PDE_CACHE_MODE_EVICT_ALL_PARTIALS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_PDE_CACHE_MODE_OFF 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_L2_SEND_MODE 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_L2_SEND_MODE_ONE_PTE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_L2_SEND_MODE_WHOLE_CL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_WORK_CREATION_DISABLE 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_WORK_CREATION_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_WORK_CREATION_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_ATOMIC_CAPABILITY_MODE 25:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_STRONG_BIT_ATOMIC_CYA 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL 0x00501480 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_VM_PG_SIZE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_VM_PG_SIZE_128KB 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_VM_PG_SIZE_64KB 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_COMP_FAULT 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_COMP_FAULT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_COMP_FAULT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_MISS_GRAN 4:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_MISS_GRAN_FULL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_MISS_GRAN_HALF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_MISS_GRAN_QUARTER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_MISS_GRAN_NO_PTE_COMP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_CACHE_MODE 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_CACHE_MODE_ON 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_CACHE_MODE_OFF 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_PDE_CACHE_MODE 8:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_PDE_CACHE_MODE_ON 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_PDE_CACHE_MODE_EVICT_SMPG_PARTIALS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_PDE_CACHE_MODE_EVICT_ALL_PARTIALS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_PDE_CACHE_MODE_OFF 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_L2_SEND_MODE 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_L2_SEND_MODE_ONE_PTE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_L2_SEND_MODE_WHOLE_CL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_WORK_CREATION_DISABLE 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_WORK_CREATION_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_WORK_CREATION_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_USE_PDB_BIG_PAGE_SIZE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_USE_PDB_BIG_PAGE_SIZE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_ATOMIC_CAPABILITY_MODE 25:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_ATOMIC_CAPABILITY_MODE_L2 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_ATOMIC_CAPABILITY_MODE_RMW 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_ATOMIC_CAPABILITY_MODE_POWER 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_STRONG_BIT_ATOMIC_CYA 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_STRONG_BIT_ATOMIC_CYA_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_STRONG_BIT_ATOMIC_CYA_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM 0x00500884 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_00 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_01 0x001 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_02 0x002 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_03 0x003 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_04 0x004 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_05 0x005 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_06 0x006 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_07 0x007 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_08 0x008 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_09 0x009 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_0A 0x00a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_0B 0x00b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_0C 0x00c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_0D 0x00d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_0E 0x00e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_0F 0x00f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_10 0x010 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_11 0x011 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_12 0x012 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_13 0x013 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_14 0x014 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_15 0x015 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_16 0x016 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_17 0x017 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_18 0x018 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_19 0x019 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1A 0x01a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1B 0x01b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1C 0x01c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1D 0x01d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1E 0x01e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1F 0x01f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_20 0x020 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_21 0x021 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_22 0x022 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_23 0x023 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_24 0x024 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_25 0x025 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_26 0x026 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_27 0x027 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_28 0x028 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_29 0x029 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_2A 0x02a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_2B 0x02b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_2C 0x02c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_2D 0x02d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_2E 0x02e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_2F 0x02f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_30 0x030 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_31 0x031 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_32 0x032 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_33 0x033 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_34 0x034 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_35 0x035 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_36 0x036 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_37 0x037 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_38 0x038 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_39 0x039 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_3A 0x03a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_3B 0x03b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_3C 0x03c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_3D 0x03d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_3E 0x03e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_3F 0x03f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_40 0x040 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_41 0x041 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_42 0x042 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_43 0x043 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_44 0x044 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_45 0x045 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_46 0x046 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_47 0x047 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_48 0x048 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_49 0x049 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_4A 0x04a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_4B 0x04b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_4C 0x04c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_4D 0x04d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_4E 0x04e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_4F 0x04f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_50 0x050 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_51 0x051 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_52 0x052 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_53 0x053 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_54 0x054 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_55 0x055 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_56 0x056 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_57 0x057 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_58 0x058 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_59 0x059 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_5A 0x05a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_5B 0x05b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_5C 0x05c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_5D 0x05d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_5E 0x05e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_5F 0x05f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_60 0x060 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_61 0x061 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_62 0x062 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_63 0x063 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_64 0x064 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_65 0x065 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_66 0x066 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_67 0x067 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_68 0x068 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_69 0x069 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_6A 0x06a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_6B 0x06b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_6C 0x06c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_6D 0x06d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_6E 0x06e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_6F 0x06f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_70 0x070 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_71 0x071 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_72 0x072 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_73 0x073 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_74 0x074 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_75 0x075 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_76 0x076 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_77 0x077 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_78 0x078 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_79 0x079 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_7A 0x07a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_7B 0x07b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_7C 0x07c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_7D 0x07d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_7E 0x07e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_7F 0x07f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_80 0x080 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_81 0x081 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_82 0x082 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_83 0x083 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_84 0x084 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_85 0x085 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_86 0x086 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_87 0x087 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_88 0x088 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_89 0x089 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_8A 0x08a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_8B 0x08b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_8C 0x08c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_8D 0x08d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_8E 0x08e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_8F 0x08f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_90 0x090 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_91 0x091 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_92 0x092 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_93 0x093 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_94 0x094 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_95 0x095 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_96 0x096 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_97 0x097 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_98 0x098 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_99 0x099 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_9A 0x09a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_9B 0x09b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_9C 0x09c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_9D 0x09d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_9E 0x09e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_9F 0x09f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_A0 0x0a0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_A1 0x0a1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_A2 0x0a2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_A3 0x0a3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_A4 0x0a4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_A5 0x0a5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_A6 0x0a6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_A7 0x0a7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_A8 0x0a8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_A9 0x0a9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_AA 0x0aa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_AB 0x0ab /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_AC 0x0ac /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_AD 0x0ad /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_AE 0x0ae /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_AF 0x0af /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_B0 0x0b0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_B1 0x0b1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_B2 0x0b2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_B3 0x0b3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_B4 0x0b4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_B5 0x0b5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_B6 0x0b6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_B7 0x0b7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_B8 0x0b8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_B9 0x0b9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_BA 0x0ba /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_BB 0x0bb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_BC 0x0bc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_BD 0x0bd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_BE 0x0be /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_BF 0x0bf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_C0 0x0c0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_C1 0x0c1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_C2 0x0c2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_C3 0x0c3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_C4 0x0c4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_C5 0x0c5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_C6 0x0c6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_C7 0x0c7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_C8 0x0c8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_C9 0x0c9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_CA 0x0ca /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_CB 0x0cb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_CC 0x0cc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_CD 0x0cd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_CE 0x0ce /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_CF 0x0cf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_D0 0x0d0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_D1 0x0d1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_D2 0x0d2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_D3 0x0d3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_D4 0x0d4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_D5 0x0d5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_D6 0x0d6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_D7 0x0d7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_D8 0x0d8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_D9 0x0d9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_DA 0x0da /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_DB 0x0db /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_DC 0x0dc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_DD 0x0dd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_DE 0x0de /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_DF 0x0df /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_E0 0x0e0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_E1 0x0e1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_E2 0x0e2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_E3 0x0e3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_E4 0x0e4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_E5 0x0e5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_E6 0x0e6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_E7 0x0e7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_E8 0x0e8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_E9 0x0e9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_EA 0x0ea /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_EB 0x0eb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_EC 0x0ec /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_ED 0x0ed /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_EE 0x0ee /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_EF 0x0ef /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_F0 0x0f0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_F1 0x0f1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_F2 0x0f2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_F3 0x0f3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_F4 0x0f4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_F5 0x0f5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_F6 0x0f6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_F7 0x0f7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_F8 0x0f8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_F9 0x0f9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_FA 0x0fa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_FB 0x0fb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_FC 0x0fc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_FD 0x0fd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x0fe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x0ff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_100 0x100 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_101 0x101 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_102 0x102 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_103 0x103 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_104 0x104 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_105 0x105 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_106 0x106 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_107 0x107 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_108 0x108 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_109 0x109 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_10A 0x10a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_10B 0x10b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_10C 0x10c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_10D 0x10d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_10E 0x10e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_10F 0x10f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_110 0x110 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_111 0x111 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_112 0x112 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_113 0x113 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_114 0x114 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_115 0x115 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_116 0x116 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_117 0x117 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_118 0x118 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_119 0x119 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_11A 0x11a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_11B 0x11b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_11C 0x11c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_11D 0x11d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_11E 0x11e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_11F 0x11f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_120 0x120 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_121 0x121 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_122 0x122 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_123 0x123 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_124 0x124 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_125 0x125 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_126 0x126 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_127 0x127 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_128 0x128 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_129 0x129 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_12A 0x12a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_12B 0x12b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_12C 0x12c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_12D 0x12d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_12E 0x12e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_12F 0x12f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_130 0x130 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_131 0x131 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_132 0x132 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_133 0x133 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_134 0x134 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_135 0x135 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_136 0x136 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_137 0x137 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_138 0x138 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_139 0x139 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_13A 0x13a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_13B 0x13b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_13C 0x13c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_13D 0x13d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_13E 0x13e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_13F 0x13f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_140 0x140 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_141 0x141 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_142 0x142 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_143 0x143 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_144 0x144 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_145 0x145 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_146 0x146 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_147 0x147 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_148 0x148 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_149 0x149 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_14A 0x14a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_14B 0x14b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_14C 0x14c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_14D 0x14d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_14E 0x14e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_14F 0x14f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_150 0x150 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_151 0x151 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_152 0x152 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_153 0x153 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_154 0x154 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_155 0x155 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_156 0x156 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_157 0x157 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_158 0x158 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_159 0x159 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_15A 0x15a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_15B 0x15b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_15C 0x15c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_15D 0x15d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_15E 0x15e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_15F 0x15f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_160 0x160 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_161 0x161 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_162 0x162 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_163 0x163 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_164 0x164 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_165 0x165 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_166 0x166 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_167 0x167 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_168 0x168 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_169 0x169 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_16A 0x16a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_16B 0x16b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_16C 0x16c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_16D 0x16d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_16E 0x16e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_16F 0x16f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_170 0x170 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_171 0x171 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_172 0x172 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_173 0x173 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_174 0x174 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_175 0x175 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_176 0x176 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_177 0x177 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_178 0x178 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_179 0x179 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_17A 0x17a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_17B 0x17b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_17C 0x17c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_17D 0x17d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_17E 0x17e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_17F 0x17f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_180 0x180 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_181 0x181 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_182 0x182 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_183 0x183 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_184 0x184 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_185 0x185 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_186 0x186 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_187 0x187 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_188 0x188 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_189 0x189 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_18A 0x18a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_18B 0x18b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_18C 0x18c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_18D 0x18d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_18E 0x18e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_18F 0x18f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_190 0x190 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_191 0x191 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_192 0x192 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_193 0x193 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_194 0x194 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_195 0x195 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_196 0x196 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_197 0x197 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_198 0x198 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_199 0x199 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_19A 0x19a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_19B 0x19b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_19C 0x19c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_19D 0x19d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_19E 0x19e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_19F 0x19f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1A0 0x1a0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1A1 0x1a1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1A2 0x1a2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1A3 0x1a3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1A4 0x1a4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1A5 0x1a5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1A6 0x1a6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1A7 0x1a7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1A8 0x1a8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1A9 0x1a9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1AA 0x1aa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1AB 0x1ab /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1AC 0x1ac /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1AD 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1AE 0x1ae /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1AF 0x1af /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1B0 0x1b0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1B1 0x1b1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1B2 0x1b2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1B3 0x1b3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1B4 0x1b4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1B5 0x1b5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1B6 0x1b6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1B7 0x1b7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1B8 0x1b8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1B9 0x1b9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1BA 0x1ba /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1BB 0x1bb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1BC 0x1bc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1BD 0x1bd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1BE 0x1be /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1BF 0x1bf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1C0 0x1c0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1C1 0x1c1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1C2 0x1c2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1C3 0x1c3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1C4 0x1c4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1C5 0x1c5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1C6 0x1c6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1C7 0x1c7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1C8 0x1c8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1C9 0x1c9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1CA 0x1ca /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1CB 0x1cb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1CC 0x1cc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1CD 0x1cd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1CE 0x1ce /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1CF 0x1cf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1D0 0x1d0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1D1 0x1d1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1D2 0x1d2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1D3 0x1d3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1D4 0x1d4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1D5 0x1d5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1D6 0x1d6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1D7 0x1d7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1D8 0x1d8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1D9 0x1d9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1DA 0x1da /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1DB 0x1db /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1DC 0x1dc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1DD 0x1dd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1DE 0x1de /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1DF 0x1df /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1E0 0x1e0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1E1 0x1e1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1E2 0x1e2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1E3 0x1e3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1E4 0x1e4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1E5 0x1e5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1E6 0x1e6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1E7 0x1e7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1E8 0x1e8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1E9 0x1e9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1EA 0x1ea /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1EB 0x1eb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1EC 0x1ec /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1ED 0x1ed /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1EE 0x1ee /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1EF 0x1ef /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1F0 0x1f0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1F1 0x1f1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1F2 0x1f2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1F3 0x1f3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1F4 0x1f4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1F5 0x1f5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1F6 0x1f6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1F7 0x1f7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1F8 0x1f8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1F9 0x1f9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1FA 0x1fa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1FB 0x1fb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1FC 0x1fc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1FD 0x1fd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1FE 0x1fe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_GRP_1FF 0x1ff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1 24:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_00 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_01 0x001 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_02 0x002 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_03 0x003 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_04 0x004 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_05 0x005 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_06 0x006 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_07 0x007 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_08 0x008 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_09 0x009 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_0A 0x00a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_0B 0x00b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_0C 0x00c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_0D 0x00d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_0E 0x00e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_0F 0x00f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_10 0x010 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_11 0x011 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_12 0x012 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_13 0x013 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_14 0x014 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_15 0x015 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_16 0x016 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_17 0x017 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_18 0x018 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_19 0x019 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1A 0x01a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1B 0x01b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1C 0x01c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1D 0x01d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1E 0x01e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1F 0x01f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_20 0x020 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_21 0x021 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_22 0x022 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_23 0x023 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_24 0x024 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_25 0x025 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_26 0x026 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_27 0x027 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_28 0x028 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_29 0x029 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_2A 0x02a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_2B 0x02b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_2C 0x02c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_2D 0x02d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_2E 0x02e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_2F 0x02f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_30 0x030 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_31 0x031 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_32 0x032 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_33 0x033 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_34 0x034 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_35 0x035 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_36 0x036 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_37 0x037 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_38 0x038 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_39 0x039 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_3A 0x03a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_3B 0x03b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_3C 0x03c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_3D 0x03d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_3E 0x03e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_3F 0x03f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_40 0x040 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_41 0x041 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_42 0x042 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_43 0x043 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_44 0x044 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_45 0x045 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_46 0x046 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_47 0x047 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_48 0x048 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_49 0x049 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_4A 0x04a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_4B 0x04b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_4C 0x04c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_4D 0x04d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_4E 0x04e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_4F 0x04f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_50 0x050 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_51 0x051 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_52 0x052 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_53 0x053 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_54 0x054 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_55 0x055 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_56 0x056 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_57 0x057 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_58 0x058 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_59 0x059 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_5A 0x05a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_5B 0x05b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_5C 0x05c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_5D 0x05d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_5E 0x05e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_5F 0x05f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_60 0x060 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_61 0x061 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_62 0x062 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_63 0x063 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_64 0x064 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_65 0x065 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_66 0x066 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_67 0x067 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_68 0x068 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_69 0x069 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_6A 0x06a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_6B 0x06b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_6C 0x06c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_6D 0x06d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_6E 0x06e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_6F 0x06f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_70 0x070 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_71 0x071 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_72 0x072 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_73 0x073 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_74 0x074 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_75 0x075 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_76 0x076 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_77 0x077 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_78 0x078 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_79 0x079 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_7A 0x07a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_7B 0x07b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_7C 0x07c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_7D 0x07d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_7E 0x07e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_7F 0x07f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_80 0x080 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_81 0x081 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_82 0x082 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_83 0x083 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_84 0x084 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_85 0x085 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_86 0x086 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_87 0x087 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_88 0x088 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_89 0x089 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_8A 0x08a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_8B 0x08b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_8C 0x08c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_8D 0x08d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_8E 0x08e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_8F 0x08f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_90 0x090 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_91 0x091 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_92 0x092 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_93 0x093 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_94 0x094 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_95 0x095 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_96 0x096 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_97 0x097 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_98 0x098 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_99 0x099 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_9A 0x09a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_9B 0x09b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_9C 0x09c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_9D 0x09d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_9E 0x09e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_9F 0x09f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_A0 0x0a0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_A1 0x0a1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_A2 0x0a2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_A3 0x0a3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_A4 0x0a4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_A5 0x0a5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_A6 0x0a6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_A7 0x0a7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_A8 0x0a8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_A9 0x0a9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_AA 0x0aa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_AB 0x0ab /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_AC 0x0ac /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_AD 0x0ad /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_AE 0x0ae /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_AF 0x0af /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_B0 0x0b0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_B1 0x0b1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_B2 0x0b2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_B3 0x0b3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_B4 0x0b4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_B5 0x0b5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_B6 0x0b6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_B7 0x0b7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_B8 0x0b8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_B9 0x0b9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_BA 0x0ba /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_BB 0x0bb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_BC 0x0bc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_BD 0x0bd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_BE 0x0be /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_BF 0x0bf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_C0 0x0c0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_C1 0x0c1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_C2 0x0c2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_C3 0x0c3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_C4 0x0c4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_C5 0x0c5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_C6 0x0c6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_C7 0x0c7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_C8 0x0c8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_C9 0x0c9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_CA 0x0ca /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_CB 0x0cb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_CC 0x0cc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_CD 0x0cd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_CE 0x0ce /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_CF 0x0cf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_D0 0x0d0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_D1 0x0d1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_D2 0x0d2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_D3 0x0d3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_D4 0x0d4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_D5 0x0d5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_D6 0x0d6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_D7 0x0d7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_D8 0x0d8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_D9 0x0d9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_DA 0x0da /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_DB 0x0db /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_DC 0x0dc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_DD 0x0dd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_DE 0x0de /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_DF 0x0df /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_E0 0x0e0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_E1 0x0e1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_E2 0x0e2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_E3 0x0e3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_E4 0x0e4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_E5 0x0e5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_E6 0x0e6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_E7 0x0e7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_E8 0x0e8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_E9 0x0e9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_EA 0x0ea /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_EB 0x0eb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_EC 0x0ec /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_ED 0x0ed /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_EE 0x0ee /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_EF 0x0ef /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_F0 0x0f0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_F1 0x0f1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_F2 0x0f2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_F3 0x0f3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_F4 0x0f4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_F5 0x0f5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_F6 0x0f6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_F7 0x0f7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_F8 0x0f8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_F9 0x0f9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_FA 0x0fa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_FB 0x0fb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_FC 0x0fc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_FD 0x0fd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP 0x0fe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP 0x0ff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_100 0x100 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_101 0x101 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_102 0x102 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_103 0x103 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_104 0x104 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_105 0x105 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_106 0x106 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_107 0x107 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_108 0x108 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_109 0x109 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_10A 0x10a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_10B 0x10b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_10C 0x10c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_10D 0x10d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_10E 0x10e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_10F 0x10f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_110 0x110 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_111 0x111 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_112 0x112 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_113 0x113 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_114 0x114 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_115 0x115 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_116 0x116 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_117 0x117 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_118 0x118 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_119 0x119 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_11A 0x11a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_11B 0x11b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_11C 0x11c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_11D 0x11d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_11E 0x11e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_11F 0x11f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_120 0x120 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_121 0x121 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_122 0x122 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_123 0x123 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_124 0x124 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_125 0x125 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_126 0x126 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_127 0x127 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_128 0x128 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_129 0x129 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_12A 0x12a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_12B 0x12b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_12C 0x12c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_12D 0x12d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_12E 0x12e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_12F 0x12f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_130 0x130 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_131 0x131 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_132 0x132 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_133 0x133 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_134 0x134 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_135 0x135 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_136 0x136 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_137 0x137 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_138 0x138 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_139 0x139 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_13A 0x13a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_13B 0x13b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_13C 0x13c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_13D 0x13d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_13E 0x13e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_13F 0x13f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_140 0x140 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_141 0x141 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_142 0x142 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_143 0x143 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_144 0x144 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_145 0x145 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_146 0x146 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_147 0x147 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_148 0x148 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_149 0x149 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_14A 0x14a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_14B 0x14b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_14C 0x14c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_14D 0x14d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_14E 0x14e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_14F 0x14f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_150 0x150 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_151 0x151 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_152 0x152 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_153 0x153 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_154 0x154 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_155 0x155 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_156 0x156 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_157 0x157 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_158 0x158 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_159 0x159 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_15A 0x15a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_15B 0x15b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_15C 0x15c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_15D 0x15d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_15E 0x15e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_15F 0x15f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_160 0x160 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_161 0x161 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_162 0x162 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_163 0x163 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_164 0x164 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_165 0x165 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_166 0x166 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_167 0x167 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_168 0x168 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_169 0x169 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_16A 0x16a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_16B 0x16b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_16C 0x16c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_16D 0x16d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_16E 0x16e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_16F 0x16f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_170 0x170 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_171 0x171 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_172 0x172 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_173 0x173 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_174 0x174 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_175 0x175 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_176 0x176 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_177 0x177 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_178 0x178 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_179 0x179 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_17A 0x17a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_17B 0x17b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_17C 0x17c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_17D 0x17d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_17E 0x17e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_17F 0x17f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_180 0x180 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_181 0x181 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_182 0x182 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_183 0x183 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_184 0x184 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_185 0x185 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_186 0x186 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_187 0x187 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_188 0x188 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_189 0x189 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_18A 0x18a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_18B 0x18b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_18C 0x18c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_18D 0x18d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_18E 0x18e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_18F 0x18f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_190 0x190 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_191 0x191 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_192 0x192 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_193 0x193 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_194 0x194 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_195 0x195 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_196 0x196 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_197 0x197 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_198 0x198 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_199 0x199 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_19A 0x19a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_19B 0x19b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_19C 0x19c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_19D 0x19d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_19E 0x19e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_19F 0x19f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1A0 0x1a0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1A1 0x1a1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1A2 0x1a2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1A3 0x1a3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1A4 0x1a4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1A5 0x1a5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1A6 0x1a6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1A7 0x1a7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1A8 0x1a8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1A9 0x1a9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1AA 0x1aa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1AB 0x1ab /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1AC 0x1ac /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1AD 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1AE 0x1ae /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1AF 0x1af /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1B0 0x1b0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1B1 0x1b1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1B2 0x1b2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1B3 0x1b3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1B4 0x1b4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1B5 0x1b5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1B6 0x1b6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1B7 0x1b7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1B8 0x1b8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1B9 0x1b9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1BA 0x1ba /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1BB 0x1bb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1BC 0x1bc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1BD 0x1bd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1BE 0x1be /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1BF 0x1bf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1C0 0x1c0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1C1 0x1c1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1C2 0x1c2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1C3 0x1c3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1C4 0x1c4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1C5 0x1c5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1C6 0x1c6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1C7 0x1c7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1C8 0x1c8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1C9 0x1c9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1CA 0x1ca /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1CB 0x1cb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1CC 0x1cc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1CD 0x1cd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1CE 0x1ce /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1CF 0x1cf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1D0 0x1d0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1D1 0x1d1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1D2 0x1d2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1D3 0x1d3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1D4 0x1d4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1D5 0x1d5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1D6 0x1d6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1D7 0x1d7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1D8 0x1d8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1D9 0x1d9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1DA 0x1da /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1DB 0x1db /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1DC 0x1dc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1DD 0x1dd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1DE 0x1de /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1DF 0x1df /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1E0 0x1e0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1E1 0x1e1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1E2 0x1e2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1E3 0x1e3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1E4 0x1e4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1E5 0x1e5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1E6 0x1e6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1E7 0x1e7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1E8 0x1e8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1E9 0x1e9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1EA 0x1ea /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1EB 0x1eb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1EC 0x1ec /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1ED 0x1ed /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1EE 0x1ee /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1EF 0x1ef /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1F0 0x1f0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1F1 0x1f1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1F2 0x1f2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1F3 0x1f3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1F4 0x1f4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1F5 0x1f5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1F6 0x1f6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1F7 0x1f7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1F8 0x1f8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1F9 0x1f9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1FA 0x1fa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1FB 0x1fb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1FC 0x1fc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1FD 0x1fd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1FE 0x1fe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_SELECT_MUX1_GRP_1FF 0x1ff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ALT_INPUT 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ALT_INPUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ALT_INPUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ALT_INPUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_BLK_ACT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_BLK_ACT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_BLK_ACT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_BLK_ACT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM 0x00501484 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_00 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_01 0x001 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_02 0x002 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_03 0x003 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_04 0x004 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_05 0x005 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_06 0x006 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_07 0x007 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_08 0x008 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_09 0x009 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_0A 0x00a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_0B 0x00b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_0C 0x00c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_0D 0x00d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_0E 0x00e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_0F 0x00f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_10 0x010 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_11 0x011 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_12 0x012 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_13 0x013 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_14 0x014 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_15 0x015 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_16 0x016 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_17 0x017 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_18 0x018 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_19 0x019 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1A 0x01a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1B 0x01b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1C 0x01c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1D 0x01d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1E 0x01e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1F 0x01f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_20 0x020 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_21 0x021 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_22 0x022 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_23 0x023 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_24 0x024 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_25 0x025 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_26 0x026 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_27 0x027 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_28 0x028 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_29 0x029 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_2A 0x02a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_2B 0x02b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_2C 0x02c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_2D 0x02d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_2E 0x02e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_2F 0x02f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_30 0x030 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_31 0x031 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_32 0x032 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_33 0x033 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_34 0x034 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_35 0x035 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_36 0x036 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_37 0x037 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_38 0x038 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_39 0x039 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_3A 0x03a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_3B 0x03b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_3C 0x03c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_3D 0x03d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_3E 0x03e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_3F 0x03f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_40 0x040 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_41 0x041 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_42 0x042 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_43 0x043 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_44 0x044 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_45 0x045 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_46 0x046 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_47 0x047 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_48 0x048 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_49 0x049 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_4A 0x04a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_4B 0x04b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_4C 0x04c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_4D 0x04d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_4E 0x04e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_4F 0x04f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_50 0x050 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_51 0x051 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_52 0x052 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_53 0x053 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_54 0x054 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_55 0x055 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_56 0x056 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_57 0x057 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_58 0x058 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_59 0x059 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_5A 0x05a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_5B 0x05b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_5C 0x05c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_5D 0x05d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_5E 0x05e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_5F 0x05f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_60 0x060 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_61 0x061 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_62 0x062 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_63 0x063 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_64 0x064 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_65 0x065 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_66 0x066 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_67 0x067 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_68 0x068 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_69 0x069 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_6A 0x06a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_6B 0x06b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_6C 0x06c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_6D 0x06d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_6E 0x06e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_6F 0x06f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_70 0x070 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_71 0x071 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_72 0x072 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_73 0x073 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_74 0x074 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_75 0x075 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_76 0x076 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_77 0x077 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_78 0x078 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_79 0x079 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_7A 0x07a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_7B 0x07b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_7C 0x07c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_7D 0x07d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_7E 0x07e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_7F 0x07f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_80 0x080 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_81 0x081 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_82 0x082 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_83 0x083 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_84 0x084 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_85 0x085 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_86 0x086 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_87 0x087 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_88 0x088 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_89 0x089 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_8A 0x08a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_8B 0x08b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_8C 0x08c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_8D 0x08d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_8E 0x08e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_8F 0x08f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_90 0x090 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_91 0x091 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_92 0x092 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_93 0x093 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_94 0x094 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_95 0x095 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_96 0x096 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_97 0x097 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_98 0x098 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_99 0x099 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_9A 0x09a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_9B 0x09b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_9C 0x09c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_9D 0x09d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_9E 0x09e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_9F 0x09f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_A0 0x0a0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_A1 0x0a1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_A2 0x0a2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_A3 0x0a3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_A4 0x0a4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_A5 0x0a5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_A6 0x0a6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_A7 0x0a7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_A8 0x0a8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_A9 0x0a9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_AA 0x0aa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_AB 0x0ab /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_AC 0x0ac /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_AD 0x0ad /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_AE 0x0ae /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_AF 0x0af /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_B0 0x0b0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_B1 0x0b1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_B2 0x0b2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_B3 0x0b3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_B4 0x0b4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_B5 0x0b5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_B6 0x0b6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_B7 0x0b7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_B8 0x0b8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_B9 0x0b9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_BA 0x0ba /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_BB 0x0bb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_BC 0x0bc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_BD 0x0bd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_BE 0x0be /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_BF 0x0bf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_C0 0x0c0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_C1 0x0c1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_C2 0x0c2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_C3 0x0c3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_C4 0x0c4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_C5 0x0c5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_C6 0x0c6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_C7 0x0c7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_C8 0x0c8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_C9 0x0c9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_CA 0x0ca /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_CB 0x0cb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_CC 0x0cc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_CD 0x0cd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_CE 0x0ce /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_CF 0x0cf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_D0 0x0d0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_D1 0x0d1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_D2 0x0d2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_D3 0x0d3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_D4 0x0d4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_D5 0x0d5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_D6 0x0d6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_D7 0x0d7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_D8 0x0d8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_D9 0x0d9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_DA 0x0da /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_DB 0x0db /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_DC 0x0dc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_DD 0x0dd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_DE 0x0de /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_DF 0x0df /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_E0 0x0e0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_E1 0x0e1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_E2 0x0e2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_E3 0x0e3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_E4 0x0e4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_E5 0x0e5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_E6 0x0e6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_E7 0x0e7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_E8 0x0e8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_E9 0x0e9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_EA 0x0ea /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_EB 0x0eb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_EC 0x0ec /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_ED 0x0ed /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_EE 0x0ee /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_EF 0x0ef /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_F0 0x0f0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_F1 0x0f1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_F2 0x0f2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_F3 0x0f3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_F4 0x0f4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_F5 0x0f5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_F6 0x0f6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_F7 0x0f7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_F8 0x0f8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_F9 0x0f9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_FA 0x0fa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_FB 0x0fb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_FC 0x0fc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_FD 0x0fd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x0fe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x0ff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_100 0x100 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_101 0x101 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_102 0x102 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_103 0x103 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_104 0x104 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_105 0x105 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_106 0x106 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_107 0x107 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_108 0x108 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_109 0x109 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_10A 0x10a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_10B 0x10b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_10C 0x10c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_10D 0x10d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_10E 0x10e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_10F 0x10f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_110 0x110 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_111 0x111 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_112 0x112 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_113 0x113 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_114 0x114 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_115 0x115 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_116 0x116 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_117 0x117 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_118 0x118 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_119 0x119 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_11A 0x11a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_11B 0x11b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_11C 0x11c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_11D 0x11d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_11E 0x11e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_11F 0x11f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_120 0x120 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_121 0x121 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_122 0x122 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_123 0x123 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_124 0x124 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_125 0x125 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_126 0x126 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_127 0x127 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_128 0x128 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_129 0x129 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_12A 0x12a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_12B 0x12b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_12C 0x12c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_12D 0x12d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_12E 0x12e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_12F 0x12f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_130 0x130 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_131 0x131 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_132 0x132 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_133 0x133 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_134 0x134 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_135 0x135 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_136 0x136 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_137 0x137 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_138 0x138 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_139 0x139 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_13A 0x13a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_13B 0x13b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_13C 0x13c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_13D 0x13d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_13E 0x13e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_13F 0x13f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_140 0x140 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_141 0x141 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_142 0x142 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_143 0x143 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_144 0x144 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_145 0x145 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_146 0x146 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_147 0x147 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_148 0x148 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_149 0x149 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_14A 0x14a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_14B 0x14b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_14C 0x14c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_14D 0x14d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_14E 0x14e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_14F 0x14f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_150 0x150 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_151 0x151 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_152 0x152 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_153 0x153 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_154 0x154 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_155 0x155 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_156 0x156 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_157 0x157 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_158 0x158 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_159 0x159 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_15A 0x15a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_15B 0x15b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_15C 0x15c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_15D 0x15d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_15E 0x15e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_15F 0x15f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_160 0x160 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_161 0x161 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_162 0x162 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_163 0x163 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_164 0x164 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_165 0x165 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_166 0x166 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_167 0x167 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_168 0x168 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_169 0x169 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_16A 0x16a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_16B 0x16b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_16C 0x16c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_16D 0x16d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_16E 0x16e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_16F 0x16f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_170 0x170 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_171 0x171 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_172 0x172 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_173 0x173 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_174 0x174 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_175 0x175 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_176 0x176 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_177 0x177 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_178 0x178 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_179 0x179 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_17A 0x17a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_17B 0x17b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_17C 0x17c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_17D 0x17d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_17E 0x17e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_17F 0x17f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_180 0x180 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_181 0x181 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_182 0x182 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_183 0x183 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_184 0x184 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_185 0x185 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_186 0x186 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_187 0x187 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_188 0x188 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_189 0x189 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_18A 0x18a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_18B 0x18b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_18C 0x18c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_18D 0x18d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_18E 0x18e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_18F 0x18f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_190 0x190 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_191 0x191 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_192 0x192 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_193 0x193 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_194 0x194 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_195 0x195 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_196 0x196 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_197 0x197 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_198 0x198 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_199 0x199 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_19A 0x19a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_19B 0x19b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_19C 0x19c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_19D 0x19d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_19E 0x19e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_19F 0x19f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1A0 0x1a0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1A1 0x1a1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1A2 0x1a2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1A3 0x1a3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1A4 0x1a4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1A5 0x1a5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1A6 0x1a6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1A7 0x1a7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1A8 0x1a8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1A9 0x1a9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1AA 0x1aa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1AB 0x1ab /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1AC 0x1ac /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1AD 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1AE 0x1ae /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1AF 0x1af /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1B0 0x1b0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1B1 0x1b1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1B2 0x1b2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1B3 0x1b3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1B4 0x1b4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1B5 0x1b5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1B6 0x1b6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1B7 0x1b7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1B8 0x1b8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1B9 0x1b9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1BA 0x1ba /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1BB 0x1bb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1BC 0x1bc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1BD 0x1bd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1BE 0x1be /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1BF 0x1bf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1C0 0x1c0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1C1 0x1c1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1C2 0x1c2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1C3 0x1c3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1C4 0x1c4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1C5 0x1c5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1C6 0x1c6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1C7 0x1c7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1C8 0x1c8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1C9 0x1c9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1CA 0x1ca /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1CB 0x1cb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1CC 0x1cc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1CD 0x1cd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1CE 0x1ce /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1CF 0x1cf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1D0 0x1d0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1D1 0x1d1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1D2 0x1d2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1D3 0x1d3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1D4 0x1d4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1D5 0x1d5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1D6 0x1d6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1D7 0x1d7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1D8 0x1d8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1D9 0x1d9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1DA 0x1da /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1DB 0x1db /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1DC 0x1dc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1DD 0x1dd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1DE 0x1de /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1DF 0x1df /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1E0 0x1e0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1E1 0x1e1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1E2 0x1e2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1E3 0x1e3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1E4 0x1e4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1E5 0x1e5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1E6 0x1e6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1E7 0x1e7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1E8 0x1e8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1E9 0x1e9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1EA 0x1ea /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1EB 0x1eb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1EC 0x1ec /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1ED 0x1ed /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1EE 0x1ee /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1EF 0x1ef /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1F0 0x1f0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1F1 0x1f1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1F2 0x1f2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1F3 0x1f3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1F4 0x1f4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1F5 0x1f5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1F6 0x1f6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1F7 0x1f7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1F8 0x1f8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1F9 0x1f9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1FA 0x1fa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1FB 0x1fb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1FC 0x1fc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1FD 0x1fd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1FE 0x1fe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_GRP_1FF 0x1ff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1 24:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_00 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_01 0x001 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_02 0x002 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_03 0x003 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_04 0x004 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_05 0x005 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_06 0x006 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_07 0x007 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_08 0x008 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_09 0x009 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_0A 0x00a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_0B 0x00b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_0C 0x00c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_0D 0x00d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_0E 0x00e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_0F 0x00f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_10 0x010 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_11 0x011 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_12 0x012 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_13 0x013 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_14 0x014 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_15 0x015 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_16 0x016 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_17 0x017 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_18 0x018 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_19 0x019 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1A 0x01a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1B 0x01b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1C 0x01c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1D 0x01d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1E 0x01e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1F 0x01f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_20 0x020 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_21 0x021 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_22 0x022 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_23 0x023 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_24 0x024 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_25 0x025 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_26 0x026 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_27 0x027 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_28 0x028 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_29 0x029 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_2A 0x02a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_2B 0x02b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_2C 0x02c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_2D 0x02d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_2E 0x02e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_2F 0x02f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_30 0x030 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_31 0x031 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_32 0x032 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_33 0x033 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_34 0x034 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_35 0x035 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_36 0x036 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_37 0x037 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_38 0x038 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_39 0x039 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_3A 0x03a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_3B 0x03b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_3C 0x03c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_3D 0x03d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_3E 0x03e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_3F 0x03f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_40 0x040 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_41 0x041 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_42 0x042 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_43 0x043 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_44 0x044 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_45 0x045 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_46 0x046 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_47 0x047 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_48 0x048 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_49 0x049 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_4A 0x04a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_4B 0x04b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_4C 0x04c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_4D 0x04d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_4E 0x04e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_4F 0x04f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_50 0x050 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_51 0x051 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_52 0x052 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_53 0x053 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_54 0x054 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_55 0x055 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_56 0x056 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_57 0x057 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_58 0x058 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_59 0x059 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_5A 0x05a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_5B 0x05b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_5C 0x05c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_5D 0x05d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_5E 0x05e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_5F 0x05f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_60 0x060 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_61 0x061 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_62 0x062 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_63 0x063 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_64 0x064 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_65 0x065 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_66 0x066 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_67 0x067 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_68 0x068 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_69 0x069 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_6A 0x06a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_6B 0x06b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_6C 0x06c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_6D 0x06d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_6E 0x06e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_6F 0x06f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_70 0x070 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_71 0x071 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_72 0x072 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_73 0x073 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_74 0x074 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_75 0x075 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_76 0x076 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_77 0x077 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_78 0x078 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_79 0x079 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_7A 0x07a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_7B 0x07b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_7C 0x07c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_7D 0x07d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_7E 0x07e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_7F 0x07f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_80 0x080 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_81 0x081 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_82 0x082 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_83 0x083 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_84 0x084 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_85 0x085 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_86 0x086 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_87 0x087 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_88 0x088 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_89 0x089 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_8A 0x08a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_8B 0x08b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_8C 0x08c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_8D 0x08d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_8E 0x08e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_8F 0x08f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_90 0x090 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_91 0x091 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_92 0x092 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_93 0x093 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_94 0x094 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_95 0x095 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_96 0x096 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_97 0x097 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_98 0x098 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_99 0x099 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_9A 0x09a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_9B 0x09b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_9C 0x09c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_9D 0x09d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_9E 0x09e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_9F 0x09f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_A0 0x0a0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_A1 0x0a1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_A2 0x0a2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_A3 0x0a3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_A4 0x0a4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_A5 0x0a5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_A6 0x0a6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_A7 0x0a7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_A8 0x0a8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_A9 0x0a9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_AA 0x0aa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_AB 0x0ab /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_AC 0x0ac /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_AD 0x0ad /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_AE 0x0ae /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_AF 0x0af /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_B0 0x0b0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_B1 0x0b1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_B2 0x0b2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_B3 0x0b3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_B4 0x0b4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_B5 0x0b5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_B6 0x0b6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_B7 0x0b7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_B8 0x0b8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_B9 0x0b9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_BA 0x0ba /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_BB 0x0bb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_BC 0x0bc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_BD 0x0bd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_BE 0x0be /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_BF 0x0bf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_C0 0x0c0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_C1 0x0c1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_C2 0x0c2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_C3 0x0c3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_C4 0x0c4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_C5 0x0c5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_C6 0x0c6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_C7 0x0c7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_C8 0x0c8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_C9 0x0c9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_CA 0x0ca /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_CB 0x0cb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_CC 0x0cc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_CD 0x0cd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_CE 0x0ce /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_CF 0x0cf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_D0 0x0d0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_D1 0x0d1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_D2 0x0d2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_D3 0x0d3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_D4 0x0d4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_D5 0x0d5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_D6 0x0d6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_D7 0x0d7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_D8 0x0d8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_D9 0x0d9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_DA 0x0da /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_DB 0x0db /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_DC 0x0dc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_DD 0x0dd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_DE 0x0de /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_DF 0x0df /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_E0 0x0e0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_E1 0x0e1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_E2 0x0e2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_E3 0x0e3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_E4 0x0e4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_E5 0x0e5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_E6 0x0e6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_E7 0x0e7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_E8 0x0e8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_E9 0x0e9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_EA 0x0ea /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_EB 0x0eb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_EC 0x0ec /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_ED 0x0ed /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_EE 0x0ee /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_EF 0x0ef /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_F0 0x0f0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_F1 0x0f1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_F2 0x0f2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_F3 0x0f3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_F4 0x0f4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_F5 0x0f5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_F6 0x0f6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_F7 0x0f7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_F8 0x0f8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_F9 0x0f9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_FA 0x0fa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_FB 0x0fb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_FC 0x0fc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_FD 0x0fd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP 0x0fe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP 0x0ff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_100 0x100 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_101 0x101 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_102 0x102 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_103 0x103 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_104 0x104 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_105 0x105 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_106 0x106 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_107 0x107 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_108 0x108 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_109 0x109 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_10A 0x10a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_10B 0x10b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_10C 0x10c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_10D 0x10d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_10E 0x10e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_10F 0x10f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_110 0x110 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_111 0x111 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_112 0x112 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_113 0x113 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_114 0x114 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_115 0x115 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_116 0x116 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_117 0x117 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_118 0x118 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_119 0x119 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_11A 0x11a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_11B 0x11b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_11C 0x11c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_11D 0x11d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_11E 0x11e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_11F 0x11f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_120 0x120 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_121 0x121 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_122 0x122 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_123 0x123 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_124 0x124 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_125 0x125 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_126 0x126 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_127 0x127 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_128 0x128 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_129 0x129 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_12A 0x12a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_12B 0x12b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_12C 0x12c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_12D 0x12d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_12E 0x12e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_12F 0x12f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_130 0x130 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_131 0x131 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_132 0x132 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_133 0x133 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_134 0x134 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_135 0x135 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_136 0x136 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_137 0x137 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_138 0x138 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_139 0x139 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_13A 0x13a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_13B 0x13b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_13C 0x13c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_13D 0x13d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_13E 0x13e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_13F 0x13f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_140 0x140 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_141 0x141 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_142 0x142 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_143 0x143 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_144 0x144 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_145 0x145 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_146 0x146 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_147 0x147 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_148 0x148 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_149 0x149 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_14A 0x14a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_14B 0x14b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_14C 0x14c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_14D 0x14d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_14E 0x14e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_14F 0x14f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_150 0x150 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_151 0x151 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_152 0x152 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_153 0x153 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_154 0x154 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_155 0x155 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_156 0x156 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_157 0x157 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_158 0x158 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_159 0x159 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_15A 0x15a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_15B 0x15b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_15C 0x15c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_15D 0x15d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_15E 0x15e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_15F 0x15f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_160 0x160 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_161 0x161 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_162 0x162 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_163 0x163 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_164 0x164 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_165 0x165 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_166 0x166 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_167 0x167 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_168 0x168 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_169 0x169 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_16A 0x16a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_16B 0x16b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_16C 0x16c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_16D 0x16d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_16E 0x16e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_16F 0x16f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_170 0x170 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_171 0x171 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_172 0x172 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_173 0x173 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_174 0x174 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_175 0x175 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_176 0x176 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_177 0x177 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_178 0x178 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_179 0x179 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_17A 0x17a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_17B 0x17b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_17C 0x17c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_17D 0x17d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_17E 0x17e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_17F 0x17f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_180 0x180 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_181 0x181 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_182 0x182 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_183 0x183 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_184 0x184 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_185 0x185 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_186 0x186 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_187 0x187 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_188 0x188 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_189 0x189 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_18A 0x18a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_18B 0x18b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_18C 0x18c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_18D 0x18d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_18E 0x18e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_18F 0x18f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_190 0x190 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_191 0x191 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_192 0x192 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_193 0x193 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_194 0x194 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_195 0x195 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_196 0x196 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_197 0x197 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_198 0x198 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_199 0x199 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_19A 0x19a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_19B 0x19b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_19C 0x19c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_19D 0x19d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_19E 0x19e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_19F 0x19f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1A0 0x1a0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1A1 0x1a1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1A2 0x1a2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1A3 0x1a3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1A4 0x1a4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1A5 0x1a5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1A6 0x1a6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1A7 0x1a7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1A8 0x1a8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1A9 0x1a9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1AA 0x1aa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1AB 0x1ab /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1AC 0x1ac /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1AD 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1AE 0x1ae /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1AF 0x1af /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1B0 0x1b0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1B1 0x1b1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1B2 0x1b2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1B3 0x1b3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1B4 0x1b4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1B5 0x1b5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1B6 0x1b6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1B7 0x1b7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1B8 0x1b8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1B9 0x1b9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1BA 0x1ba /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1BB 0x1bb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1BC 0x1bc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1BD 0x1bd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1BE 0x1be /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1BF 0x1bf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1C0 0x1c0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1C1 0x1c1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1C2 0x1c2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1C3 0x1c3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1C4 0x1c4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1C5 0x1c5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1C6 0x1c6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1C7 0x1c7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1C8 0x1c8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1C9 0x1c9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1CA 0x1ca /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1CB 0x1cb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1CC 0x1cc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1CD 0x1cd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1CE 0x1ce /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1CF 0x1cf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1D0 0x1d0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1D1 0x1d1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1D2 0x1d2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1D3 0x1d3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1D4 0x1d4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1D5 0x1d5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1D6 0x1d6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1D7 0x1d7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1D8 0x1d8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1D9 0x1d9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1DA 0x1da /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1DB 0x1db /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1DC 0x1dc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1DD 0x1dd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1DE 0x1de /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1DF 0x1df /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1E0 0x1e0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1E1 0x1e1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1E2 0x1e2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1E3 0x1e3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1E4 0x1e4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1E5 0x1e5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1E6 0x1e6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1E7 0x1e7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1E8 0x1e8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1E9 0x1e9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1EA 0x1ea /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1EB 0x1eb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1EC 0x1ec /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1ED 0x1ed /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1EE 0x1ee /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1EF 0x1ef /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1F0 0x1f0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1F1 0x1f1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1F2 0x1f2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1F3 0x1f3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1F4 0x1f4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1F5 0x1f5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1F6 0x1f6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1F7 0x1f7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1F8 0x1f8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1F9 0x1f9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1FA 0x1fa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1FB 0x1fb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1FC 0x1fc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1FD 0x1fd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1FE 0x1fe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_SELECT_MUX1_GRP_1FF 0x1ff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ALT_INPUT 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ALT_INPUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ALT_INPUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ALT_INPUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_BLK_ACT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_BLK_ACT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_BLK_ACT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_BLK_ACT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ADDR_LOW 0x00500888 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ADDR_LOW_ALIGNMENT 0x00000008 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ADDR_LOW_BITS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ADDR_LOW_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ADDR_LOW 0x00501488 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ADDR_LOW_ALIGNMENT 0x00000008 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ADDR_LOW_BITS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ADDR_LOW_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ADDR_HIGH 0x0050088c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ADDR_HIGH_ALIGNMENT 0x00000008 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ADDR_HIGH_BITS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_ADDR_HIGH_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ADDR_HIGH 0x0050148c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ADDR_HIGH_ALIGNMENT 0x00000008 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ADDR_HIGH_BITS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_ADDR_HIGH_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK 0x00500300 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0005c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK 0x00501400 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0005c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK 0x00500358 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0005c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK 0x00501458 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0005c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK 0x0050032c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x8 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK 0x0050142c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x8 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK 0x00500308 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK 0x00501408 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK 0x00500328 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0004c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK 0x00501428 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0004c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CONTROL 0x00500310 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK 0x00500328 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CONTROL 0x00501410 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK 0x00500328 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS 0x00500314 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS 0x00501414 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT 0x00500318 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT 0x00501418 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT 0x0050031c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT 0x0050141c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_ADDRESS 0x00500320 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_ADDRESS 0x00501420 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_GPCMMU_GLOBAL_ESR 0x00500324 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_MMU_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_MMU_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_MMU_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_MMU_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_MMU_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_MMU_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_MMU0_GPCMMU_GLOBAL_ESR 0x00501424 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_MMU0_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL 0x005008a4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_SIZE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_RB_SIZE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_SIZE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_RB_SIZE 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_PROP_SIZE 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_PROP_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_PROP_RB_SIZE 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_PROP_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_SIZE 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_FA_SIZE 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_FA_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_RB_SIZE 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_SET_INDEX_BIG_PG 19:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_SET_INDEX_BIG_PG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_SET_INDEX_SMALL_PG 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_SET_INDEX_SMALL_PG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_FAST_PATH_DISABLE 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_PRF_FAULT_ENABLE 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_PRF_FAULT_ENABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_PRF_FAULT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_FAST_PATH_DISABLE 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_PRF_FAULT_ENABLE 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_PRF_FAULT_ENABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_PRF_FAULT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_PROP_FAST_PATH_DISABLE 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_PROP_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_PROP_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_FAST_PATH_DISABLE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_L1_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_DB_SIZE 29:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_RGG_DB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_DB_SIZE 31:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_CTRL_LTP_DB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL 0x005014a4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_SIZE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_RB_SIZE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_SIZE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_RB_SIZE 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_PROP_SIZE 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_PROP_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_PROP_RB_SIZE 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_PROP_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_SIZE 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_FA_SIZE 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_FA_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_RB_SIZE 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_SET_INDEX_BIG_PG 19:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_SET_INDEX_BIG_PG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_SET_INDEX_SMALL_PG 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_SET_INDEX_SMALL_PG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_FAST_PATH_DISABLE 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_PRF_FAULT_ENABLE 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_PRF_FAULT_ENABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_PRF_FAULT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_FAST_PATH_DISABLE 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_PRF_FAULT_ENABLE 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_PRF_FAULT_ENABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_PRF_FAULT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_PROP_FAST_PATH_DISABLE 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_PROP_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_PROP_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_FAST_PATH_DISABLE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_L1_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_DB_SIZE 29:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_RGG_DB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_DB_SIZE 31:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_CTRL_LTP_DB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_MISC 0x0050037c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_MISC_ROP_SIZE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_MISC_ROP_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_MISC_ROP_RB_SIZE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_MISC_ROP_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_MISC_ROP_DB_SIZE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_MISC_ROP_DB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_MISC 0x0050147c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_MISC_ROP_SIZE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_MISC_ROP_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_MISC_ROP_RB_SIZE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_MISC_ROP_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_MISC_ROP_DB_SIZE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_MISC_ROP_DB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD 0x005008a8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_RGG_UTLB_CL_VC_B 2:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_RGG_UTLB_CL_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_RGG_UTLB_CL_VC_NB 5:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_RGG_UTLB_CL_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_RGG_UTLB_RB_VC_B 8:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_RGG_UTLB_RB_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_RGG_UTLB_RB_VC_NB 11:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_RGG_UTLB_RB_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_LTP_UTLB_CL_VC_B 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_LTP_UTLB_CL_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_LTP_UTLB_CL_VC_NB 17:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_LTP_UTLB_CL_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_LTP_UTLB_RB_VC_B 20:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_LTP_UTLB_RB_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_LTP_UTLB_RB_VC_NB 23:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_LTP_UTLB_RB_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_LTP_UTLB_DB_VC_B 26:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_LTP_UTLB_DB_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_LTP_UTLB_DB_VC_NB 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_LTP_UTLB_DB_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_MEMBAR_RQ_TRACKING 31:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_MEMBAR_RQ_TRACKING_RW 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_MEMBAR_RQ_TRACKING_WRT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_MEMBAR_RQ_TRACKING_SYSMEM 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_RSRVD_MEMBAR_RQ_TRACKING_NONE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD 0x005014a8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_RGG_UTLB_CL_VC_B 2:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_RGG_UTLB_CL_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_RGG_UTLB_CL_VC_NB 5:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_RGG_UTLB_CL_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_RGG_UTLB_RB_VC_B 8:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_RGG_UTLB_RB_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_RGG_UTLB_RB_VC_NB 11:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_RGG_UTLB_RB_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_LTP_UTLB_CL_VC_B 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_LTP_UTLB_CL_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_LTP_UTLB_CL_VC_NB 17:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_LTP_UTLB_CL_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_LTP_UTLB_RB_VC_B 20:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_LTP_UTLB_RB_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_LTP_UTLB_RB_VC_NB 23:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_LTP_UTLB_RB_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_LTP_UTLB_DB_VC_B 26:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_LTP_UTLB_DB_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_LTP_UTLB_DB_VC_NB 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_LTP_UTLB_DB_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_MEMBAR_RQ_TRACKING 31:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_MEMBAR_RQ_TRACKING_RW 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_MEMBAR_RQ_TRACKING_WRT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_MEMBAR_RQ_TRACKING_SYSMEM 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_RSRVD_MEMBAR_RQ_TRACKING_NONE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS 0x005008ac /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_V 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_V_INIT 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_COUNT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_COUNT_INIT 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_HALF_LTC 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_HALF_LTC_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_HALF_LTC_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_HALF_LTC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i) ((i)+16):((i)+16) /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_SLICES_PER_LTC 30:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_NUM_ACTIVE_LTCS_SLICES_PER_LTC_INIT 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS 0x005014ac /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_V 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_V_INIT 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_COUNT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_COUNT_INIT 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_HALF_LTC 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_HALF_LTC_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_HALF_LTC_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_HALF_LTC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i) ((i)+16):((i)+16) /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_SLICES_PER_LTC 30:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_NUM_ACTIVE_LTCS_SLICES_PER_LTC_INIT 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL 0x005008b0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL_WR_KIND 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL_WR_KIND_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL_RD_KIND 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL_RD_KIND_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL_DEBUG 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL_DEBUG_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL_DEBUG_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL_PAGE_SIZE 18:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL_PAGE_SIZE_4KB 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL_PAGE_SIZE_64KB 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL_PAGE_SIZE_128KB 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_CTRL_PAGE_SIZE_1MB 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL 0x005014b0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL_WR_KIND 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL_WR_KIND_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL_RD_KIND 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL_RD_KIND_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL_DEBUG 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL_DEBUG_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL_DEBUG_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL_PAGE_SIZE 18:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL_PAGE_SIZE_4KB 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL_PAGE_SIZE_64KB 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL_PAGE_SIZE_128KB 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_CTRL_PAGE_SIZE_1MB 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_WR 0x005008b4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_WR_APERTURE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_WR_APERTURE_VID_MEM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_WR_APERTURE_PEER_MEM 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_WR_APERTURE_SYS_MEM_C 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_WR_VOL 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_WR_VOL_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_WR_VOL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_WR_ADDR 31:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_WR_ADDR_INIT 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_WR_ADDR_ALIGNMENT 0x000000c /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_WR 0x005014b4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_WR_APERTURE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_WR_APERTURE_VID_MEM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_WR_APERTURE_PEER_MEM 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_WR_APERTURE_SYS_MEM_C 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_WR_APERTURE_SYS_MEM_NC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_WR_VOL 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_WR_VOL_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_WR_VOL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_WR_ADDR 31:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_WR_ADDR_INIT 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_WR_ADDR_ALIGNMENT 0x000000c /* */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_RD 0x005008b8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_RD_APERTURE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_RD_APERTURE_VID_MEM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_RD_APERTURE_PEER_MEM 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_RD_APERTURE_SYS_MEM_C 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_RD_VOL 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_RD_VOL_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_RD_VOL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_RD_ADDR 31:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_RD_ADDR_INIT 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_DEBUG_RD_ADDR_ALIGNMENT 0x000000c /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_RD 0x005014b8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_RD_APERTURE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_RD_APERTURE_VID_MEM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_RD_APERTURE_PEER_MEM 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_RD_APERTURE_SYS_MEM_C 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_RD_APERTURE_SYS_MEM_NC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_RD_VOL 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_RD_VOL_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_RD_VOL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_RD_ADDR 31:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_RD_ADDR_INIT 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_DEBUG_RD_ADDR_ALIGNMENT 0x000000c /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UPPER_ADDR_LOW 0x00500334 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UPPER_ADDR_LOW_BITS 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UPPER_ADDR_LOW_BITS_INIT 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UPPER_ADDR_LOW 0x00501434 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UPPER_ADDR_LOW_BITS 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UPPER_ADDR_LOW_BITS_INIT 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UPPER_ADDR_HIGH 0x00500338 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UPPER_ADDR_HIGH_BITS 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UPPER_ADDR_HIGH_BITS_INIT 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UPPER_ADDR_HIGH 0x00501438 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UPPER_ADDR_HIGH_BITS 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UPPER_ADDR_HIGH_BITS_INIT 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE 0x00500304 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE__PRIV_LEVEL_MASK 0x00500300 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_PROTECTED_MODE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_PROTECTED_MODE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_PROTECTED_MODE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_PROTECTED_MODE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_UPDATE_MODE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_UPDATE_MODE_FALSE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_UPDATE_MODE_TRUE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_UPDATE_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_SECURE_LOCK 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_SECURE_LOCK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_SECURE_LOCK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_VPR_LOCK_MISC 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_VPR_LOCK_MISC_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_VPR_LOCK_MISC_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_VPR_LOCK_HWPM 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_VPR_LOCK_HWPM_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_VPR_LOCK_HWPM_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_VPR_LOCK_SMPC 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_VPR_LOCK_SMPC_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_WPR_WRITE_VPR_LOCK_SMPC_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE 0x00501404 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE__PRIV_LEVEL_MASK 0x00500300 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_PROTECTED_MODE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_PROTECTED_MODE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_PROTECTED_MODE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_PROTECTED_MODE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_UPDATE_MODE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_UPDATE_MODE_FALSE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_UPDATE_MODE_TRUE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_UPDATE_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_SECURE_LOCK 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_SECURE_LOCK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_SECURE_LOCK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_VPR_LOCK_MISC 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_VPR_LOCK_MISC_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_VPR_LOCK_MISC_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_VPR_LOCK_HWPM 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_VPR_LOCK_HWPM_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_VPR_LOCK_HWPM_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_VPR_LOCK_SMPC 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_VPR_LOCK_SMPC_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_WPR_WRITE_VPR_LOCK_SMPC_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE 0x0050035c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE__PRIV_LEVEL_MASK 0x00500358 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PROTECTED_MODE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PROTECTED_MODE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PROTECTED_MODE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VPR_STATE_PROTECTED_MODE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE 0x0050145c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE__PRIV_LEVEL_MASK 0x00500358 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PROTECTED_MODE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PROTECTED_MODE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PROTECTED_MODE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VPR_STATE_PROTECTED_MODE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI 0x00500330 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI__PRIV_LEVEL_MASK 0x0050032c /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_BYPASS_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_BYPASS_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_BYPASS_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_BYPASS_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_DC_EN 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_DC_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_DC_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_DC_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_AC_EN 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_AC_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_AC_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CTRL_DBI_AC_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI 0x00501430 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI__PRIV_LEVEL_MASK 0x0050032c /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_BYPASS_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_BYPASS_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_BYPASS_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_BYPASS_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_DC_EN 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_DC_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_DC_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_DC_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_AC_EN 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_AC_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_AC_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CTRL_DBI_AC_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_BOTTOM 0x00500340 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_BOTTOM_PER_SLICE 19:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_BOTTOM_PER_SLICE_INIT 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_MEM_PARTITION_BOTTOM 0x00501440 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_MEM_PARTITION_BOTTOM_PER_SLICE 19:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_MEM_PARTITION_BOTTOM_PER_SLICE_INIT 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_MIDDLE 0x00500344 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_MIDDLE_PER_SLICE 19:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_INIT 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE 0x01000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE_LG2 0x0000c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_MEM_PARTITION_MIDDLE 0x00501444 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_MEM_PARTITION_MIDDLE_PER_SLICE 19:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_MEM_PARTITION_MIDDLE_PER_SLICE_INIT 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE 0x01000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE_LG2 0x0000c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_BOUNDARY_CFG0 0x00500348 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL 10:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT 0x603 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_MEM_PARTITION_BOUNDARY_CFG0 0x00501448 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_MEM_PARTITION_BOUNDARY_CFG0_VAL 10:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT 0x603 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG 0x0050034c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER(i) ((i)*4+1):((i)*4) /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_INVALID 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB0 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB1 0x2 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_BOTH_HSHUBS 0x3 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_PCIE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER0 1:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER1 5:4 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER2 9:8 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER3 13:12 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER4 17:16 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER5 21:20 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER6 25:24 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER7 29:28 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU_PEER_HSHUB_CONNECTION_CFG_PEER7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG 0x0050144c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER(i) ((i)*4+1):((i)*4) /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_INVALID 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB0 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB1 0x2 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_BOTH_HSHUBS 0x3 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_PCIE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER0 1:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER1 5:4 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER2 9:8 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER3 13:12 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER4 17:16 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER5 21:20 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER6 25:24 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER7 29:28 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_SYSMEM_HSHUB_CONNECTION_CFG 0x00500350 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS 1:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB0 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_BOTH_HSHUBS 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_PCIE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_SYSMEM_HSHUB_CONNECTION_CFG 0x00501450 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS 1:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB0 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_BOTH_HSHUBS 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_PCIE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_GPCMMU_HYPERVISOR_CTL0 0x00500354 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_GPCMMU_HYPERVISOR_CTL0 0x00501454 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT 0x0050033c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_SIZE 3:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_SIZE_INIT 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_GRANULARITY 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_GRANULARITY_INIT 0x5 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_MODE 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_MODE_ACCESS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_MODE_DIRTY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT 0x0050143c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_SIZE 3:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_SIZE_INIT 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_GRANULARITY 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_GRANULARITY_INIT 0x5 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_DISABLE_MODE 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_MODE 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_MODE_ACCESS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_MODE_DIRTY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO 0x00500360 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL 31:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_LO 0x00501460 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL 31:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI 0x00500364 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_HI 0x00501464 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK 0x00500890 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TX_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TX_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TX_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TX_1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TX_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TX_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_PE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_PE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_PE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPCCS 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPCCS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPCCS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_RAST 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_RAST_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_RAST_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_GCC 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_GCC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_GCC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_GPCCS 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_GPCCS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_GPCCS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_PROP 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_PROP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_PROP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_ROP_0 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_ROP_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_ROP_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_ROP_1 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_ROP_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_ROP_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_0 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_1 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_2 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_2_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_3 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_3_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_3_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_4 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_4_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_4_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_5 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_5_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_5_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_6 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_6_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_6_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_7 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_7_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_UNIT_MASK_TPC_7_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK 0x00501490 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TX_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TX_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TX_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TX_1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TX_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TX_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_PE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_PE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_PE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPCCS 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPCCS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPCCS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_RAST 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_RAST_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_RAST_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_GCC 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_GCC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_GCC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_GPCCS 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_GPCCS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_GPCCS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_PROP 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_PROP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_PROP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_ROP_0 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_ROP_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_ROP_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_ROP_1 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_ROP_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_ROP_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_0 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_1 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_2 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_2_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_3 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_3_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_3_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_4 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_4_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_4_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_5 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_5_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_5_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_6 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_6_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_6_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_7 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_7_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_UNIT_MASK_TPC_7_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK 0x00500894 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_RD 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_RD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_RD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_WR 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_WR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_WR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_GATOM 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_GRED 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_GRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_CACHE_MGMT 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_CACHE_MGMT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_CACHE_MGMT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PREFETCH 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PREFETCH_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PREFETCH_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PF1_PREFETCH 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PF1_PREFETCH_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PF1_PREFETCH_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_MEMBAR 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_MEMBAR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_MEMBAR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PHYS_RD 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PHYS_RD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PHYS_RD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PHYS_WR 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PHYS_WR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PHYS_WR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PHYS_GRED 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PHYS_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PHYS_GRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PHYS_GATOM 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PHYS_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PHYS_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PACK_RD 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PACK_RD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PACK_RD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_CONCAT_WR 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_CONCAT_WR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_CONCAT_WR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_CONCAT_GRED 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_CONCAT_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_CONCAT_GRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_CONCAT_GATOM 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_CONCAT_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_CONCAT_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_ALL_CLIENTS 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_ALL_CLIENTS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_ALL_CLIENTS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_ALL_REQUESTS 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_ALL_REQUESTS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_ALL_REQUESTS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_VIDMEM 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_VIDMEM_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_VIDMEM_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PEER 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PEER_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_PEER_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_SYSMEM_C 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_SYSMEM_C_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_SYSMEM_C_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_SYSMEM_NC 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_SYSMEM_NC_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_SYSMEM_NC_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_TYPE 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_TYPE_VIRTUAL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_TYPE_PHYSICAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_EXCLUSIVE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_EXCLUSIVE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PM_REQ_MASK_EXCLUSIVE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK 0x00501494 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_RD 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_RD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_RD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_WR 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_WR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_WR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_GATOM 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_GRED 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_GRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_CACHE_MGMT 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_CACHE_MGMT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_CACHE_MGMT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PREFETCH 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PREFETCH_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PREFETCH_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PF1_PREFETCH 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PF1_PREFETCH_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PF1_PREFETCH_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_MEMBAR 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_MEMBAR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_MEMBAR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PHYS_RD 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PHYS_RD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PHYS_RD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PHYS_WR 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PHYS_WR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PHYS_WR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PHYS_GRED 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PHYS_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PHYS_GRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PHYS_GATOM 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PHYS_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PHYS_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PACK_RD 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PACK_RD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PACK_RD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_CONCAT_WR 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_CONCAT_WR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_CONCAT_WR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_CONCAT_GRED 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_CONCAT_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_CONCAT_GRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_CONCAT_GATOM 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_CONCAT_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_CONCAT_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_ALL_CLIENTS 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_ALL_CLIENTS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_ALL_CLIENTS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_ALL_REQUESTS 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_ALL_REQUESTS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_ALL_REQUESTS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_VIDMEM 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_VIDMEM_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_VIDMEM_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PEER 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PEER_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_PEER_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_SYSMEM_C 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_SYSMEM_C_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_SYSMEM_C_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_SYSMEM_NC 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_SYSMEM_NC_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_SYSMEM_NC_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_TYPE 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_TYPE_VIRTUAL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_TYPE_PHYSICAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_EXCLUSIVE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_EXCLUSIVE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PM_REQ_MASK_EXCLUSIVE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG 0x00500898 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG 0x00501498 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_MMU_CG1 0x0050089c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG1 0x0050149c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG 0x005008a0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_IDLE_BLPG_EN 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_DIS_EARLY_WUP 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_DEEP_ELPG_EN 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_IDLE_ELPG_EN 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_DIDT_DELAY 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_DIDT_DELAY_HWINIT 0xa /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_RESET_DURATION 26:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_RESET_DURATION_HWINIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_CLAMP_DELAY 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_CLAMP_DELAY_HWINIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_ZONE_OFF_MASK 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_SOFT_GATING_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG 0x005014a0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_IDLE_BLPG_EN 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_DIS_EARLY_WUP 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_DEEP_ELPG_EN 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_IDLE_ELPG_EN 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_DIDT_DELAY 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_DIDT_DELAY_HWINIT 0xa /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_RESET_DURATION 26:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_RESET_DURATION_HWINIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_CLAMP_DELAY 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_CLAMP_DELAY_HWINIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_ZONE_OFF_MASK 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_SOFT_GATING_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG1 0x005008bc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU_PG1_ZONE_SEQ 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU_PG1_ZONE_MASK 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU_PG1_ZONE_MASK_HWINIT 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG1 0x005014bc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG1_ZONE_SEQ 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG1_ZONE_MASK 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_MMU0_PG1_ZONE_MASK_HWINIT 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP 0x005005ff:0x00500400 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1 0x00500400 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_FRSTR_3D 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_FRSTR_3D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_FRSTR_3D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_FRSTR_3D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_FRSTR_2D 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_FRSTR_2D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_FRSTR_2D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_FRSTR_2D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_CSB_3D 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_CSB_3D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_CSB_3D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_CSB_3D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_CSB_2D 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_CSB_2D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_CSB_2D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_CSB_2D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SBFILTER 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SBFILTER_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SBFILTER_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SBFILTER_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_FORCE_NO_COMPRESSION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_FORCE_NO_COMPRESSION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_FORCE_NO_COMPRESSION_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_FORCE_NO_COMPRESSION_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_ZCOMPRESS 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_ZCOMPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_ZCOMPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_ZCOMPRESS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_CCOMPRESS 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_CCOMPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_CCOMPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_CCOMPRESS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_BLENDOPT 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_BLENDOPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_BLENDOPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_BLENDOPT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SKIP_ZROP 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SKIP_ZROP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SKIP_ZROP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SKIP_ZROP_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB 18:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB_Z_PRIORITY 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB_C_PRIORITY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB_ROUND_ROBIN 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_TIR_TRUNCATION_REDUCTION_OPT 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_TIR_TRUNCATION_REDUCTION_OPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_TIR_TRUNCATION_REDUCTION_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_TIR_TRUNCATION_REDUCTION_OPT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER 22:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_TIER_1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_TIER_1_2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_TIER_1_2_3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_COLOR_MODULATION_AVOID_NULL_ITER 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_COLOR_MODULATION_AVOID_NULL_ITER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_COLOR_MODULATION_AVOID_NULL_ITER_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_COLOR_MODULATION_AVOID_NULL_ITER_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_TIR_FORCE_EOCP_AT_FRSTR_END 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_TIR_FORCE_EOCP_AT_FRSTR_END_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_TIR_FORCE_EOCP_AT_FRSTR_END_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_TIR_FORCE_EOCP_AT_FRSTR_END_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_ROP_SLICE 26:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_ROP_SLICE_NONE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_ROP_SLICE_ROP0 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_ROP_SLICE_ROP1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_SWALLOW_ROP_SLICE_BOTH 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_KILL_BUNDLES_TO_FS_RDM 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_KILL_BUNDLES_TO_FS_RDM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_KILL_BUNDLES_TO_FS_RDM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_KILL_BUNDLES_TO_FS_RDM_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_ASSUME_FULL_CPIX_FOR_BIN_COUNT 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_ASSUME_FULL_CPIX_FOR_BIN_COUNT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_ASSUME_FULL_CPIX_FOR_BIN_COUNT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_ASSUME_FULL_CPIX_FOR_BIN_COUNT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_VISIBLE_EARLY_Z 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_VISIBLE_EARLY_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_VISIBLE_EARLY_Z_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_VISIBLE_EARLY_Z_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_RDM_DETERMINISM_MODE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_RDM_DETERMINISM_MODE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_RDM_DETERMINISM_MODE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG1_RDM_DETERMINISM_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2 0x00500404 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_PITCH_2D_CHECK 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_PITCH_2D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_PITCH_2D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_PITCH_2D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_PITCH_3D_CHECK 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_PITCH_3D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_PITCH_3D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_PITCH_3D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_WIDTH_3D_ZT_CHECK 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_WIDTH_3D_ZT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_WIDTH_3D_ZT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_WIDTH_3D_ZT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_HEIGHT_3D_ZT_CHECK 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_HEIGHT_3D_ZT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_HEIGHT_3D_ZT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_HEIGHT_3D_ZT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_WIDTH_3D_CT_CHECK 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_WIDTH_3D_CT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_WIDTH_3D_CT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_WIDTH_3D_CT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_HEIGHT_3D_CT_CHECK 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_HEIGHT_3D_CT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_HEIGHT_3D_CT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_HEIGHT_3D_CT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_2D_CHECK 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_2D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_2D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_2D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_3D_ZT_CHECK 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_3D_ZT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_3D_ZT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_3D_ZT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_3D_CT_CHECK 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_3D_CT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_3D_CT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_3D_CT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_MEMLAYOUT_2D_CHECK 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_MEMLAYOUT_2D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_MEMLAYOUT_2D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_MEMLAYOUT_2D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_MEMLAYOUT_3D_CT_CHECK 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_MEMLAYOUT_3D_CT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_MEMLAYOUT_3D_CT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_MEMLAYOUT_3D_CT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_ZBLEND_2D_CHECK 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_ZBLEND_2D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_ZBLEND_2D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_ZBLEND_2D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_ZBLEND_3D_CHECK 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_ZBLEND_3D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_ZBLEND_3D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_ZBLEND_3D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_SYSMEM_2D_CHECK 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_SYSMEM_2D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_SYSMEM_2D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_SYSMEM_2D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_SYSMEM_3D_ZT_CHECK 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_SYSMEM_3D_ZT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_SYSMEM_3D_ZT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_SYSMEM_3D_ZT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_SYSMEM_3D_CT_CHECK 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_SYSMEM_3D_CT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_SYSMEM_3D_CT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_KIND_SYSMEM_3D_CT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_COMPOK_Z_PLANES_THRESHOLD 18:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_COMPOK_Z_PLANES_THRESHOLD_INIT 0x4 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_COMPOK_Z_PLANES_THRESHOLD_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_COMPOK_Z_PLANES_THRESHOLD_NEVER 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_TIR_SSAA_CHECK 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_TIR_SSAA_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_TIR_SSAA_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_TIR_SSAA_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_TIR_ZBUF_CHECK 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_TIR_ZBUF_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_TIR_ZBUF_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_TIR_ZBUF_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_PSI_SSAA_CONF_PIX_CHECK 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_PSI_SSAA_CONF_PIX_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_PSI_SSAA_CONF_PIX_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG2_PSI_SSAA_CONF_PIX_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3 0x00500408 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_ERROR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_ERROR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_INFO 11:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_INFO_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_INFO_SEEN_PIXOUT_EOST_SHADER_COVG 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_INFO_PIXOUT_UPSTREAM_STALL_AT_EOST 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_INFO_PIXOUT_AND_PROP_COVG_EOST_MATCHING 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_INFO_SHADER_COVG_EOST_MATCHING 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_INFO_MRT_EOST_MATCHING 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_INFO_MRT_OVERFLOW 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_INFO_CONSTANT_COLOR_NO_PIXOUT_RETIRE 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_INFO_PIXOUT_EOST_ON_LAST_RENDER_TARGET 0x8 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_CDP_ASSERTION_INFO_UNEXPECTED_PIXOUT_PACKET 0x9 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_MAX_THREADS_IN_C_BINNING_TILE 21:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_MAX_THREADS_IN_C_BINNING_TILE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_MAX_THREADS_IN_Z_BINNING_TILE 29:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_MAX_THREADS_IN_Z_BINNING_TILE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_TIR_PSS_COLOR_ERROR 30:30 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_TIR_PSS_COLOR_ERROR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG3_TIR_PSS_COLOR_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4 0x0050040c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_INIT 0x008 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_2D 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_2D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_2D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_2D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_3D 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_3D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_3D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_3D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE 22:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_INIT 0x001 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_OVERRIDE 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_OVERRIDE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_OVERRIDE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_NEXT_ROP_FOR_BYPASS 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_NEXT_ROP_FOR_BYPASS_ROP0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG4_NEXT_ROP_FOR_BYPASS_ROP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG5 0x00500410 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG5_CSLF_WR_LIMIT 11:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG5_CSLF_WR_LIMIT_INIT 0xfff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG5_ZTLF_WR_LIMIT 28:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG5_ZTLF_WR_LIMIT_INIT 0x1fff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG6 0x00500414 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG6_CZLF_WR_LIMIT 11:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG6_CZLF_WR_LIMIT_INIT 0xfff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG6_ZPASS_WR_LIMIT 27:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG6_ZPASS_WR_LIMIT_INIT 0xfff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG7 0x00500418 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG7_CDP_COVG_WR_LIMIT 12:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG7_CDP_COVG_WR_LIMIT_INIT 0x1fff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG7_PXB_C_WR_LIMIT 26:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG7_PXB_C_WR_LIMIT_INIT 0x7ff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG8 0x0050041c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG8_CBF_WR_LIMIT 10:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG8_CBF_WR_LIMIT_INIT 0x3ff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG8_ZBF_WR_LIMIT 20:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG8_ZBF_WR_LIMIT_INIT 0x1ff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG8_MAX_CPIX_IN_C_BINNING_TILE 31:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_DEBUG8_MAX_CPIX_IN_C_BINNING_TILE_INIT 0x1c0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR 0x00500420 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_PITCH_2D_VIOL 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_PITCH_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_PITCH_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_PITCH_3D_VIOL 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_PITCH_3D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_PITCH_3D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_WIDTH_3D_ZT_VIOL 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_WIDTH_3D_ZT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_WIDTH_3D_ZT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_HEIGHT_3D_ZT_VIOL 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_HEIGHT_3D_ZT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_HEIGHT_3D_ZT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_WIDTH_3D_CT_VIOL 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_WIDTH_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_WIDTH_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_HEIGHT_3D_CT_VIOL 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_HEIGHT_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_HEIGHT_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_2D_VIOL 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_3D_ZT_VIOL 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_3D_ZT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_3D_ZT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_3D_CT_VIOL 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_MEMLAYOUT_2D_VIOL 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_MEMLAYOUT_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_MEMLAYOUT_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_MEMLAYOUT_3D_CT_VIOL 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_MEMLAYOUT_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_MEMLAYOUT_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_ZBLEND_2D_VIOL 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_ZBLEND_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_ZBLEND_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_ZBLEND_3D_VIOL 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_ZBLEND_3D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_ZBLEND_3D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_SYSMEM_2D_VIOL 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_SYSMEM_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_SYSMEM_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_SYSMEM_3D_ZT_VIOL 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_SYSMEM_3D_ZT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_SYSMEM_3D_ZT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_SYSMEM_3D_CT_VIOL 15:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_SYSMEM_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_KIND_SYSMEM_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_TIR_SSAA_VIOL 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_TIR_SSAA_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_TIR_SSAA_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_PSI_SSAA_CONF_PIX_VIOL 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_PSI_SSAA_CONF_PIX_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_PSI_SSAA_CONF_PIX_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_TIR_ZBUF_VIOL 18:18 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_TIR_ZBUF_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_TIR_ZBUF_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_COORD 0x00500434 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_COORD_X 15:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_COORD_X_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_COORD_Y 31:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_COORD_Y_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT 0x00500438 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_DST 6:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_DST_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_CT 14:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_CT_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_ZT 19:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_ZT_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_BLEND_3D 20:20 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_BLEND_3D_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_LOGICOP_3D 21:21 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_LOGICOP_3D_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_AA_SAMPLES 27:24 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_AA_SAMPLES_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_OPERATION_2D 30:28 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_FORMAT_OPERATION_2D_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE 0x0050043c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_PTE_KIND 2:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_PTE_KIND_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_MMU_RESP 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_MMU_RESP_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_APERTURE 21:20 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_APERTURE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_DST_C_TO_Z 22:22 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_DST_C_TO_Z_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_C_TO_Z 23:23 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_C_TO_Z_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_COMPTAG_VLD 24:24 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_COMPTAG_VLD_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_PITCH_ACTIVE 25:25 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE_PITCH_ACTIVE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE2 0x00500440 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE2_LAYER 11:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE2_LAYER_INIT 0x000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE2_CT_TARGET 18:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_STATE2_CT_TARGET_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_OFFSET 0x00500444 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_OFFSET_V 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PROP_HWW_ESR_OFFSET_V_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PROP_PS_INVOCATIONS_LO 0x00500450 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_PS_INVOCATIONS_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_PS_INVOCATIONS_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_PS_INVOCATIONS_HI 0x00500454 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_PS_INVOCATIONS_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_PS_INVOCATIONS_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_CNT_LO 0x00500460 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_CNT_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_CNT_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_CNT_HI 0x00500464 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_CNT_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_CNT_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_CNT_LO 0x0050046c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_CNT_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_CNT_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_CNT_HI 0x00500470 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_CNT_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_CNT_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_0 0x00500480 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_0_MMU_REQ_COUNT 9:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_0_ZLAT_NUM_SUBID_ALLOCATED 20:10 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_0_ZLAT_LAST_SUBID_ACCEPTED_BY_ZSB 31:21 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1 0x00500484 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB 20:18 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI 23:21 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO 29:27 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2 0x00500488 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF 20:18 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT 23:21 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF 29:27 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3 0x0050048c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF 23:21 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ 29:27 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4 0x00500490 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6 0x00500498 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB 20:18 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES 23:21 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT 29:27 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL 0x005004a0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_64 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_65 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_66 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_67 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_68 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_69 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_70 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_71 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_72 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_73 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_74 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_75 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_76 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_77 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_78 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_79 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_80 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_81 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_82 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_83 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_84 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_85 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_86 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_87 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_88 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_89 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_90 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_91 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_92 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_93 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_94 0x5e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_95 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_96 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_97 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_98 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_99 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_100 0x64 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_101 0x65 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_102 0x66 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_103 0x67 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_104 0x68 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_105 0x69 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_106 0x6a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_107 0x6b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_108 0x6c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_109 0x6d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_110 0x6e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_111 0x6f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_112 0x70 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_113 0x71 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_114 0x72 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_115 0x73 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_116 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_117 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_118 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_119 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_120 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_121 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_122 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_123 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_124 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_125 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_126 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_127 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_128 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_129 0x81 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_130 0x82 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_131 0x83 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_132 0x84 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_133 0x85 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_134 0x86 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_135 0x87 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_136 0x88 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_137 0x89 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_138 0x8a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_139 0x8b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_140 0x8c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_141 0x8d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_142 0x8e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_143 0x8f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_144 0x90 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_145 0x91 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_146 0x92 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_147 0x93 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_148 0x94 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_149 0x95 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_150 0x96 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_151 0x97 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_152 0x98 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_153 0x99 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_154 0x9a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_155 0x9b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_156 0x9c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_157 0x9d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_158 0x9e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_159 0x9f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_160 0xa0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_161 0xa1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_162 0xa2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_163 0xa3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_164 0xa4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_165 0xa5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_166 0xa6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_167 0xa7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_168 0xa8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_169 0xa9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_170 0xaa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_171 0xab /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_172 0xac /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_173 0xad /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_174 0xae /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_175 0xaf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_176 0xb0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_177 0xb1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_178 0xb2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_179 0xb3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_180 0xb4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_181 0xb5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_182 0xb6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_183 0xb7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_184 0xb8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_185 0xb9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_186 0xba /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_187 0xbb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_188 0xbc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_189 0xbd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_190 0xbe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_191 0xbf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_192 0xc0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_193 0xc1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_194 0xc2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_195 0xc3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_196 0xc4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_197 0xc5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_198 0xc6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_199 0xc7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_200 0xc8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_201 0xc9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_202 0xca /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_203 0xcb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_204 0xcc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_205 0xcd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_206 0xce /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_207 0xcf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_208 0xd0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_209 0xd1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_210 0xd2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_211 0xd3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_212 0xd4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_213 0xd5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_214 0xd6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_215 0xd7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_216 0xd8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_217 0xd9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_218 0xda /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_219 0xdb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_220 0xdc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_221 0xdd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_222 0xde /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_223 0xdf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_224 0xe0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_225 0xe1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_226 0xe2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_227 0xe3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_228 0xe4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_229 0xe5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_230 0xe6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_231 0xe7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_232 0xe8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_233 0xe9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_234 0xea /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_235 0xeb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_236 0xec /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_237 0xed /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_238 0xee /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_239 0xef /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_240 0xf0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_241 0xf1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_242 0xf2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_243 0xf3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_244 0xf4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_245 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_246 0xf6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_247 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_248 0xf8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_249 0xf9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_250 0xfa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_251 0xfb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_252 0xfc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_GRP_253 0xfd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_STATIC_PATTERN_55_8_GROUP 0xfe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_STATIC_PATTERN_AA_8_GROUP 0xff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_64 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_65 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_66 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_67 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_68 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_69 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_70 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_71 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_72 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_73 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_74 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_75 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_76 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_77 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_78 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_79 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_80 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_81 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_82 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_83 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_84 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_85 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_86 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_87 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_88 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_89 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_90 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_91 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_92 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_93 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_94 0x5e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_95 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_96 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_97 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_98 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_99 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_100 0x64 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_101 0x65 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_102 0x66 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_103 0x67 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_104 0x68 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_105 0x69 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_106 0x6a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_107 0x6b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_108 0x6c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_109 0x6d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_110 0x6e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_111 0x6f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_112 0x70 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_113 0x71 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_114 0x72 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_115 0x73 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_116 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_117 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_118 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_119 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_120 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_121 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_122 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_123 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_124 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_125 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_126 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_127 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_128 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_129 0x81 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_130 0x82 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_131 0x83 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_132 0x84 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_133 0x85 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_134 0x86 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_135 0x87 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_136 0x88 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_137 0x89 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_138 0x8a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_139 0x8b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_140 0x8c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_141 0x8d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_142 0x8e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_143 0x8f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_144 0x90 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_145 0x91 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_146 0x92 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_147 0x93 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_148 0x94 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_149 0x95 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_150 0x96 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_151 0x97 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_152 0x98 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_153 0x99 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_154 0x9a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_155 0x9b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_156 0x9c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_157 0x9d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_158 0x9e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_159 0x9f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_160 0xa0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_161 0xa1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_162 0xa2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_163 0xa3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_164 0xa4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_165 0xa5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_166 0xa6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_167 0xa7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_168 0xa8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_169 0xa9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_170 0xaa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_171 0xab /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_172 0xac /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_173 0xad /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_174 0xae /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_175 0xaf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_176 0xb0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_177 0xb1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_178 0xb2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_179 0xb3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_180 0xb4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_181 0xb5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_182 0xb6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_183 0xb7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_184 0xb8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_185 0xb9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_186 0xba /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_187 0xbb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_188 0xbc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_189 0xbd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_190 0xbe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_191 0xbf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_192 0xc0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_193 0xc1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_194 0xc2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_195 0xc3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_196 0xc4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_197 0xc5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_198 0xc6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_199 0xc7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_200 0xc8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_201 0xc9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_202 0xca /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_203 0xcb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_204 0xcc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_205 0xcd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_206 0xce /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_207 0xcf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_208 0xd0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_209 0xd1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_210 0xd2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_211 0xd3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_212 0xd4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_213 0xd5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_214 0xd6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_215 0xd7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_216 0xd8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_217 0xd9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_218 0xda /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_219 0xdb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_220 0xdc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_221 0xdd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_222 0xde /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_223 0xdf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_224 0xe0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_225 0xe1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_226 0xe2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_227 0xe3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_228 0xe4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_229 0xe5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_230 0xe6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_231 0xe7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_232 0xe8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_233 0xe9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_234 0xea /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_235 0xeb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_236 0xec /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_237 0xed /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_238 0xee /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_239 0xef /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_240 0xf0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_241 0xf1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_242 0xf2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_243 0xf3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_244 0xf4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_245 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_246 0xf6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_247 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_248 0xf8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_249 0xf9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_250 0xfa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_251 0xfb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_252 0xfc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_GRP_253 0xfd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_STATIC_PATTERN_55_8_GROUP 0xfe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_STATIC_PATTERN_AA_8_GROUP 0xff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_PERF_SEL2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_XPG2ZLAT_LAT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_XPG2ZLAT_LAT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_XPG2ZLAT_LAT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_XPG2ZLAT_LAT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_ACCUM_LO 0x005004a4 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_ACCUM_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_ACCUM_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_ACCUM_HI 0x005004a8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_ACCUM_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_ACCUM_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_ACCUM_LO 0x005004ac /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_ACCUM_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_ACCUM_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_ACCUM_HI 0x005004b0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_ACCUM_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_ACCUM_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_INTERVAL_ACCUM_LO 0x005004b8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_INTERVAL_ACCUM_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_INTERVAL_ACCUM_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_INTERVAL_ACCUM_HI 0x005004bc /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_INTERVAL_ACCUM_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_ZPASS_INTERVAL_ACCUM_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_INTERVAL_ACCUM_LO 0x005004c0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_INTERVAL_ACCUM_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_INTERVAL_ACCUM_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_INTERVAL_ACCUM_HI 0x005004c4 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_INTERVAL_ACCUM_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PROP_EZ_ZPASS_INTERVAL_ACCUM_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG 0x00500500 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PROP_CG1 0x00500504 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PROP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG1_SLCG 24:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PROP_CG1_SLCG_ENABLED 0x000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG1_SLCG_DISABLED 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PROP_CG1_SLCG__PROD 0x000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR 0x0050067f:0x00500600 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG 0x00500600 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_OPTIMIZE_4X4 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_OPTIMIZE_4X4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_OPTIMIZE_4X4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_OPTIMIZE_4X4_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PROC_3EDGE_ALIASED 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PROC_3EDGE_ALIASED_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PROC_3EDGE_ALIASED_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PROC_3EDGE_ALIASED_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PROC_2EDGE_ALIASED 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PROC_2EDGE_ALIASED_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PROC_2EDGE_ALIASED_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PROC_2EDGE_ALIASED_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PROC_4EDGE_4X4 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PROC_4EDGE_4X4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PROC_4EDGE_4X4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PROC_4EDGE_4X4_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_POWER_FIXES 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_POWER_FIXES_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_POWER_FIXES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_POWER_FIXES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_USE_REDUCED_PRECISION_EDGE_DATA 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_USE_REDUCED_PRECISION_EDGE_DATA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_USE_REDUCED_PRECISION_EDGE_DATA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_USE_REDUCED_PRECISION_EDGE_DATA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PLACEHOLDER2 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PLACEHOLDER2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PLACEHOLDER2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PLACEHOLDER2_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PLACEHOLDER3 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PLACEHOLDER3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PLACEHOLDER3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PLACEHOLDER3_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_LANA_CLOCKGATE_CONTROL 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_BLKACTIVITY_DISABLE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_ZERO_LOWER_THREE_ZC_BITS 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_ZERO_LOWER_THREE_ZC_BITS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_ZERO_LOWER_THREE_ZC_BITS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_ZERO_LOWER_THREE_ZC_BITS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PLACEHOLDER8 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PLACEHOLDER8_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PLACEHOLDER8_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_PLACEHOLDER8_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_USE_INNER_COVG_AS_OUTER_COVG 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_DEBUG_USE_INNER_COVG_AS_OUTER_COVG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL 0x00500604 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRP0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRPA 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRPB 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRPC 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_GRPD 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_PERF_SEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG 0x00500608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG1 0x0050060c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_FRSTR_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP 0x005006ff:0x00500680 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL 0x00500680 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRP0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRPA 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRPB 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRPC 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_GRPD 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_PERF_SEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG 0x00500684 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_PLACEHOLDER0 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_PLACEHOLDER0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_PLACEHOLDER0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_PLACEHOLDER0_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_PLACEHOLDER1 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_PLACEHOLDER1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_PLACEHOLDER1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_PLACEHOLDER1_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_PLACEHOLDER2 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_PLACEHOLDER2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_PLACEHOLDER2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_PLACEHOLDER2_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_GFXP_DISABLE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_GFXP_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_BLKACTIVITY_DISABLE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_FORCE_STIPPLE_FOR_PSAA_RATE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_FORCE_STIPPLE_FOR_PSAA_RATE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_FORCE_STIPPLE_FOR_PSAA_RATE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_FORCE_STIPPLE_FOR_PSAA_RATE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_MODS_VPRS_BYPASS_FOR_PROP_TESTING 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_MODS_VPRS_BYPASS_FOR_PROP_TESTING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_MODS_VPRS_BYPASS_FOR_PROP_TESTING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_MODS_VPRS_BYPASS_FOR_PROP_TESTING_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_DISABLE_FULLY_COVERED_OPTIMIZATION 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_DEBUG_DISABLE_FULLY_COVERED_OPTIMIZATION_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG 0x00500688 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG1 0x0050068c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG1_SLCG 4:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG1_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG1_SLCG_DISABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WIDCLIP_CG1_SLCG__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC 0x005007ff:0x00500700 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_TC_FLUSH 0x00500700 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TC_FLUSH_CRITERION 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_FLUSH_CRITERION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_FLUSH_CRITERION_END_OF_CBE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_FLUSH_CRITERION_TIMEOUT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_TIMEOUT 0x00500704 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TC_TIMEOUT_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_TIMEOUT_VALUE_INIT 0x00000080 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0 0x00500708 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_LIMIT_COALESCE_BUFFER_SIZE 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_LIMIT_COALESCE_BUFFER_SIZE_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_LIMIT_NUM_OF_TILES 14:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_LIMIT_NUM_OF_TILES_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_FORCE_CONFLICT_DETECTION_TO_VPRS 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_FORCE_CONFLICT_DETECTION_TO_VPRS_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_FORCE_CONFLICT_DETECTION_TO_VPRS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_LIMIT_CBES_ACTIVE 26:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_LIMIT_CBES_ACTIVE_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_FLUSH_ON_VPRS_CHANGE 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_FLUSH_ON_VPRS_CHANGE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_FLUSH_ON_VPRS_CHANGE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_PSI_FORCE_FLUSH_ON_CONFLICT 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_PSI_FORCE_FLUSH_ON_CONFLICT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_BLKACTIVITY_DISABLE 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_RTAI_FLUSH 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_RTAI_FLUSH_ON_OVERRIDE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG0_RTAI_FLUSH_ALWAYS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1 0x0050070c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_LIMIT_TILES_INFLIGHT 10:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_LIMIT_TILES_INFLIGHT_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_SPARE11 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_SPARE11_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_SPARE12 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_SPARE12_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_SPARE13 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_SPARE13_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_SPARE14 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_SPARE14_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_SPARE15 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_SPARE15_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_LIMIT_TRANS_INFLIGHT 28:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_LIMIT_TRANS_INFLIGHT_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_LOCAL_TIMEOUT_OVERRIDE 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_LOCAL_TIMEOUT_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_PSI_LIMIT_TILES_MIN_1 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_PSI_LIMIT_TILES_MIN_1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_PSI_DO_NOT_SPLIT_QUADS 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_DEBUG1_PSI_DO_NOT_SPLIT_QUADS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_TILE_SIZE 0x00500710 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TC_TILE_SIZE_MAX 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TC_TILE_SIZE_MAX_16X16 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TC_TILE_SIZE_MAX_16X8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_TILE_SIZE_MAX_8X8 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL 0x00500714 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRP0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRPA 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRPB 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRPC 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRPD 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRPE 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_GRPF 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_PERF_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_PM_CTRL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TC_CG 0x00500718 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TC_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TC_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TC_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TC_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TC_CG1 0x0050071c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TC_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_CG1_SLCG 9:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TC_CG1_SLCG_ENABLED 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TC_CG1_SLCG_DISABLED 0x1ff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TC_CG1_SLCG__PROD 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB 0x005003ff:0x00500380 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS 0x00500380 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_SETUP 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_SETUP_EVICT_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_SETUP_EVICT_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_SETUP_EVICT_LAST 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_WIDREQ 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_WIDREQ_EVICT_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_WIDREQ_EVICT_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_WIDREQ_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_ZCULL 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_ZCULL_EVICT_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_ZCULL_EVICT_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_ZCULL_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_SWDX 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_SWDX_EVICT_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_SWDX_EVICT_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_LINE_CLASS_SWDX_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL 0x00500384 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRP0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRPA 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRPB 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRPC 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_GRPD 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_PERF_SEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_CG2 0x00500388 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_CG2_SLCG 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_CG2_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_CG2_SLCG_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_RASTERARB_CG2_SLCG__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP 0x0050087f:0x00500800 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG 0x00500800 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_POLY_OFFSET_NAN_IS_ZERO 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_POLY_OFFSET_NAN_IS_ZERO_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_POLY_OFFSET_NAN_IS_ZERO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_POLY_OFFSET_NAN_IS_ZERO_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_POLY_OFFSET_ZERO_X_NAN_IS_ZERO 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_POLY_OFFSET_ZERO_X_NAN_IS_ZERO_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_POLY_OFFSET_ZERO_X_NAN_IS_ZERO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_POLY_OFFSET_ZERO_X_NAN_IS_ZERO_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_DO_NOT_USE_ABS_Z_GAMUT_MAX_FOR_POFFSET 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_DO_NOT_USE_ABS_Z_GAMUT_MAX_FOR_POFFSET_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_DO_NOT_USE_ABS_Z_GAMUT_MAX_FOR_POFFSET_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_DO_NOT_USE_ABS_Z_GAMUT_MAX_FOR_POFFSET_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_Z_GAMUT_THRESHOLD 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_Z_GAMUT_THRESHOLD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_Z_GAMUT_THRESHOLD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_Z_GAMUT_THRESHOLD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LANA_CLOCKGATE_CONTROL 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LANA_CLOCKGATE_CONTROL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LANA_CLOCKGATE_CONTROL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LANA_CLOCKGATE_CONTROL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_BLKACTIVITY_DISABLE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_THRESHOLD 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_THRESHOLD_INIT 0x86 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SETUP_COMPUTES_STIPPLE_PHASE_FOR_LINES 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SETUP_COMPUTES_STIPPLE_PHASE_FOR_LINES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SETUP_COMPUTES_STIPPLE_PHASE_FOR_LINES_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SETUP_COMPUTES_STIPPLE_PHASE_FOR_LINES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SETUP_MS_POINT_BBOX_BLOAT 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SETUP_MS_POINT_BBOX_BLOAT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SETUP_MS_POINT_BBOX_BLOAT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SETUP_MS_POINT_BBOX_BLOAT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_TIGHTEN_ALIASED_TRI_BBOX 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_TIGHTEN_ALIASED_TRI_BBOX_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_TIGHTEN_ALIASED_TRI_BBOX_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_TIGHTEN_ALIASED_TRI_BBOX_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_USE_24_FRACTIONAL_BIT_STIPPLE_PHASE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_USE_24_FRACTIONAL_BIT_STIPPLE_PHASE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_USE_24_FRACTIONAL_BIT_STIPPLE_PHASE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_USE_24_FRACTIONAL_BIT_STIPPLE_PHASE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SPARE0 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SPARE0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SPARE1 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SPARE1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_CONSERVATIVE_RASTER_TIER1_ONLY 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_CONSERVATIVE_RASTER_TIER1_ONLY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_CONSERVATIVE_RASTER_TIER1_ONLY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_CONSERVATIVE_RASTER_TIER1_ONLY_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SPARE6 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SPARE6_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SETUP2PE_EARLY_THROTTLE 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SETUP2PE_EARLY_THROTTLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SETUP2PE_EARLY_THROTTLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SETUP2PE_EARLY_THROTTLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_ALIASED_LINE_BBOX_SHRINK 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_ALIASED_LINE_BBOX_SHRINK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_ALIASED_LINE_BBOX_SHRINK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_ALIASED_LINE_BBOX_SHRINK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_TRI_CORNER_CLIPPING 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_TRI_CORNER_CLIPPING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_TRI_CORNER_CLIPPING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_TRI_CORNER_CLIPPING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_NEAR_FAR_CULLING 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_NEAR_FAR_CULLING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_NEAR_FAR_CULLING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_NEAR_FAR_CULLING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SMOOTH_LINE_BBOX_SHRINK 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SMOOTH_LINE_BBOX_SHRINK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SMOOTH_LINE_BBOX_SHRINK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_SMOOTH_LINE_BBOX_SHRINK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_Z_GAMUT_OFFSET 0x00500830 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_Z_GAMUT_OFFSET_AMOUNT 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_Z_GAMUT_OFFSET_AMOUNT_INIT 0x0000001 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_Z_GAMUT_OFFSET_ZF32_AS_Z16 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_Z_GAMUT_OFFSET_ZF32_AS_Z16_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_Z_GAMUT_OFFSET_ZF32_AS_Z16_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_Z_GAMUT_OFFSET_ZF32_AS_Z16_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2 0x00500808 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_ALIASED_LINE_BBOX_EXPANSION_LEGACY 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_ALIASED_LINE_BBOX_EXPANSION_LEGACY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_ALIASED_LINE_BBOX_EXPANSION_LEGACY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_ALIASED_LINE_BBOX_EXPANSION_LEGACY_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_LATE_Z_FOR_COLOR_CLEARS 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_LATE_Z_FOR_COLOR_CLEARS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_LATE_Z_FOR_COLOR_CLEARS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_LATE_Z_FOR_COLOR_CLEARS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_TIER1_BEHAVIOR_FOR_LINES_AND_POINTS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_TIER1_BEHAVIOR_FOR_LINES_AND_POINTS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_TIER1_BEHAVIOR_FOR_LINES_AND_POINTS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_TIER1_BEHAVIOR_FOR_LINES_AND_POINTS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_TIER4_LINE_BUG_CHANGE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_TIER4_LINE_BUG_CHANGE_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_TIER4_LINE_BUG_CHANGE_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_TIER4_LINE_BUG_CHANGE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_LINE_LENGTH_ZERO_CULL_PATH 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_LINE_LENGTH_ZERO_CULL_PATH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_LINE_LENGTH_ZERO_CULL_PATH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_LINE_LENGTH_ZERO_CULL_PATH_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_FIX_NEGATIVE_ZERO_COMPARE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_FIX_NEGATIVE_ZERO_COMPARE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_FIX_NEGATIVE_ZERO_COMPARE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_FIX_NEGATIVE_ZERO_COMPARE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE6 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE6_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE7 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE7_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE8 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE8_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE9 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE9_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE10 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE10_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE11 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE11_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE12 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE12_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE13 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE13_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE14 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE14_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE15 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG2_SPARE15_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG 0x00500828 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG1 0x0050082c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_RM_ATTRIB_CB_BASE 0x00500810 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 0x000000c /* */ #define NV_PGRAPH_PRI_GPC0_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_RM_ATTRIB_CB_BASE_VALID_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_RM_ATTRIB_CB_BASE_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LIMIT0 0x00500814 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LIMIT0_SWDX2SETUP_VALUE 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LIMIT0_SWDX2SETUP_VALUE_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LIMIT0_TAG_LATENCY_VALUE 26:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LIMIT0_TAG_LATENCY_VALUE_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LIMIT1 0x00500818 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LIMIT1_RRRAM_VALUE 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LIMIT1_RRRAM_VALUE_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LIMIT1_SETUP2PE_VALUE 24:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LIMIT1_SETUP2PE_VALUE_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LIMIT1_PRIM_PTR_MSB_VALUE 31:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_DEBUG_LIMIT1_PRIM_PTR_MSB_VALUE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL 0x0050081c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRP0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRPA 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRPB 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRPC 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRPD 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRPE 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_GRPF 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY3 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY4 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY5 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY6 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE0 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE1 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE2 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE3 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE4 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE5 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE6 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY0 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY1 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY2 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY3 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY4 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY5 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY6 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE0 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE1 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE2 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE3 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE4 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE5 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE6 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_STATIC_PATTERN_15_5_GROUP 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_STATIC_PATTERN_0A_5_GROUP 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_PERF_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR 0x00500824 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_INTR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_INTR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_INTR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_LDCONST_OOB 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_LDCONST_OOB_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_LDCONST_OOB_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_POOLPAGE_INVALID 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_POOLPAGE_INVALID_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_POOLPAGE_INVALID_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_RESET_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_SETUP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR 0x00500bff:0x00500b00 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG 0x00500b00 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_SEARCH 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_SEARCH_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_SEARCH_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_SEARCH_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_BBOXDISC 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_BBOXDISC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_BBOXDISC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_BBOXDISC_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_BBOX2X2OPT 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_BBOX2X2OPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_BBOX2X2OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_BBOX2X2OPT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_BLKACTIVITY_DISABLE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_LANA_CLOCKGATE_CONTROL 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_GFXP_SYNC_DISABLE 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_GFXP_SYNC_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_INNER_COVG 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_INNER_COVG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_INNER_COVG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_INNER_COVG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_POINTS 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_POINTS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_LINES 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_LINES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_TRIS 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_TRIS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_FULLY_COVERED_OPTIMIZATION 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_FULLY_COVERED_OPTIMIZATION_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_VPRS_CACHE 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_VPRS_CACHE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_SEARCH_UPDATES 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_SEARCH_UPDATES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_INDEPENDENT_ENGINES 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_DISABLE_INDEPENDENT_ENGINES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_SAVED 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_DEBUG_SAVED_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL 0x00500b04 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRP0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRPA 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRPB 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRPC 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_GRPD 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_PERF_SEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP(i) (0x00500b08+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP__SIZE_1 43 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP_TILE0 4:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP_TILE0_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP_TILE1 9:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP_TILE1_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP_TILE2 14:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP_TILE2_INIT 0x02 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP_TILE3 19:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP_TILE3_INIT 0x03 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP_TILE4 24:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP_TILE4_INIT 0x04 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP_TILE5 29:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_GPC_MAP_TILE5_INIT 0x05 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_MAP_TABLE_CONFIG 0x00500bb8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET_INIT 0x03 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG 0x00500bbc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG1 0x00500bc0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_HEAVY_BUNDLE_ADDITIONS 0x00500bf0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_CRSTR_HEAVY_BUNDLE_ADDITIONS_ADDRESS_0 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_HEAVY_BUNDLE_ADDITIONS_ADDRESS_0_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_CRSTR_HEAVY_BUNDLE_ADDITIONS_ADDRESS_1 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_CRSTR_HEAVY_BUNDLE_ADDITIONS_ADDRESS_1_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD 0x00500c7f:0x00500c00 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS 0x00500c00 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_MODE_ALPHA 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_MODE_ALPHA_UNPARTITIONED 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_MODE_ALPHA_MIXED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_MODE_BETA 4:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_MODE_BETA_UNPARTITIONED 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_MODE_BETA_MIXED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_ALPHA_FSM 10:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_ALPHA_FSM_WTB 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_ALPHA_FSM_SB 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_ALPHA_FSM_WFP 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_ALPHA_FSM_WFC 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_ALPHA_FSM_SWTB 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_ALPHA_PRIMID_EN 12:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_BETA_FSM 18:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_BETA_FSM_READY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_BETA_FSM_SENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_BETA_FSM_COMPLEX 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_BETA_FSM_NUM_THREADS 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_BETA_FSM_SWTB 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_BETA_FORWARD_BETA 20:20 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS_BETA_SPM_ID 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS2 0x00500c08 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_STATUS2_BATCH_INTERLOCK_COUNT 13:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM 0x00500c04 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP64 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP65 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP66 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP67 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP68 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP69 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP70 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_STATIC_PATTERN_AA_8_GROUP 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_STATIC_PATTERN_55_8_GROUP 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_SELECT_GRP_MAX 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x00500c10+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x00500c30+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_LIVE_PHYSICAL_PES 0x00500c50 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_LIVE_PHYSICAL_PES_MASK 3:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG 0x00500c6c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_GPMPD2PEL_ARB 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_GPMPD2PEL_ARB_AUTO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_GPMPD2PEL_ARB_ROUND_ROBIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_GPMPD2PEL_ARB_ALPHA 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_GPMPD2PEL_ARB_BETA 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_GPMPD2PEL_ARB_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_PD2GPM_SLICE_REDUCE 8:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_PD2GPM_SLICE_REDUCE_FULLSIZE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_PD2GPM_SLICE_REDUCE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_LOAD_BALANCE_LAST_TPC_SELECTION 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_LOAD_BALANCE_LAST_TPC_SELECTION_NO_ACTION 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_LOAD_BALANCE_LAST_TPC_SELECTION_EXCLUDE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_LOAD_BALANCE_LAST_TPC_SELECTION_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM_ROUND_ROBIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM_LOAD_BALANCED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM_ROUND_ROBIN_PES 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_HONOR_PD_DISTRIBUTION 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_HONOR_PD_DISTRIBUTION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_HONOR_PD_DISTRIBUTION_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_HONOR_PD_DISTRIBUTION_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL_AUTO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL_OFF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL_ON 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL 20:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_NO_XTRA_SPACE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_BLOCK_ON_SPACE_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_BLOCK_ON_DRAIN_AND_SPACE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_BLOCK_UNTIL_DRAINS_ACKED 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_NO_BLOCK 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_STRICT_ALPHA_BETA_INTERLOCK 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_STRICT_ALPHA_BETA_INTERLOCK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_STRICT_ALPHA_BETA_INTERLOCK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_STRICT_ALPHA_BETA_INTERLOCK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_DISABLE_INTERLOCK 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_DISABLE_INTERLOCK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_DISABLE_INTERLOCK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_DISABLE_INTERLOCK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_BLOCK_ALPHA_WORK_IN_UNPARTITIONED_TO_ALPHA_TRANSITION 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_BLOCK_ALPHA_WORK_IN_UNPARTITIONED_TO_ALPHA_TRANSITION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_BLOCK_ALPHA_WORK_IN_UNPARTITIONED_TO_ALPHA_TRANSITION_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_BLOCK_ALPHA_WORK_IN_UNPARTITIONED_TO_ALPHA_TRANSITION_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_DISABLE_RTV_PREFETCH 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_DISABLE_RTV_PREFETCH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_DISABLE_RTV_PREFETCH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_DISABLE_RTV_PREFETCH_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_DISABLE_INSTRUCTION_PREFETCH 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_RESERVED 31:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CONFIG_RESERVED_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG 0x00500c70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG1 0x00500c74 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_PD_CG1_SLCG__PROD 0x7fffffc0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD 0x00500cff:0x00500c80 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG 0x00500c80 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DIST_3D 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DIST_3D_LOAD_BASED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DIST_3D_ROUND_ROBIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DIST_3D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DIST_2D 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DIST_2D_LOAD_BASED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DIST_2D_ROUND_ROBIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DIST_2D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_RESERVED0 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_RESERVED0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DISABLE_INSTRUCTION_PREFETCH 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DETERMINISTIC_DIST 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DETERMINISTIC_DIST_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DETERMINISTIC_DIST_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DETERMINISTIC_DIST_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_RESERVED1 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_RESERVED1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_FORCE_TICKET_ZERO 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_FORCE_TICKET_ZERO_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_FORCE_TICKET_ZERO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_FORCE_TICKET_ZERO_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_PROP2X_ALLOW_SAME_TPC 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_PROP2X_ALLOW_SAME_TPC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_PROP2X_ALLOW_SAME_TPC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_PROP2X_ALLOW_SAME_TPC_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_RESERVED2 15:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_RESERVED2_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DIST_THRESHOLD_3D 21:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DIST_THRESHOLD_3D_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_RESERVED3 23:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_RESERVED3_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DIST_THRESHOLD_2D 29:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DIST_THRESHOLD_2D_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DRAIN_GFX_TPC_TWO_PHASE 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DRAIN_GFX_TPC_TWO_PHASE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_DRAIN_GFX_TPC_TWO_PHASE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_RESERVED4 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CONFIG_RESERVED4_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS 0x00500c84 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_LOAD 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM 0x00500c88 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_STATIC_PATTERN_2A_6_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_STATIC_PATTERN_15_6_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_SELECT_MAX 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_COLL 0x00500c90 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_COLL_COLL 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_DIST 0x00500c94 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_DIST_DIST 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_DIST_SOF 6:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_IN 0x00500c98 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_IN_COLL 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_IN_DIST 6:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_IN_PROP2GPM_SUBTL 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_IN_GPMPD2GPMSD_COMPUTE 18:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_OUT 0x00500c9c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_OUT_GPM2GCC_PIX 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_OUT_GPM2PROP_SUBTL 6:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_OUT_GPM2PROP_PIXOUT0 10:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_OUT_GPM2PROP_PIXOUT1 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_OUT_GPM2MPC_PIX 22:20 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_TPC(i) (0x00500ca0+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_TPC__SIZE_1 6 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_TPC_MPC2GPM_SUBTL 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_STATUS_TPC_SMM2GPM_PIXOUT 6:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG 0x00500cf0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG1 0x00500cf4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_SD_CG1_SLCG__PROD 0x7ffffff8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT 0x00500d7f:0x00500d00 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM 0x00500d00 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_SELECT_MAX 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_ALPHA_WRITE_POINTERS 0x00500d04 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_ALPHA_WRITE_POINTERS_P0 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_ALPHA_WRITE_POINTERS_P1 6:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_ALPHA_WRITE_POINTERS_P2 10:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_ALPHA_WRITE_POINTERS_P3 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_ALPHA_WRITE_POINTERS_P4 18:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_ALPHA_WRITE_POINTERS_P5 22:20 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_ALPHA_WRITE_POINTERS_P6 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_ALPHA_WRITE_POINTERS_P7 30:28 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_BETA_WRITE_POINTERS 0x00500d08 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_BETA_WRITE_POINTERS_P0 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_BETA_WRITE_POINTERS_P1 6:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_BETA_WRITE_POINTERS_P2 10:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_BETA_WRITE_POINTERS_P3 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_BETA_WRITE_POINTERS_P4 18:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_BETA_WRITE_POINTERS_P5 22:20 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_BETA_WRITE_POINTERS_P6 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_BETA_WRITE_POINTERS_P7 30:28 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CONFIG 0x00500d0c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CONFIG_RESERVED 31:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CONFIG_RESERVED_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_SCOREBOARD_0 0x00500d10 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_SCOREBOARD_0_S0 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_SCOREBOARD_0_S1 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_SCOREBOARD_1 0x00500d14 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_SCOREBOARD_1_S2 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_SCOREBOARD_1_S3 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_SCOREBOARD_2 0x00500d18 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_SCOREBOARD_2_S4 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_SCOREBOARD_2_S5 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_SCOREBOARD_3 0x00500d1c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_SCOREBOARD_3_S6 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_SCOREBOARD_3_S7 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_STATUS 0x00500d20 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_STATUS_READ_POINTER 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_STATUS_FULL_FLAGS 23:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_STATUS_EMPTY_FLAGS 31:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG 0x00500d70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG1 0x00500d74 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GPM_RPT_CG1_SLCG__PROD 0x7ffffff0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS 0x00500fff:0x00500f00 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG 0x00500f00 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG_ALPHA_NEXTSM_REDUCE_DIV16 4:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG_ALPHA_NEXTSM_REDUCE_DIV16_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG_ALPHA_NEXTSM_REDUCE_DIV16_FULLSIZE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG_BETA_NEXTSM_REDUCE_DIV16 9:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG_BETA_NEXTSM_REDUCE_DIV16_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG_BETA_NEXTSM_REDUCE_DIV16_FULLSIZE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG_TWO_PRIM_XBAR_MESSAGE 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG_TWO_PRIM_XBAR_MESSAGE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG_TWO_PRIM_XBAR_MESSAGE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG_TWO_PRIM_XBAR_MESSAGE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG_RESERVED 15:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CONFIG_RESERVED_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM 0x00500f08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_STATIC_PATTERN_2A_7_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_STATIC_PATTERN_55_7_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_SELECT_MAX 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG 0x00500f0c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG1 0x00500f10 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_WDXPS_CG1_SLCG__PROD 0x7ffffff0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC 0x005013ff:0x00501000 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x00501000 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_L15 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_L15_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_L15_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_INVALIDATE 1:1 /* -WIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_INVALIDATE_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_INVALIDATE_TASK_INIT 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_WORLD_INSTR 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_WORLD_INSTR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_WORLD_INSTR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_WORLD_INSTR_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_NUM_WAYS_DISABLED 5:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_NUM_WAYS_DISABLED_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CONSTANTS_IN_PAGEPOOL_CHANNEL 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CONSTANTS_IN_PAGEPOOL_CHANNEL_NONBLOCKING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CONSTANTS_IN_PAGEPOOL_CHANNEL_BLOCKING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CONSTANTS_NOT_IN_PAGEPOOL_CHANNEL 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CONSTANTS_NOT_IN_PAGEPOOL_CHANNEL_NONBLOCKING 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CONSTANTS_NOT_IN_PAGEPOOL_CHANNEL_BLOCKING 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_VA_CONSTANTS_CHANNEL 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_VA_CONSTANTS_CHANNEL_NONBLOCKING 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_VA_CONSTANTS_CHANNEL_BLOCKING 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_INSTRUCTIONS_CHANNEL 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_INSTRUCTIONS_CHANNEL_NONBLOCKING 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_INSTRUCTIONS_CHANNEL_BLOCKING 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_TSL2_CHANNEL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_TSL2_CHANNEL_NONBLOCKING 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_TSL2_CHANNEL_BLOCKING 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_ARB_DISABLE_HIT0 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_ARB_DISABLE_HIT0_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_ARB_DISABLE_HIT0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_ARB_DISABLE_HIT1 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_ARB_DISABLE_HIT1_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_ARB_DISABLE_HIT1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_ARB_DISABLE_MISS 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_ARB_DISABLE_MISS_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_ARB_DISABLE_MISS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_API 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_API_DX 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_API_OGL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CONSTANTS_IN_RTV_CHANNEL 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CONSTANTS_IN_RTV_CHANNEL_NONBLOCKING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CONSTANTS_IN_RTV_CHANNEL_BLOCKING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_SCREEN_INSTR 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_SCREEN_INSTR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_SCREEN_INSTR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_SCREEN_INSTR_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_WORLD_RTV 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_WORLD_RTV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_WORLD_RTV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_WORLD_RTV_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_PREFETCH_MAX_COUNT_PER_SET 22:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_PREFETCH_MAX_COUNT_PER_SET_INIT 0x4 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_PREFETCH_MAX_TOTAL 28:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_PREFETCH_MAX_TOTAL_INIT 0x20 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CYA_CONST_CL_FETCH 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CYA_CONST_CL_FETCH_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CYA_CONST_CL_FETCH_FULL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CYA_CONST_CL_FETCH_PARTIAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CYA_INVALIDATE_ALL 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CYA_INVALIDATE_ALL_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_CYA_INVALIDATE_ALL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_SCREEN_RTV 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_SCREEN_RTV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_SCREEN_RTV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_GFX_PREFETCH_SCREEN_RTV_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_3 0x00501014 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_3_PREFETCH_ENABLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_3_PREFETCH_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_3_PREFETCH_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_3_PREFETCH_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_3_PREFETCH_OFFSET 3:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_3_PREFETCH_OFFSET_256B 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_3_PREFETCH_OFFSET_768B 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_3_PREFETCH_OFFSET_1792B 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_3_PREFETCH_OFFSET_2816B 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_3_PREFETCH_OFFSET_3840B 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_3_PREFETCH_OFFSET_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_RM_PAGEPOOL_BASE 0x00501004 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_RM_PAGEPOOL_BASE_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_RM_RTV_CB_BASE 0x00501034 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GCC_RM_RTV_CB_BASE_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_RM_RTV_CB_BASE_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_RM_PAGEPOOL 0x00501008 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_GCC_RM_PAGEPOOL_TOTAL_PAGES 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_GCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON 0x0050100c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_OUTPUT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_HITMISS2 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_HITMISS3 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_HITMISS4 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_HITMISS5 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_HITMISS6 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_STATIC_PATTERN_25_6_GROUP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_STATIC_PATTERN_1A_6_GROUP 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_LATENCY 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_MISC1 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_MISC2 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_SM2GCC_INP_REQ 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_OUTSTANDING_MISS_TO_RETURN 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_OUTSTANDING_INSTR_REQ 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_OUTSTANDING_CONST_REQ 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_OUTSTANDING_TEX_REQ 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_GPM2GCC_PIX 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_PIPE_STALL1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_PIPE_STALL2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_OCCUPANCY_MISS_BUFFER 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_INSTR_PREFETCH 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_TEX_INVAL_BUNDLES 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_QMD_PREFETCH 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_L15_HITMISS1 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_L15_HITMISS2 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_L15_HITMISS3 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_L15_HITMISS4 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_L15_GNIC_REQ 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_GCC_PREFETCH 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_PPCAM_HITMISS 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_IN_OUT_REQS 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_INVAL_REQS 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_QMD_CONST_PREFETCH 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_GFX_INST_PREFETCH 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_GFX_CONST_PREFETCH_0 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_GFX_CONST_PREFETCH_1 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_GFX_CONST_PREFETCH_2 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_SELECT_GFX_CONST_PREFETCH_3 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_PERFMON_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR 0x00501028 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR_ECC_CORRECTED 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR_ECC_CORRECTED_NOT_PENDING 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR_ECC_CORRECTED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR_ECC_UNCORRECTED 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR_ECC_UNCORRECTED_NOT_PENDING 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR_ECC_UNCORRECTED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG 0x00501020 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_CG1 0x00501024 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GCC_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_CG1_SLCG__PROD 0xff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK 0x00501040 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CONTROL 0x00501044 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CONTROL__PRIV_LEVEL_MASK 0x00501040 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CONTROL_INJECT_CORRECTED_ERR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CONTROL_INJECT_UNCORRECTED_ERR 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS 0x00501048 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK1_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK1_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK0 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK1 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK1_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK1_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_RESET_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CORRECTED_ERR_COUNT 0x0050104c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_UNCORRECTED_ERR_COUNT 0x00501054 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_ADDRESS 0x00501058 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_GCC_L15_ECC_ADDRESS_INDEX 16:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK 0x00501060 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "gcc_dbg" /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2 0x0050105c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2__PRIV_LEVEL_MASK 0x00501060 /* */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_SPARE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_GCC_DBG_2_SPARE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0 0x00504000 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SELECT 0x00504520 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SELECT_INDEX 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SELECT_INDEX_LANE0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SELECT_INDEX_LANE1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SELECT_INDEX_ALL 0x3f /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SELECT_AUTO_INCREMENT 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SELECT_AUTO_INCREMENT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SELECT_AUTO_INCREMENT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANES 0x00504530 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANES_NUM_CHAINS 5:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN 0x00504534 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE0_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE0_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE1_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE1_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE2_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE2_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE3_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE3_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE4 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE4_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE4_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE5_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE5_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE6_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE6_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE7_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE7_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE8 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE8_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE8_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE9 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE9_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE9_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE10 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE10_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE10_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE11 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE11_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE11_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE12 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE12_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE12_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE13 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE13_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE13_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE14 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE14_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE14_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE15 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE15_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE15_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE16 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE16_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE16_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE17 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE17_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RUN_LANE17_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS 0x00504538 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE0 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE0_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE0_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE1 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE1_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE1_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE2 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE2_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE2_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE3 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE3_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE3_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE4 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE4_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE4_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE5 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE5_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE5_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE6 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE6_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE6_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE7 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE7_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE7_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE8 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE8_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE8_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE9 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE9_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE9_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE10 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE10_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE10_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE11 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE11_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE11_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE12 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE12_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE12_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE13 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE13_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE13_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE14 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE14_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE14_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE15 15:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE15_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE15_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE16 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE16_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE16_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE17 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE17_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_STATUS_LANE17_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK 0x005045d0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_IFF_GPCCS_FECS_GSP_SEC2_FUSE1 0x8007c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CONTROL 0x00504584 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CONTROL__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CONTROL_COMPRESSION 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CONTROL_COMPRESSION_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CONTROL_COMPRESSION_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CONTROL_BLOAT_BUDGET 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CONTROL_BLOAT_BUDGET_0 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CONTROL_COMPRESSION_SETTINGS 27:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CONTROL_COMPRESSION_SETTINGS__0 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SAVE_OFFSET 0x00504588 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SAVE_OFFSET__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SAVE_OFFSET_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SAVE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RESTORE_OFFSET 0x0050458c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RESTORE_OFFSET__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RESTORE_OFFSET_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RESTORE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CURRENT_OFFSET 0x005045ac /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CURRENT_OFFSET_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CURRENT_OFFSET_V_0 0x00000000 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CURRENT_SUBOFFSET 0x005045b0 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CURRENT_SUBOFFSET_V 5:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CURRENT_SUBOFFSET_V_0 0x00 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SIZE 0x00504590 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SIZE__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SIZE_V 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SIZE_V_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_PREFETCH_OFFSET 0x00504594 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_PREFETCH_OFFSET__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_PREFETCH_OFFSET_V 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_PREFETCH_OFFSET_V_10 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SAVED_WORDS 0x005045b4 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SAVED_WORDS__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SAVED_WORDS_V 23:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SAVED_WORDS_V_0 0x000000 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RESTORE_WORDS 0x005045b8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RESTORE_WORDS__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RESTORE_WORDS_V 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_RESTORE_WORDS_V_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_DATA 0x00504598 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_DATA__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_DATA_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_DATA_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_LOC 0x0050459c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_LOC__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_LOC_RAMID 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_LOC_RAMID_V 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_LOC_OFFSET 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_LOC_OFFSET_V 0x000f /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_CFG 0x005045a0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_CFG__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_CFG_DELAY 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_CFG_DELAY_V 0x41 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_CFG_CREDITS 21:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_CFG_CREDITS_V 0x3f /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_CFG_AUTOSEEK 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_CFG_AUTOSEEK_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_CFG_AUTOSEEK_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_RCCLASS 0x005045bc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_RCCLASS__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_RCCLASS_V 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_RCCLASS_V_3 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_RCCLASS_V_WFI 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_RCCLASS_V_GFXP 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS 0x005045a4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD 4:0 /* RW-VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_IDLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SEEK 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_DISCOVER_LENGTH 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SAVE 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RESTORE 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_LOAD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_READ_POP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_WRITE_PUSH 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_ENABLE 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_DISABLE 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_ENABLE 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_DISABLE 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_ENABLE 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_DISABLE 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_OVERRIDE 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_FLUSH 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SUSPEND 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_CURRENT 9:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_CURRENT_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_STATUS_CURRENT_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC 0x005045a8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_IDLE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_SEEK 0x01 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_DISCOVER_LENGTH 0x02 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_SAVE 0x03 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_RESTORE 0x04 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_LOAD 0x05 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_READ_POP 0x06 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_WRITE_PUSH 0x07 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_RAMID_ENABLE 0x08 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_RAMID_DISABLE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_ENABLE 0x0a /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_DISABLE 0x0b /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_CHAIN_ENABLE 0x0c /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_CHAIN_DISABLE 0x0d /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_OVERRIDE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_FLUSH 0x0f /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_SUSPEND 0x10 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CMD_EXEC_CMD_SCRUB 0x11 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_COMPUTED_CHECKSUM 0x005045c4 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_COMPUTED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SAVED_CHECKSUM 0x005045c8 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SAVED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CHECKSUM 0x005045cc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CHECKSUM__PRIV_LEVEL_MASK 0x005045d0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CHECKSUM_CTRL_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CHECKSUM_CTRL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CHECKSUM_STATUS_MATCH 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_RC_LANE_CHECKSUM_STATUS_MISMATCH 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_CG1 0x00504524 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_CG1_SLCG 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_LANE_CTL 0x00504540 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES_V 0x8 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_LANE_CTL_WRR_WEIGHT 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_LANE_CTL_WRR_WEIGHT_V 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_BASE_ADDR 0x00504544 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_BASE_ADDR_F 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_BASE_ADDR_F_V 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_HI_BASE_ADDR 0x00504578 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_HI_BASE_ADDR_F 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_HI_BASE_ADDR_F_V 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_ENGINE_CTL 0x0050457c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_ENGINE_CTL_ENGINE_ID 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_ENGINE_CTL_ENGINE_ID_VEID0 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_ENGINE_CTL_ENGINE_ID_BAR2_FN0 0xc0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_ENGINE_CTL_VEID 21:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_ENGINE_CTL_VEID_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_ENGINE_CTL_GFID 29:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_ENGINE_CTL_GFID_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK 0x00504568 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD 0x00504550 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD__PRIV_LEVEL_MASK 0x00504568 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_IDLE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_FB_OP_FLUSH 0x05 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_FB_OP_SOFT_FLUSH 0x06 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_FB_OP_BIND_INST_BLK_PTR 0x07 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_FB_OP_MMU_TLB_INVALIDATE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_PREFETCH 0x0a /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_FB_OP_PHYSICAL_L2_CACHE_MGMT 0x0b /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_CACHE_MGMT 0x0c /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_FB_OP_L2_PEER_INVALIDATE 0x0d /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_FB_OP_L2_SYSMEM_INVALIDATE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_CLEAN_COMPTAGS 0x0f /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_FLUSH_DIRTY 0x10 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_CMD_MEMBAR 0x01 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_SUB_OP 8:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_SUB_OP_INVALIDATE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_SUB_OP_CLEAN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_SUB_OP_DEMOTE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_ACK 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_ACK_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_ACK_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_ACK_TLB 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_ACK_MEM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_ACK_NONE_REQUIRED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_ACK_GLOBALLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_ACK_INTRANODE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_HALT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_HALT_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_HALT_REQUEST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_UNHALT 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_UNHALT_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CTX_CMD_UNHALT_REQUEST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_L2_EVICTION_CTL 0x00504554 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_L2_EVICTION_CTL_WR 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_L2_EVICTION_CTL_WR_FIRST 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_L2_EVICTION_CTL_WR_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_L2_EVICTION_CTL_WR_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_L2_EVICTION_CTL_RD 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_L2_EVICTION_CTL_RD_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_L2_EVICTION_CTL_RD_NORMAL 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_L2_EVICTION_CTL_RD_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_PRIV 0x00504558 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_PRIV_OVERRIDE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_PRIV_OVERRIDE_PRIV 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_PRIV_OVERRIDE_NONPRIV 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS 0x0050455c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_CLEAR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_CLEAR_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_CLEAR_CLEAR 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_ACK 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_ACK_OK 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_ACK_NACK 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_SUBID 15:2 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_OUTSTANDING_TRANSACTIONS 23:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_BUFFER_NOT_EMPTY 24:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_FLUSH_WHEN_BUSY 28:28 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_FLUSH_WHEN_BUSY_DEFAULT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_FLUSH_WHEN_BUSY_ERROR 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_HALTED 30:30 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_STATUS_BUSY 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CMD_OVERRIDE 0x00504560 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CMD_OVERRIDE_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CMD_OVERRIDE_CMD_VIRTUAL 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_VID_MEM 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_NONCOHERENT 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_COHERENT 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CMD_OVERRIDE_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CMD_OVERRIDE_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_CMD_OVERRIDE_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR 0x0050456c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR__PRIV_LEVEL_MASK 0x00504568 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_RC_ID 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_RC_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_RC_SECURE_LEVEL 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_RC_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PVS_ID 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PVS_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PVS_SECURE_LEVEL 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_PVS_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_CMD_ID 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_CMD_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_CMD_SECURE_LEVEL 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_CMD_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_BLOCKED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_ALLOWED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK 0x00504570 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG 0x00504574 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG__PRIV_LEVEL_MASK 0x00504570 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T0 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T1 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T2 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T3 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T4 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T5 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T6 27:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T7 31:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_ARB_FALCON_REGIONCFG_T7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x00504500 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_PE 2:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_PE_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_PE_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_PE_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_PE_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_PE_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_PE_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_PE_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_PE_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_MPC 5:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_MPC_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_MPC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_MPC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_MPC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_MPC_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_MPC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_MPC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_MPC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_SM 8:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_SM_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_SM_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_SM_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_SM_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_SM_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_SM_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_SM_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0_SM_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x00504508 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_PE 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_PE_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_PE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_MPC 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_MPC_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_MPC_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x0050450c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_PE 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_PE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_PE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_MPC 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_MPC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_MPC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_DEBUG 0x00504510 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_DEBUG_STATUS_FILTER 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_DEBUG_STATUS_FILTER_INIT 0x14 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_DEBUG_STATUS_FILTER_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00504100 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLKCG_CG 0x00504004 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLKCG_CG__PRIV_LEVEL_MASK 0x00504100 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLKCG_CG_BLKACTIVITY_ENABLE 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLKCG_CG_BLKACTIVITY_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLKCG_CG_BLKACTIVITY_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLKCG_CG_BLKACTIVITY_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLKCG_CG_BLKACTIVITY_ERR 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLKCG_CG_BLKACTIVITY_ERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLKCG_CG_BLKACTIVITY_ERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLKCG_CG_BLKACTIVITY_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG 0x00504010 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_DEBUG_SPARE_3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF 0x0050400c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_PHASE_ARB_DETERM 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_PHASE_ARB_DETERM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_PHASE_ARB_DETERM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_PHASE_ARB_DETERM_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_CACHE_INVAL_METHOD_EN 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_CACHE_INVAL_METHOD_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_CACHE_INVAL_METHOD_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_CACHE_INVAL_METHOD_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_DEBUG_SPARE_2 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_DEBUG_SPARE_2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_DEBUG_SPARE_2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_DEBUG_SPARE_2_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_INVAL_DISABLE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_INVAL_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_INVAL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_INVAL_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_FAST_MODE_SWITCH 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_FAST_MODE_SWITCH_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_FAST_MODE_SWITCH_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_FAST_MODE_SWITCH_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_CPI_FORCE_PER_TASK_CACHE_INVAL 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_CPI_FORCE_PER_TASK_CACHE_INVAL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_CPI_FORCE_PER_TASK_CACHE_INVAL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_CPI_FORCE_PER_TASK_CACHE_INVAL_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_WRACK_DISABLE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_WRACK_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_WRACK_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_WRACK_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_CPI_VC_IN_CPO_OPT_MODE 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_CPI_VC_IN_CPO_OPT_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_CPI_VC_IN_CPO_OPT_MODE_IS_BLOCKING 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_VAF_CPI_VC_IN_CPO_OPT_MODE_IS_NON_BLOCKING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_XBAR_PORT_ID 0x00504044 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_XBAR_PORT_ID_VALUE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_XBAR_PORT_ID_VALUE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW 0x00504038 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW_READ_PACKING 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW_READ_PACKING_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW_READ_PACKING_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW_READ_PACKING_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW_WRITE_PACKING 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW_WRITE_PACKING_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW_WRITE_PACKING_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW_WRITE_PACKING_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW_READ_CMD_HOLDOFF 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW_READ_CMD_HOLDOFF_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW_ACACHE_READ_CMD_HOLDOFF 7:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_MIW_ACACHE_READ_CMD_HOLDOFF_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE 0x0050404c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_VAF_LINES 11:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_STRI_LINES 23:12 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_GPULL_LINES 24:24 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_CACHE_DISABLE 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_CACHE_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_CACHE_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_CACHE_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_VAF_INVAL_DISABLE 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_VAF_INVAL_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_VAF_INVAL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_VAF_INVAL_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_STRI_INVAL_DISABLE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_STRI_INVAL_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_STRI_INVAL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_ACACHE_STRI_INVAL_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI 0x00504050 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI_LRU_DISABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI_LRU_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI_LRU_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI_LRU_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI_INVAL_DISABLE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI_INVAL_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI_INVAL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI_INVAL_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI_LRU_KEEP_HIST_ENABLE 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI_LRU_KEEP_HIST_ENABLE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI_LRU_KEEP_HIST_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STRI_LRU_KEEP_HIST_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM 0x00504054 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STATUS 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STATUS_ACACHE 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STATUS_PIF 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STATUS_PIN 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STATUS_STRI 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STATUS_TG 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STATUS_VAF 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STATUS_VSC 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CG_STATUS_ACACHE 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CG_STATUS_PIF 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CG_STATUS_PIN 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CG_STATUS_STRI 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CG_STATUS_TG 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CG_STATUS_VAF 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CG_STATUS_VSC 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CG_STATUS 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_BLK_ACTIVITY 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_WAKEUP 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_ACACHE_GRP_0 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_ACACHE_GRP_1 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_ACACHE_GRP_2 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_ACACHE_GRP_3 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_ACACHE_GRP_4 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CPO_GRP_0 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CPO_GRP_1 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_PIF_GRP_0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_PIF_GRP_1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_PIF_GRP_2 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_PIN_GRP_0 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_PIN_GRP_1 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_SSYNC_GRP_0 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STREAM_GRP_0 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STREAM_GRP_1 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STREAM_GRP_2 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STREAM_GRP_3 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STRI_GRP_0 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_0 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_1 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_2 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_3 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_4 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_5 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_6 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_7 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_9 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_10 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_11 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_12 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_TG_GRP_13 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_0 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_1 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_2 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_3 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_4 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_5 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_6 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_7 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_8 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VPC_GRP_0 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VPC_GRP_1 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VPC_GRP_2 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VPC_GRP_3 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VPC_GRP_4 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VPC_GRP_5 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VPC_GRP_6 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VPC_GRP_7 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VPC_GRP_8 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_PVLDRDY1 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_PVLDRDY2 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_PVLDRDY3 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_PVLDRDY4 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VALID1 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VALID2 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VALID3 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_PVLDRDY5 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_PVLDRDY6 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VPC_GRP_9 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VPC_GRP_10 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VPC_GRP_11 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_PG_STATUS 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STRI_GRP_1 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_9 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_11 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_12 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_14 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_15 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_16 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_17 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_18 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_19 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_20 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_VAF_GRP_22 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STRI_GRP_2 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_BA_GRP_1 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STATIC_PATTERN_AAA_12_GROUP 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_STATIC_PATTERN_555_12_GROUP 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_SINGLE_PASS_GRP_1 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_GPCID_PEID_GROUP 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CTL_EN 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CTL_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CTL_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PM_SELECT_CTL_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CACHE_INVALIDATE 0x00504058 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CACHE_INVALIDATE_ENABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CACHE_INVALIDATE_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CACHE_INVALIDATE_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CACHE_INVALIDATE_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS 0x00504060 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_PE 2:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_PE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_PIF 5:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_PIF_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_PIN 8:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_PIN_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_VAF 11:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_VAF_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_ACACHE 14:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_ACACHE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_STRI 17:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_STRI_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_TGA 20:18 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_TGA_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_GSPILL 23:21 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_GSPILL_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_GPULL 26:24 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_GPULL_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_VSC 29:27 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_STATUS_VSC_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_CB_GLOBAL_BASE_ADDR 0x00504048 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_CB_GLOBAL_BASE_ADDR_V_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY 0x00504064 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_CPI 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_CPI_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_CPI_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_CPI_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_CPI_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_STRI 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_STRI_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_STRI_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_STRI_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_STRI_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_VPC 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_VPC_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_VPC_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_VPC_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_VPC_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_STREAM 11:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_STREAM_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_STREAM_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_STREAM_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_L2_EVICT_POLICY_STREAM_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG 0x00504068 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG1 0x0050406c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG1_SLCG 23:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG1_SLCG_ENABLED 0x000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG1_SLCG_DISABLED 0x7fffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_CG1_SLCG__PROD 0x000082 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR 0x00504084 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_PIF_ERR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_PIF_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_PIF_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_PIN_ERR 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_PIN_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_PIN_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_VAF_ERR 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_VAF_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_VAF_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_ACACHE_ERR 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_ACACHE_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_ACACHE_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_STRI_ERR 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_STRI_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_STRI_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_TG_ERR 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_TG_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_TG_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_GSPILL_ERR 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_GSPILL_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_GSPILL_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_GPULL_ERR 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_GPULL_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_GPULL_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_VSC_ERR 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_VSC_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_VSC_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_RESET_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_RESET_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_HWW_ESR_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_A 0x00504094 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_A__PRIV_LEVEL_MASK 0x00504100 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_A_1 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_A_1_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_A_2 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_A_2_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_A_3 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_A_3_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_B 0x00504098 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_B__PRIV_LEVEL_MASK 0x00504100 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_B_4 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_B_4_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_B_5 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_B_5_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_B_6 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_B_6_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_C 0x0050409c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_C__PRIV_LEVEL_MASK 0x00504100 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_C_7 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_C_7_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_C_8 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_C_8_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_C_9 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_PE_BLK_ACTIVITY_WEIGHTS_C_9_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00504300 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL 0x00504304 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_STATUS 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_ACTIVE_WARPS 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_ACTIVE_WARPS2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_RFA_WARP_CANT_DRAIN_OUT_OF_ORDER 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_RFA_WARP_CANT_DRAIN 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_ICC 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_ACTIVE_CTAS 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_TRAP 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_SHADER_PROGRAM 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_SFE_DEBUG0 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_PROFILER 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_STATIC_PATTERN0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_STATIC_PATTERN1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_SIGDUMP_DEBUG 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG_ACTIVE_WARPS_FULL 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG_ACTIVE_WARPS_PS_FULL 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG_ACTIVE_WARPS_VTG_FULL 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_CILP_DEBUG 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG1 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG2 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG3 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG4 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG5 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG6 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG7 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG8 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG9 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_DEBUG10 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_SINGLE_PASS0 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_SINGLE_PASS1 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_SINGLE_PASS2 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_SINGLE_PASS3 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_FULL0 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_NMEAS 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_SINGLE_PASS4 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_SINGLE_PASS5 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_APM_GROUP_5 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_APM_GROUP_4 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_APM_GROUP_3 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_APM_GROUP_2 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_APM_GROUP_1 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_APM_GROUP_0 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_ENABLE 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_CORE_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL 14:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_STATUS_ACTIVITY 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_STATUS_ACTIVITY1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_ACTIVE_WARPS 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_INST_ISSUE_EXECUTED_IPC 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_REGISTER_BANK_UTIL 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_1 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_2 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_3 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_4 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_5 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_6 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_7 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_USCH_1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_USCH_2 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_USCH_3 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_1 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_2 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_3 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_4 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_5 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_6 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_7 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_8 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_9 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_THREAD_INST_EXECUTED 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_IMC 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_TEX 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_PMTRIG 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_THREADS_LAUNCHED 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_LSU_WB_OPS 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_CANT_DISPATCH 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_TEX_PENDING 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_MIO_0 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_BRU 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_REGISTER_READ 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_REGISTER_READ_PART1 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_REGISTER_READ_PART2 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_UNWEIGHTED_SCH_CANT_ISSUE_1 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_UNWEIGHTED_SCH_CANT_ISSUE_2 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_IFB 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_TEX_WB_INST_PENDING_HIST 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG0 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG1 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG2 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG3 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG4 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG5 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG6 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG7 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG8 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG9 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG10 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG11 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG12 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG13 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_DEBUG0 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_BRU_DEBUG0 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_UNIFORM_DATA_DETECT 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DATA_ACTIVITY0 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DATA_ACTIVITY1 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_LRF_READ_0 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_LRF_READ_1 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_WARP_OFF_DECK_REASON 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_THREAD_OCCUPANCY0 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_THREAD_OCCUPANCY1 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_THREAD_OCCUPANCY2 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_STATIC_PATTERN0 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_STATIC_PATTERN1 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_POWER_THROTTLE 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_IDE_SLEEPER 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_BLOCK_ACTIVITY 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_BLOCK_ACTIVITY1 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_BLOCK_ACTIVITY2 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_SINGLE_PASS0 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_10 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_11 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_12 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_13 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_14 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_15 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_APM_GROUP_11 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_APM_GROUP_10 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_APM_GROUP_9 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_APM_GROUP_8 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_APM_GROUP_7 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_APM_GROUP_6 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_APM_GROUP_5 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_APM_GROUP_4 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_APM_GROUP_3 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_APM_GROUP_2 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_APM_GROUP_1 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_APM_GROUP_0 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_ENABLE 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_QCTL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL 22:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_STATUS_0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_STATUS_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_STATUS_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIO_STATUS_PART0 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIO_STATUS_PART1 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_PIXOUT 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_IDC 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOP_PART0 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOP_PART1 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOP_PART2 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_PQ_PART0 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_PQ_PART1 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_PQ_2 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_PQ_3 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOS_PART0 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOS_PART1 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_PIXOUT_2 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_POSTCOALESCE 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_IQ_FULL_PART0 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_IQ_FULL_PART1 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_TEXIO 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOP_DEBUG0_PART0 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOP_DEBUG1_PART0 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOP_DEBUG2_PART0 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOP_DEBUG3_PART1 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_TEXIO_DEBUG0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_TEXIO_DEBUG1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_TEXIO_DEBUG2 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_TEXIO_DEBUG3 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG0_PART0 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG1_PART0 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG2_PART0 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG0_PART1 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG1_PART1 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG2_PART1 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG2_PART2 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_PIXOUT_DEBUG0 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_MMISC_DEBUG0 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_STATIC_PATTERN0 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_STATIC_PATTERN1 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_DEBUG1 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_DEBUG2 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_DEBUG3 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_DEBUG4 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_DEBUG5 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_DEBUG6 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_DEBUG7 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_DEBUG8 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_DEBUG9 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_DEBUG10 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_DEBUG11 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_SINGLE_PASS0 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_L1DATA_PART0 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_SINGLE_PASS_COMPUTE 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_T2D_PART0 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_T2D_PART1 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_PMPRED0 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_PMPRED1 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_PMPRED2 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_PMPRED3 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_SINGLE_PASS1 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_POSTCOALESCE2 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_POSTCOALESCE3 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_PMPRED4 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_DEBUG12 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_APM_GROUP_5 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_APM_GROUP_4 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_APM_GROUP_3 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_APM_GROUP_2 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_APM_GROUP_1 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_APM_GROUP_0 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_ENABLE 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_CTRL_MIO_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_DIDT_WEIGHTS_CTL 0x005043e0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_DIDT_WEIGHTS_CTL__PRIV_LEVEL_MASK 0x00504300 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_DIDT_WEIGHTS_CTL_INDEX 1:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_DIDT_WEIGHTS_CTL_INDEX_ZERO 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_DIDT_WEIGHTS_CTL_INDEX_MIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_DIDT_WEIGHTS_CTL_INDEX_MAX 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_DIDT_WEIGHTS_DATA 0x005043e4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_DIDT_WEIGHTS_DATA__PRIV_LEVEL_MASK 0x00504300 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_DIDT_WEIGHTS_DATA__APERTURE_INDEX_OFFSET 0xfffffffc /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_DIDT_WEIGHTS_DATA_DATA 31:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_DIDT_WEIGHTS_DATA_DATA_INIT 0x00000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x00504330 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 /* R--UF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_MAJOR 19:16 /* R--UF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_MAJOR_5 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_MAJOR_7 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_MAJOR_8 0x8 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_MINOR 15:8 /* R--UF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_MINOR_00 0x00 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_MINOR_01 0x01 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_MINOR_02 0x02 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_MINOR_03 0x03 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_MINOR_05 0x05 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_MINOR_06 0x06 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_MINOR_07 0x07 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 19:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_5_00 0x500 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_5_02 0x502 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_5_03 0x503 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_5_05 0x505 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_5_06 0x506 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_5_07 0x507 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_7_00 0x700 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_7_01 0x701 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_8_02 0x802 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_8_04 0x804 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_8_06 0x806 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MAJOR 31:28 /* R--UF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MAJOR_5 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MAJOR_6 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MAJOR_7 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MAJOR_8 0x8 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MINOR 27:20 /* R--UF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MINOR_00 0x00 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MINOR_01 0x01 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MINOR_02 0x02 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MINOR_03 0x03 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MINOR_05 0x05 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MINOR_06 0x06 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_MINOR_07 0x07 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION 31:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_5_00 0x500 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_5_02 0x502 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_5_03 0x503 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_5_05 0x505 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_5_06 0x506 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_6_00 0x600 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_6_01 0x601 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_6_02 0x602 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_7_00 0x700 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_7_01 0x701 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_8_02 0x802 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_8_04 0x804 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_8_06 0x806 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION_8_07 0x807 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MACHINE_ID0 0x00504334 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MACHINE_ID0_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MACHINE_ID0_V_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONTEXT_SAVE_ADDR 0x00504338 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONTEXT_SAVE_ADDR_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONTEXT_SAVE_ADDR_V_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x0050433c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_ICACHE_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_ICACHE_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_IDC_CCACHE 1:1 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_IDC_CCACHE_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_IDC_CCACHE_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_IMM_CCACHE0 2:2 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_IMM_CCACHE0_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_IMM_CCACHE0_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_STATE_IMC_IV 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_STATE_IMC_IV_INCLUDE_TPC_MODE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_STATE_IMC_IV_EXCLUDE_TPC_MODE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_FILTER 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_FILTER_ENABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_FILTER_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_ALL_BANKS 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_ALL_BANKS_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_ALL_BANKS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_CBREF 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_CBREF_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_CBREF_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_CBREF_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_RTV 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_RTV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_RTV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_RTV_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_VEID 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_VEID_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_VEID_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_VEID_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_ICC_WAKEUP_BROADCAST_ENABLE 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_ICC_WAKEUP_BROADCAST_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_ICC_WAKEUP_BROADCAST_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_ICC_WAKEUP_BROADCAST_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_BINDLESS_START_END 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_BINDLESS_START_END_CALCULATE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_BINDLESS_START_END_SINGLE_SECTOR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_BINDLESS_START_END_ZERO_THREE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL_BINDLESS_START_END_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK 0x00504394 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_PL2_AND_PL3_ENABLED 0xc /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_CTXSW_UCODE_ENABLED 0x00076 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL 0x00504340 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL__PRIV_LEVEL_MASK 0x00504394 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_VPR_SCRUB 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_VPR_SCRUB_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_VPR_SCRUB_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_VPR_SCRUB_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_VPR_SCRUB_STATUS 4:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_VPR_SCRUB_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PRIVATE_CONTROL_VPR_SCRUB_STATUS_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL 0x00504344 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_ICC_TAG_PREFETCH_LIMIT 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_ICC_TAG_PREFETCH_LIMIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_ICC_TAG_PREFETCH_LIMIT_8 0x8 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_ICC_PREFETCH 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_ICC_PREFETCH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_ICC_PREFETCH_PLUS_1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_ICC_PREFETCH_PLUS_2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_ICC_PREFETCH_PLUS_3 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_ICC_PREFETCH_PLUS_4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_ICC_PREFETCH_PLUS_6 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_ICC_PREFETCH_PLUS_8 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_ICC_PREFETCH_PLUS_10 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_0 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_0_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_1 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_1_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_2 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_2_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_3 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_3_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_4_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_5_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_6_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_FET_CONTROL_CYA_7_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED 0x00504348 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_EOS 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_EOS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_EOS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_EOS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_ALLOC_BATCH 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_ALLOC_BATCH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_ALLOC_BATCH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_ALLOC_BATCH_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_MPC_PRIORITY 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_MPC_PRIORITY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_MPC_PRIORITY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_MPC_PRIORITY_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_VTG_BOOST 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_VTG_BOOST_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_VTG_BOOST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_VTG_BOOST_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_BATCH_BOOST 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_BATCH_BOOST_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_BATCH_BOOST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_BATCH_BOOST_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_CACHE_MISS_BOOST 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_CACHE_MISS_BOOST_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_CACHE_MISS_BOOST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_CACHE_MISS_BOOST_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_SUBTILE_HOLD 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_SUBTILE_HOLD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_SUBTILE_HOLD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_SUBTILE_HOLD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER 15:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_4 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_5 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_6 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_7 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_8 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_9 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_10 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_11 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_12 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_13 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_14 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_15 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_16 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_17 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_18 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_INF 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_INIT 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_ROTATION_CS 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_ROTATION_CS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_ROTATION_CS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_ROTATION_CS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_ROTATION_PS 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_ROTATION_PS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_ROTATION_PS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_ROTATION_PS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_ROTATION_VTG 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_ROTATION_VTG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_ROTATION_VTG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_AGE_ROTATION_VTG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_CTA_AS_TILE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_CTA_AS_TILE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_CTA_AS_TILE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_CTA_AS_TILE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_EXIT_WAIT_FOR_ERRBAR 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_EXIT_WAIT_FOR_ERRBAR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_EXIT_WAIT_FOR_ERRBAR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_EXIT_WAIT_FOR_ERRBAR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_L0IC 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_L0IC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_L0IC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_L0IC_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_UNLOCK_DROPPED_MISS 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_UNLOCK_DROPPED_MISS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_UNLOCK_DROPPED_MISS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_UNLOCK_DROPPED_MISS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FULLTAG_WAKEUP_ALL 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FULLTAG_WAKEUP_ALL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FULLTAG_WAKEUP_ALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FULLTAG_WAKEUP_ALL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_UNCOND_BRANCH_OPT 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_UNCOND_BRANCH_OPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_UNCOND_BRANCH_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_UNCOND_BRANCH_OPT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_DISABLE_DISCARD_NEXT_L0IC_HIT 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_DISABLE_DISCARD_NEXT_L0IC_HIT_DISCARD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_DISABLE_DISCARD_NEXT_L0IC_HIT_NO_DISCARD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_DISABLE_DISCARD_NEXT_L0IC_HIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_ALLOW_GSCHED_ON_FWD_PROGRESS 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_ALLOW_GSCHED_ON_FWD_PROGRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_ALLOW_GSCHED_ON_FWD_PROGRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_ALLOW_GSCHED_ON_FWD_PROGRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_EXTRA_DMMA_WAIT 28:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_EXTRA_DMMA_WAIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FP16_FWD_PROGRESS_WATERMK 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_FP16_FWD_PROGRESS_WATERMK_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_SPARE 31:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MACRO_SCHED_SPARE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED 0x00504350 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_SAFE_WAIT 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_SAFE_WAIT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_SAFE_WAIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_SAFE_WAIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_REQ_ALL 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_REQ_ALL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_REQ_ALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_REQ_ALL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FWD_PROGRESS 6:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FWD_PROGRESS_DISABLE 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FWD_PROGRESS_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_LONG_WAIT 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_LONG_WAIT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_LONG_WAIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_LONG_WAIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_GROUP_BIT 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_GROUP_BIT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_GROUP_BIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_GROUP_BIT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_DEPBAR_0 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_DEPBAR_0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_DEPBAR_0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FORCE_DEPBAR_0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_GROUP_BIT_CLR_ON_STALL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_GROUP_BIT_CLR_ON_STALL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_GROUP_BIT_CLR_ON_STALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_GROUP_BIT_CLR_ON_STALL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_DEFER_BLOCKING 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_DEFER_BLOCKING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_DEFER_BLOCKING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_DEFER_BLOCKING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_EXE_COLLAPSING 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_EXE_COLLAPSING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_EXE_COLLAPSING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_EXE_COLLAPSING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_IFB_READ_OPT 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_IFB_READ_OPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_IFB_READ_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_IFB_READ_OPT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_EXTRA_MMA_S_WAIT 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_EXTRA_MMA_S_WAIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_EXTRA_MMA_M_WAIT 16:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_EXTRA_MMA_M_WAIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_EXTRA_MMA_L_WAIT 31:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_EXTRA_MMA_L_WAIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_IPB_BYPASS 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_IPB_BYPASS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_IPB_BYPASS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_IPB_BYPASS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_B2B_EXIT_ON_SHADOWPIPE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_B2B_EXIT_ON_SHADOWPIPE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_B2B_EXIT_ON_SHADOWPIPE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_B2B_EXIT_ON_SHADOWPIPE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA16 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA16_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA16_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA16_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA32 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA32_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA32_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA32_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMAE8M10 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMAE8M10_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMAE8M10_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMAE8M10_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA8832 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA8832_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA8832_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA8832_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_BMMA 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_BMMA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_BMMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_BMMA_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_FFMA 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_FFMA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_FFMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_FFMA_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IDP4A 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IDP4A_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IDP4A_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IDP4A_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DMMA 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DMMA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DMMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DMMA_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DFMA 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DFMA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DFMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DFMA_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK 0x00504378 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL 0x00504354 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL__PRIV_LEVEL_MASK 0x00504378 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP0_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP0_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP1_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP1_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP2_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP2_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP3_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP3_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP_TASK 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_SCRUB_QRFDP_DONE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS 0x00504358 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP1_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP1_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP2_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP2_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP3_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP3_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP0 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP1 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP1_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP1_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP2 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP2_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP2_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP3 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP3_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP3_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP0 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP0_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP0_ACTIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP1 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP1_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP1_ACTIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP2 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP2_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP2_ACTIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP3 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP3_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP3_ACTIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP(i) (8+(i)):(8+(i)) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP(i) (16+(i)):(16+(i)) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP_PASSED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_SCRUB_QRFDP_FAILED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CORRECTED_ERR_COUNT 0x0050435c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_UNCORRECTED_ERR_COUNT 0x00504360 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_ADDRESS 0x00504364 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_ADDRESS_INDEX 14:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_ADDRESS_SM_ID 14:14 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_ADDRESS_QUADRANT_ID 13:12 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_ADDRESS_QUAD_ID 11:10 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_LRF_ECC_ADDRESS_BANK_ID 9:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL 0x00504368 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL__PRIV_LEVEL_MASK 0x00504378 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_0_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_0_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_TASK 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_DONE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS 0x0050436c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_0 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1(i) (2+(i)):(2+(i)) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT 0x00504370 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT 0x00504374 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK 0x0050437c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL2_ENABLED 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL23_ENABLED 0xc /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL2_ENABLED 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE 0x00504380 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE__PRIV_LEVEL_MASK 0x0050437c /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_ISSUE_STAGGER_BASE 5:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_ISSUE_STAGGER_BASE_INIT 0x00 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_ISSUE_STAGGER_INCR 13:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_ISSUE_STAGGER_INCR_INIT 0x00 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_ISSUE_STATUS 14:14 /* R-BVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_ISSUE_STATUS_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_ISSUE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_ISSUE_STATUS_INIT 0x0 /* R-B-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_ISSUE_ENABLE 15:15 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_ISSUE_ENABLE_NO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_ISSUE_ENABLE_YES 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_ISSUE_ENABLE_INIT 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_DISP_STAGGER_BASE 21:16 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_DISP_STAGGER_BASE_INIT 0x00 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_DISP_STAGGER_INCR 29:24 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_DISP_STAGGER_INCR_INIT 0x00 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_DISP_STATUS 30:30 /* R-BVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_DISP_STATUS_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_DISP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_DISP_STATUS_INIT 0x0 /* R-B-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_DISP_ENABLE 31:31 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_DISP_ENABLE_NO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_DISP_ENABLE_YES 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_HIPWR_THROTTLE_DISP_ENABLE_INIT 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_CTRL1 0x005043fc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_CTRL1_FMAH_THROTTLE_MIN 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_CTRL1_FMAH_THROTTLE_MIN_INIT 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_CTRL1_FMAH_THROTTLE_MAX 24:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_CTRL1_FMAH_THROTTLE_MAX_INIT 0x0d /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_CTRL1_FMAH_THROTTLE_INC 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_CTRL1_FMAH_THROTTLE_INC_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_CTRL1_FMAH_THROTTLE_ENABLE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_CTRL1_FMAH_THROTTLE_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DFD_CONTROL 0x00504398 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DFD_CONTROL_CMD 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DFD_CONTROL_CMD_NOP 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DFD_DATA 0x0050439c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DFD_DATA_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DFD_DATA_VALUE_EMPTY 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x005043a0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_INCLUDE_RFA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_TTU 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_TTU_EXCLUDE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_TTU_INCLUDE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_TTU_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL_1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_BR_FALLTHRU_OPT 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_BR_FALLTHRU_OPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_BR_FALLTHRU_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_BR_FALLTHRU_OPT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_8 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_8_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_8_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_8_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_9 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_9_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_9_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_9_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_10 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_10_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_10_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_10_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_11 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_11_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_11_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_11_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_12 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_12_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_12_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_12_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_13 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_13_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_13_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_13_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_14 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_14_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_14_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_14_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_15 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_15_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_15_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_SCTL_CYA_15_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_FFMA_DATAPATH 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_FFMA_DATAPATH_USE_BUNDLE_CONFIG 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_FFMA_DATAPATH_USE_BOTH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL_FFMA_DATAPATH_USE_FMA_LITE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL 0x005043a4 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_COLLECTOR_REUSE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_COLLECTOR_REUSE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_COLLECTOR_REUSE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_2_CYCLE_COLLECTION 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_2_CYCLE_COLLECTION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_2_CYCLE_COLLECTION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_FTZ_NARROWS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_FTZ_NARROWS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_FTZ_NARROWS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_FTZ_NARROWS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_KILLED_LD_IS_NOP 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_KILLED_LD_IS_NOP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_KILLED_LD_IS_NOP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_KILLED_LD_IS_NOP_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_FORCE_ALLOW_GLOBAL_STORE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_FORCE_ALLOW_GLOBAL_STORE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_FORCE_ALLOW_GLOBAL_STORE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_FORCE_ALLOW_GLOBAL_STORE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_COLLECTOR_FP64_REUSE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_COLLECTOR_FP64_REUSE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_COLLECTOR_FP64_REUSE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_FP64_PAIRING 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_FP64_PAIRING_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_FP64_PAIRING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_DDP_RAM_REUSE 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_DDP_RAM_REUSE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_DDP_RAM_REUSE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_PIXOUT_READ_PARALLEL 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_PIXOUT_READ_PARALLEL_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_PIXOUT_READ_PARALLEL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_TOQ_STATUS_STALL 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_TOQ_STATUS_STALL_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_TOQ_STATUS_STALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_RFDP_UNIFORM_DATA_DETECT 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_RFDP_UNIFORM_DATA_DETECT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_RFDP_UNIFORM_DATA_DETECT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_RE_SUPPRESS 12:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_RE_SUPPRESS_ON_PT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_RE_SUPPRESS_ON_FULL_MASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_RE_SUPPRESS_DISABLE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_VTG_SHADER_POP 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_VTG_SHADER_POP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_VTG_SHADER_POP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_PIXEL_SHADER_POP 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_PIXEL_SHADER_POP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_PIXEL_SHADER_POP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_COMPUTE_SHADER_POP 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_COMPUTE_SHADER_POP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_COMPUTE_SHADER_POP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_RE_SUPPRESS_FOR_WT 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_RE_SUPPRESS_FOR_WT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_RE_SUPPRESS_FOR_WT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_CYA1 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_CYA1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_CANCEL_REUSE_ON_BYPASS 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_CANCEL_REUSE_ON_BYPASS_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_CANCEL_REUSE_ON_BYPASS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_ACTIVE_MASK_CG 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_ACTIVE_MASK_CG_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_ACTIVE_MASK_CG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_AND_C_REUSE 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_AND_C_REUSE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_AND_C_REUSE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_COMPUTE_SHADER_QUAD 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_TTU_INST_OUTSIDE_MACRO 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_TTU_INST_OUTSIDE_MACRO_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_TTU_INST_OUTSIDE_MACRO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_NON_TTU_INST_IN_MACRO 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_NON_TTU_INST_IN_MACRO_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_NON_TTU_INST_IN_MACRO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_SPARE 31:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL_SPARE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2 0x005043a8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_PIX_PQ_WATERMARK 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_PIX_PQ_WATERMARK_MIN 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_PIX_PQ_WATERMARK_MAX 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_PIX_PQ_WATERMARK_INIT 0x19 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_SHM_PQ_WATERMARK 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_SHM_PQ_WATERMARK_MIN 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_SHM_PQ_WATERMARK_MAX 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_SHM_PQ_WATERMARK_INIT 0x1c /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_TEX_PQ_WATERMARK 20:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_TEX_PQ_WATERMARK_MIN 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_TEX_PQ_WATERMARK_MAX 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_TEX_PQ_WATERMARK_INIT 0x18 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_GRP1_PQ_WATERMARK 25:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_GRP1_PQ_WATERMARK_MIN 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_GRP1_PQ_WATERMARK_MAX 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_GRP1_PQ_WATERMARK_INIT 0x14 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL 27:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_8_CYCLES 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_16_CYCLES 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_32_CYCLES 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_AGUL_THROTTLE 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_AGUL_THROTTLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_AGUL_THROTTLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_AGUL_THROTTLE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_WAKEUP_AUX_ENTRY 29:29 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_WAKEUP_AUX_ENTRY_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_WAKEUP_AUX_ENTRY_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_RESET_ALL_PQ 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_RESET_ALL_PQ_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_RESET_ALL_PQ_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_SPARE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL2_SPARE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3 0x005043c8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_AGUL_THROTTLE_ALWAYS_ON 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_AGUL_THROTTLE_ALWAYS_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_AGUL_THROTTLE_ALWAYS_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_AGUL_THROTTLE_ALWAYS_ON_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_AGUL_THROTTLE_SHM 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_AGUL_THROTTLE_SHM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_AGUL_THROTTLE_SHM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_AGUL_THROTTLE_SHM_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_AGUL_THROTTLE_WATERMARK 6:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_AGUL_THROTTLE_WATERMARK_MIN 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_AGUL_THROTTLE_WATERMARK_MAX 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_AGUL_THROTTLE_WATERMARK_INIT 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_CLEAR_CREDIT_ON_RFA_STATUS 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_CLEAR_CREDIT_ON_RFA_STATUS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_CLEAR_CREDIT_ON_RFA_STATUS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_CLEAR_CREDIT_ON_RFA_STATUS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_CLEAR_CREDIT_ON_LST_STATUS 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_CLEAR_CREDIT_ON_LST_STATUS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_CLEAR_CREDIT_ON_LST_STATUS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_CLEAR_CREDIT_ON_LST_STATUS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_THRESHOLD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_EXT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_BOTH 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD 12:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_32 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_64 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_128 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_255 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS_DISABLE_ON_ECC 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS_ENABLE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_STALL_MUFU_ON_ECC 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_STALL_MUFU_ON_ECC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_STALL_MUFU_ON_ECC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_STALL_MUFU_ON_ECC_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT 18:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_VAL1 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_VAL2 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_VAL3 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_VAL4 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_TPQ_PARTIAL_GRANT 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_TPQ_PARTIAL_GRANT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_TPQ_PARTIAL_GRANT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_TPQ_PARTIAL_GRANT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_TTU_TPQ_PARTIAL_GRANT 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_TTU_TPQ_PARTIAL_GRANT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_TTU_TPQ_PARTIAL_GRANT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_TTU_TPQ_PARTIAL_GRANT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_TPQ_GRANT_WITH_AUX_REPLAY 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_TPQ_GRANT_WITH_AUX_REPLAY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_TPQ_GRANT_WITH_AUX_REPLAY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_TPQ_GRANT_WITH_AUX_REPLAY_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD 23:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_VAL0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_VAL1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_VAL2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_VAL3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB 25:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB_THRESHOLD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB_ALWAYS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD 28:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_VAL0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_VAL1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_VAL2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_VAL3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_INIT 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_SPARE 31:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DISP_CTRL3_SPARE_INIT 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_OBSERVE 0x005043ac /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_OBSERVE_CYA_6 6:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_OBSERVE_CYA_7 7:7 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_OBSERVE_CYA_8 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_OBSERVE_CYA_9 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_OBSERVE_CYA_10 10:10 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_OBSERVE_CYA_11 11:11 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_OBSERVE_CYA_12 12:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_OBSERVE_CYA_13 13:13 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_OBSERVE_CYA_14 14:14 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_OBSERVE_CYA_15 15:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x005043b0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL_1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WRITE_PRI_CTL 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WRITE_PRI_CTL_BOTH 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WRITE_PRI_CTL_SELECT_ONE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_PULSE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_PULSE_NEVER 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_PULSE_ON_SM_NONIDLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_PULSE_ALWAYS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT1 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT2 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT3 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1 19:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC 23:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK 25:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL 27:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL 29:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_BA_BLCG_WAKEUP 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL_BA_BLCG_WAKEUP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1 0x005043cc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_CTL 0x005044f0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_CTL_INDEX 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_CTL_INDEX_MIN 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_CTL_INDEX_MAX 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_CTL_TRIGGER 11:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_CTL_TRIGGER_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_CTL_CONTROL 30:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_CTL_CONTROL_INIT 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_CTL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_CTL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_DATA 0x005044f4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_DATA_DATA 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_THROTTLE_DATA_DATA_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_VST_CTL 0x005044f8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_VST_CTL_INDEX 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_VST_CTL_INDEX_MIN 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_VST_CTL_INDEX_MAX 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_VST_CTL_CONTROL 30:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_VST_CTL_CONTROL_INIT 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_VST_CTL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_VST_CTL_ENABLE_NO 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_VST_CTL_ENABLE_YES 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_VST_DATA 0x005044fc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_VST_DATA_DATA 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_POWER_VST_DATA_DATA_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL 0x005043b4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FMAI 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FMAI_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FMAI_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FMAI_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FMAI_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FXU 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FXU_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FXU_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FXU_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FXU_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FU 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FU_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FU_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FU_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FU_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_X2X 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_X2X_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_X2X_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_X2X_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_X2X_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_RFDP 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_RFDP_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_RFDP_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_RFDP_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_RFDP_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_SFPQ_FMA64 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_SFPQ_FMA64_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_SFPQ_FMA64_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_SFPQ_FMA64_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_SFPQ_FMA64_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_IMMA 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_IMMA_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_IMMA_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_IMMA_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_IMMA_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FP16G0DP 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FP16G0DP_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FP16G0DP_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FP16G0DP_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FP16G0DP_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FP16G1DP 19:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FP16G1DP_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FP16G1DP_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FP16G1DP_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_FP16G1DP_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_CORE2LST_WAKEUP 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_CORE2LST_WAKEUP_USE_MIOC_WAKEUP 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_CORE2LST_WAKEUP_USE_MIOC_STATUS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_F_PIPE 22:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_F_PIPE_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_F_PIPE_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_F_PIPE_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_F_PIPE_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_M_PIPE 24:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_M_PIPE_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_M_PIPE_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_M_PIPE_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_WAKEUP_CONTROL_M_PIPE_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_QUAD_BA_CONTROL 0x005043b8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_QUAD_BA_CONTROL__PRIV_LEVEL_MASK 0x00504300 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_QUAD_BA_CONTROL_INDEX 4:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_QUAD_BA_CONTROL_INDEX_ZERO 0x00 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_QUAD_BA_CONTROL_INDEX_MIN 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_QUAD_BA_CONTROL_INDEX_MAX 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_QUAD_BA_DATA 0x005043bc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_QUAD_BA_DATA__PRIV_LEVEL_MASK 0x00504300 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_QUAD_BA_DATA__APERTURE_INDEX_OFFSET 0xfffffffc /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_QUAD_BA_DATA_DATA 27:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_QUAD_BA_DATA_DATA_INIT 0x0000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_BA_CONTROL 0x005043c0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_BA_CONTROL__PRIV_LEVEL_MASK 0x00504300 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_BA_CONTROL_INDEX 1:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_BA_CONTROL_INDEX_ZERO 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_BA_CONTROL_INDEX_MIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_BA_CONTROL_INDEX_MAX 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_BA_DATA 0x005043c4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_BA_DATA__PRIV_LEVEL_MASK 0x00504300 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_BA_DATA__APERTURE_INDEX_OFFSET 0xfffffffc /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_BA_DATA_DATA 27:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_BA_DATA_DATA_INIT 0x0000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_BA_CONTROL 0x005043d0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_BA_CONTROL__PRIV_LEVEL_MASK 0x00504300 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_BA_CONTROL_INDEX 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_BA_CONTROL_INDEX_ZERO 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_BA_CONTROL_INDEX_MIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_BA_CONTROL_INDEX_MAX 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_BA_DATA 0x005043d4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_BA_DATA__PRIV_LEVEL_MASK 0x00504300 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_BA_DATA__APERTURE_INDEX_OFFSET 0xfffffffc /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_BA_DATA_DATA 27:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_BA_DATA_DATA_INIT 0x0000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_BA_CONTROL 0x00504668 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_BA_CONTROL__PRIV_LEVEL_MASK 0x00504300 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_BA_CONTROL_INDEX 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_BA_CONTROL_INDEX_ZERO 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_BA_CONTROL_INDEX_MIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_BA_CONTROL_INDEX_MAX 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_BA_DATA 0x0050466c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_BA_DATA__PRIV_LEVEL_MASK 0x00504300 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_BA_DATA__APERTURE_INDEX_OFFSET 0xfffffffc /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_BA_DATA_DATA 27:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_BA_DATA_DATA_INIT 0x0000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG 0x00504480 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_IDLE_CG_DLY_CNT__PROD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG1 0x00504484 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG1_SLCG 17:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG1_SLCG_ENABLED 0x00000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG1_SLCG_DISABLED 0x1ffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_0_CG1_SLCG__PROD 0x1fffe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG 0x00504488 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_IDLE_CG_DLY_CNT__PROD 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG1 0x0050448c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_1_CG1_SLCG__PROD 0x7fb8f9c2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG 0x00504490 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_IDLE_CG_DLY_CNT__PROD 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG1 0x00504494 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG1_SLCG 29:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG1_SLCG_DISABLED 0x1fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_2_CG1_SLCG__PROD 0x1cf80180 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG 0x00504498 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG1 0x0050449c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_3_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG 0x005044a0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_IDLE_CG_DLY_CNT__PROD 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG1 0x005044a4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG1_SLCG 13:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG1_SLCG_DISABLED 0x1fff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_4_CG1_SLCG__PROD 0x1ffe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG 0x005044a8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_IDLE_CG_DLY_CNT__PROD 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG1 0x005044ac /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_5_CG1_SLCG__PROD 0xfc00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG 0x005044b0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_IDLE_CG_DLY_CNT__PROD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG1 0x005044b4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG1_SLCG 12:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG1_SLCG_ENABLED 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG1_SLCG_DISABLED 0xfff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_BLCG_6_CG1_SLCG__PROD 0xeb0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG 0x005044e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_MEMBAR_WINDOW 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_MEMBAR_WINDOW_INIT 0x02 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_X4 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_X16 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_X64 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_X256 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_TEX2D_CONTROL 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_TEX2D_CONTROL_HALF0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_TEX2D_CONTROL_HALF1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_TEX2D_CONTROL_BOTH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_TEX2D_CONTROL_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_PIX_CMD_DONE_STALL_PFM3D 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_PIX_CMD_DONE_STALL_PFM3D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_PIX_CMD_DONE_STALL_PFM3D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_PIX_CMD_DONE_STALL_PFM3D_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_MIOP_SPARE 23:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG_MIOP_SPARE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2 0x005044ec /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_MIOS_SPARE 2:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_MIOS_SPARE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_PIXOUT_LOW_WATERMARK 5:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_PIXOUT_LOW_WATERMARK_INIT 0x5 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_IMC_TAG_HASH_CTRL 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_IMC_TAG_HASH_CTRL_GALOIS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_IMC_TAG_HASH_CTRL_NON_GALOIS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_IMC_TAG_HASH_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_TTU_BLCG_INPUT_CTRL 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_TTU_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_TTU_BLCG_INPUT_CTRL_INCLUDE_RFA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_TTU_BLCG_INPUT_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_MIOS_BLCG_INPUT_CTRL 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_MIOS_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_MIOS_BLCG_INPUT_CTRL_INCLUDE_RFA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_MIOS_BLCG_INPUT_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_MIOP_BLCG_INPUT_CTRL 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_MIOP_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_MIOP_BLCG_INPUT_CTRL_INCLUDE_RFA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_MIOP_BLCG_INPUT_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_OUTSTANDING_MIOS_WB_REQ_COUNT 16:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_OUTSTANDING_MIOS_WB_REQ_COUNT_DISABLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_OUTSTANDING_MIOS_WB_REQ_COUNT_16 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_OUTSTANDING_TEX_WB_REQ_COUNT 21:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_OUTSTANDING_TEX_WB_REQ_COUNT_DISABLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_OUTSTANDING_TEX_WB_REQ_COUNT_16 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_OUTSTANDING_ADU_WB_REQ_COUNT 26:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_OUTSTANDING_ADU_WB_REQ_COUNT_DISABLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_OUTSTANDING_ADU_WB_REQ_COUNT_16 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_DETECT_UNIFORM_LD 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_DETECT_UNIFORM_LD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_DETECT_UNIFORM_LD_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_FC_RESERVED_FOR_SUST_NUM_CYCLES 30:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_FC_RESERVED_FOR_SUST_NUM_CYCLES_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_SUST_STEAL 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_SUST_STEAL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_SUST_STEAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_MIO_CFG2_SUST_STEAL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL 0x005043d8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_FAST_POINT_SAMPLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_FAST_POINT_SAMPLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_FAST_POINT_SAMPLE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP 2:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_DEFAULT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_TO_CG 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_TO_CV 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_BYPASS 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP 4:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_DEFAULT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_TO_CG 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_TO_CV 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_BYPASS 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_TEX2SMM_ERR_RESPONSE_FORWARD 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_TEX2SMM_ERR_RESPONSE_FORWARD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_TEX2SMM_ERR_RESPONSE_FORWARD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_TEX2SMM_ERR_RESPONSE_FORWARD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE_INSTR 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE_FORCE_RTZ 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE_FORCE_RTNE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE 10:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_X86_63_47_MATCH 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_ARM_63_48_MATCH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_POWER_63_46_ZERO 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_POWER_63_49_ZERO 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_ARM_55_48_MATCH 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_NO_CHECK 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_SPARE 18:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEXIO_CONTROL_SPARE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_SAMP_CTRL 0x005043dc /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_SAMP_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_SAMP_CTRL_ENABLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_SAMP_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_SAMP_CTRL_TIMER 5:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_PM_SAMP_CTRL_TIMER_INIT 0x05 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x00504608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_TPC_ID 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_TPC_ID_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TPC_ESR_SM_SEL 0x0050460c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TPC_ESR_SM_SEL_SM0_ERROR 0:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TPC_ESR_SM_SEL_SM0_ERROR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TPC_ESR_SM_SEL_SM0_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TPC_ESR_SM_SEL_SM1_ERROR 1:1 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TPC_ESR_SM_SEL_SM1_ERROR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TPC_ESR_SM_SEL_SM1_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TPC_ESR_SM_SEL_SMC_ERROR 2:2 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TPC_ESR_SM_SEL_SMC_ERROR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TPC_ESR_SM_SEL_SMC_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x00504610 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_REPORT_MASK_VAT_ALARM 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_REPORT_MASK_VAT_ALARM_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_REPORT_MASK_VAT_ALARM_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_CORRECTED 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_CORRECTED_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_CORRECTED_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_UNCORRECTED 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_UNCORRECTED_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_UNCORRECTED_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x00504614 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_VAT_ALARM 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_VAT_ALARM_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_VAT_ALARM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_ECC_CORRECTED 4:4 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_ECC_CORRECTED_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_ECC_CORRECTED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_ECC_UNCORRECTED 5:5 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_ECC_UNCORRECTED_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_ECC_UNCORRECTED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL 0x00504618 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_NANOSLEEP_MIN 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_NANOSLEEP_MIN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_NANOSLEEP_MAX 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_NANOSLEEP_MAX_INIT 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_YIELD_NOP_CNT 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_YIELD_NOP_CNT_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_CYA_PESSIMISTIC_YIELD 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_CYA_PESSIMISTIC_YIELD_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_CYA_PESSIMISTIC_YIELD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_CYA_FORCE_ALIASED 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_CYA_FORCE_ALIASED_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_CYA_FORCE_ALIASED_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_CYA_DISABLE_OPT_TOP 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_CYA_DISABLE_OPT_TOP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_CYA_DISABLE_OPT_TOP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_BSSY_REPLACE_MASK 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_BSSY_REPLACE_MASK_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_BSSY_REPLACE_MASK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_BSYNC_EMPTY_STACK_YIELD 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_BSYNC_EMPTY_STACK_YIELD_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_BSYNC_EMPTY_STACK_YIELD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_ELECTION_RELEASE_BARRIER 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_ELECTION_RELEASE_BARRIER_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_ELECTION_RELEASE_BARRIER_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_CNTRL_ELECTION_RELEASE_BARRIER__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL 0x005043f0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SKIP_READ 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SKIP_READ_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SKIP_READ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SKIP_READ_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_HASH_LG 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_HASH_LG_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_HASH_LG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_HASH_LG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_HASH_TEX 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_HASH_TEX_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_HASH_TEX_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_HASH_TEX_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_L1_ATOMIC 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_L1_ATOMIC_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_L1_ATOMIC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_L1_ATOMIC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_SURFACE_LD 5:5 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_SURFACE_LD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_SURFACE_LD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_SURFACE_LD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_2D 6:6 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_2D_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_2D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_2D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_LOCAL 7:7 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_LOCAL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_LOCAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_LOCAL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_GLOBAL 8:8 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_GLOBAL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_GLOBAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_GLOBAL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_TEX 9:9 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_TEX_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_TEX_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_TEX_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_SURFACE_ST 10:10 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_SURFACE_ST_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_SURFACE_ST_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_SURFACE_ST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_CTRL 10:5 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_CTRL_EN_NONE 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CACHE_CTRL_EN_ALL 0x3f /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SCRUBBER_READY_COUNT 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SCRUBBER_READY_COUNT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SCRUBBER_READY_COUNT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SCRUBBER_READY_COUNT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_WRITE_ALLOC_SURFACE 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_WRITE_ALLOC_SURFACE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_WRITE_ALLOC_SURFACE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_WRITE_ALLOC_SURFACE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_WRITE_ALLOC_GLOBAL 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_WRITE_ALLOC_GLOBAL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_WRITE_ALLOC_GLOBAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_WRITE_ALLOC_GLOBAL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_WRITE_ALLOC_LOCAL 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_WRITE_ALLOC_LOCAL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_WRITE_ALLOC_LOCAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_WRITE_ALLOC_LOCAL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_DUAL_LOD_SERIAL 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_DUAL_LOD_SERIAL_AUTO 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_DUAL_LOD_SERIAL_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_REPLACEMENT_ALLOC_RANK_EU_AS_EN 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_REPLACEMENT_ALLOC_RANK_EU_AS_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_REPLACEMENT_ALLOC_RANK_EU_AS_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_REPLACEMENT_ALLOC_RANK_EU_AS_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_REPLACEMENT_HIT_RANK_EN 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_REPLACEMENT_HIT_RANK_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_REPLACEMENT_HIT_RANK_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_REPLACEMENT_HIT_RANK_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_LG_THROTTLE_T2D 22:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_LG_THROTTLE_T2D_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_LG_THROTTLE_DSLOT 27:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_LG_THROTTLE_DSLOT_INIT 0x08 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_ALWAYS_CUT_COLLECTOR 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_ALWAYS_CUT_COLLECTOR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_ALWAYS_CUT_COLLECTOR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_ALWAYS_CUT_COLLECTOR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SURFACE_CUT_COLLECTOR 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SURFACE_CUT_COLLECTOR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SURFACE_CUT_COLLECTOR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_SURFACE_CUT_COLLECTOR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_RESET_L1_ON_LEAK 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_RESET_L1_ON_LEAK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_RESET_L1_ON_LEAK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_RESET_L1_ON_LEAK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CLEAR_EV_LONG_ON_3DPFM 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CLEAR_EV_LONG_ON_3DPFM_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CLEAR_EV_LONG_ON_3DPFM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL_CLEAR_EV_LONG_ON_3DPFM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2 0x005043f4 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_RED 0:0 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_RED_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_RED_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_RED_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_ATOM_CAS 1:1 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_ATOM_CAS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_ATOM_CAS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_ATOM_CAS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_ATOM 2:2 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_ATOM_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_ATOM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_ATOM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_LG 3:3 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_LG_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_LG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_LG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_SURFACE 4:4 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_SURFACE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_SURFACE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_SURFACE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_ATOMIC_CTRL 4:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_ATOMIC_CTRL_EN_NONE 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CONCAT_ATOMIC_CTRL_EN_ALL 0x1f /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_LG_WR_COALESCE_EN 5:5 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_LG_WR_COALESCE_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_LG_WR_COALESCE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_LG_WR_COALESCE_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_LG_RD_COALESCE_EN 6:6 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_LG_RD_COALESCE_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_LG_RD_COALESCE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_LG_RD_COALESCE_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_SU_WR_COALESCE_EN 7:7 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_SU_WR_COALESCE_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_SU_WR_COALESCE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_SU_WR_COALESCE_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_SU_RD_COALESCE_EN 8:8 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_SU_RD_COALESCE_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_SU_RD_COALESCE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_SU_RD_COALESCE_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_TEX_RD_COALESCE_EN 9:9 /* RWIUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_TEX_RD_COALESCE_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_TEX_RD_COALESCE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_TEX_RD_COALESCE_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_COALESCE_EN_CTRL 9:5 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_COALESCE_EN_CTRL_EN_NONE 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_COALESCE_EN_CTRL_EN_ALL 0x1f /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_LIFE_EXTN_EN 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_LIFE_EXTN_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_LIFE_EXTN_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_LIFE_EXTN_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_LATFIFO_DEPTH_DIV4 18:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_LATFIFO_DEPTH_DIV4_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_TIMEOUT 22:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_TIMEOUT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_TIMEOUT_PRESCALAR 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_TIMEOUT_PRESCALAR_X2K 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_TIMEOUT_PRESCALAR_X16K 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_TIMEOUT_PRESCALAR_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DETECT_DSLOT_LEAK 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DETECT_DSLOT_LEAK_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DETECT_DSLOT_LEAK_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DETECT_DSLOT_LEAK__PROD 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DETECT_REFCOUNTER_ERR 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DETECT_REFCOUNTER_ERR_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DETECT_REFCOUNTER_ERR_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DETECT_REFCOUNTER_ERR__PROD 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DETECT_L1MISS_LEAK 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DETECT_L1MISS_LEAK_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DETECT_L1MISS_LEAK_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_STORE_COALESCE_GAP_EN 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_STORE_COALESCE_GAP_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_STORE_COALESCE_GAP_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_STORE_COALESCE_GAP_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_COALESCE_FLUSH 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_COALESCE_FLUSH_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_COALESCE_FLUSH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_NO_EVICT_LONG 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_NO_EVICT_LONG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_NO_EVICT_LONG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_NO_EVICT_LONG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_LD_COMMIT 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_LD_COMMIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_LD_COMMIT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_CBUF_LD_COMMIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DBE_PRTY_CYA 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DBE_PRTY_CYA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DBE_PRTY_CYA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1TAG_CTRL2_DBE_PRTY_CYA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL 0x005043f8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_LG_THROTTLE_ENABLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_LG_THROTTLE_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_LG_THROTTLE_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_LG_THROTTLE_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_MAIN_COLLECTOR_LOOK_AHEAD_ENABLE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_MAIN_COLLECTOR_LOOK_AHEAD_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_MAIN_COLLECTOR_LOOK_AHEAD_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_MAIN_COLLECTOR_LOOK_AHEAD_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIDE_COLLECTOR_LOOK_AHEAD_ENABLE 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIDE_COLLECTOR_LOOK_AHEAD_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIDE_COLLECTOR_LOOK_AHEAD_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIDE_COLLECTOR_LOOK_AHEAD_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIDE_COLLECTOR_PAIRING_ENABLE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIDE_COLLECTOR_PAIRING_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIDE_COLLECTOR_PAIRING_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIDE_COLLECTOR_PAIRING_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_HOLDING_BUFFER_BYPASS_ENABLE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_HOLDING_BUFFER_BYPASS_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_HOLDING_BUFFER_BYPASS_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_HOLDING_BUFFER_BYPASS_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_STALL_GNIC_REQUESTS_ENABLE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_STALL_GNIC_REQUESTS_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_STALL_GNIC_REQUESTS_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_STALL_GNIC_REQUESTS_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_STALL_4Q_REQUESTS_ENABLE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_STALL_4Q_REQUESTS_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_STALL_4Q_REQUESTS_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_STALL_4Q_REQUESTS_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TEX_ENABLE 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TEX_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TEX_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TEX_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_TCR_TEX_ENABLE 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_TCR_TEX_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_TCR_TEX_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_TCR_TEX_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_TCR_READ_PARTIAL_SECTOR_ENABLE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_TCR_READ_PARTIAL_SECTOR_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_TCR_READ_PARTIAL_SECTOR_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_TCR_READ_PARTIAL_SECTOR_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SM_READ_STARVATION_THRESHOLD_COUNT 14:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SM_READ_STARVATION_THRESHOLD_COUNT_INIT 0x4 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SM_READ_STALL_TEX_TCR_NUM_CYCLES 17:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SM_READ_STALL_TEX_TCR_NUM_CYCLES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_TEX_READ_STARVATION_THRESHOLD_COUNT 20:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_TEX_READ_STARVATION_THRESHOLD_COUNT_INIT 0x4 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_TEX_READ_STALL_TCR_NUM_CYCLES 23:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_TEX_READ_STALL_TCR_NUM_CYCLES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIDE_COLLECTOR_FAST_BDI_ENABLE 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIDE_COLLECTOR_FAST_BDI_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIDE_COLLECTOR_FAST_BDI_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIDE_COLLECTOR_FAST_BDI_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_TTU_READ_STARVATION_THRESHOLD_COUNT 27:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_TTU_READ_STARVATION_THRESHOLD_COUNT_INIT 0x4 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_TTU_READ_STALL_TEX_TCR_NUM_CYCLES 30:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_TTU_READ_STALL_TEX_TCR_NUM_CYCLES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TTU_ENABLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TTU_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TTU_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TTU_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_ADDRESS 0x0050461c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_ADDRESS_INDEX 17:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_ADDRESS_SM_ID 17:17 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_ADDRESS_SUBBANK_ID 16:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_DATA_ECC_ADDRESS_BANK_ID 14:10 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL 0x00504620 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL__PRIV_LEVEL_MASK 0x00504378 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_0_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_0_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_TASK 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_DONE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_PIXPRF 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_PIXPRF_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_PIXPRF_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_PIXPRF_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_MISS_FIFO 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_MISS_FIFO_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_MISS_FIFO_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CONTROL_SCRUB_MISS_FIFO_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS 0x00504624 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_0 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1(i) (2+(i)):(2+(i)) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_PIXPRF 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_PIXPRF_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_PIXPRF_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_MISS_FIFO 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_MISS_FIFO_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_MISS_FIFO_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_PIXPRF 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_PIXPRF_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_PIXPRF_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_MISS_FIFO 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_MISS_FIFO_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_MISS_FIFO_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT 0x00504628 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT 0x0050462c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS 0x00504630 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_SM_ID 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_STRUCT 14:13 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_STRUCT_EL1 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_STRUCT_PIXPRF 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_STRUCT_MISS_FIFO_T2D 0x2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_STRUCT_MISS_FIFO_W2D 0x3 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_EL1_BANK_ID 7:6 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_EL1_SET_ID 5:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_BANK_ID 7:6 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_SET_ID 5:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_PIXPRF_SM_ID 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_PIXPRF_STRUCT 14:13 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_PIXPRF_BANK_ID 9:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_PIXPRF_ROW 6:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_L1_TAG_ECC_ADDRESS_MISS_FIFO_SUBFIFO 12:10 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL 0x00504634 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL__PRIV_LEVEL_MASK 0x00504378 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM0_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM0_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM0 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM0_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM0_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM_TASK 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM_DONE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM(i) (2+(i)):(2+(i)) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM_TASK 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM_DONE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS 0x00504638 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM0 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM0 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM0 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM(i) (2+(i)):(2+(i)) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM(i) (4+(i)):(4+(i)) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM(i) (6+(i)):(6+(i)) /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CORRECTED_ERR_COUNT 0x0050463c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_UNCORRECTED_ERR_COUNT 0x00504640 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_ADDRESS 0x00504644 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_ADDRESS_INDEX 12:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_ADDRESS_SM_ID 12:12 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_ADDRESS_STRUCT 11:11 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_ADDRESS_STRUCT_WARP 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_ADDRESS_STRUCT_BARRIER 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_CBU_ECC_ADDRESS_ROW 10:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL 0x00504648 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL__PRIV_LEVEL_MASK 0x00504378 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_SCRUB_L1_DATA 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_SCRUB_L1_DATA_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_SCRUB_L1_DATA_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_SCRUB_L1_DATA_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS 0x0050464c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_L1_DATA 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_L1_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_L1_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_L1_DATA 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_L1_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_L1_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CORRECTED_ERR_COUNT 0x00504650 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT 0x00504654 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_ADDRESS 0x00504658 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_ADDRESS_SM_ID 17:17 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_ADDRESS_STRUCT 16:16 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_ADDRESS_STRUCT_L1 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_ADDRESS_SUBSTRUCT 14:14 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_ADDRESS_SUBSTRUCT_DATA 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_ADDRESS_QUAD_ID 13:12 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_ICACHE_ECC_ADDRESS_ROW 10:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL 0x00504384 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL__PRIV_LEVEL_MASK 0x00504378 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_DATA 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_DATA_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_DATA_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_DATA_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_PREDECODE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_PREDECODE_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_PREDECODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_PREDECODE_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_SCRUB_URF_DATA 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_SCRUB_URF_DATA_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_SCRUB_URF_DATA_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_SCRUB_URF_DATA_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS 0x00504388 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_DATA 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_PREDECODE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_PREDECODE_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_PREDECODE_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_URF_DATA 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_URF_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_URF_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_DATA 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_PREDECODE 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_PREDECODE_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_PREDECODE_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_URF_DATA 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_URF_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_URF_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CORRECTED_ERR_COUNT 0x0050438c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT 0x00504390 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_ADDRESS 0x0050434c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_ADDRESS_URF_DATA 0x00000002 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_ADDRESS_SM_ID 17:17 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_ADDRESS_STRUCT 16:14 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_ADDRESS_STRUCT_L0IC_DATA 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_ADDRESS_STRUCT_L0IC_PREDECODE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_ADDRESS_QUAD_ID 13:12 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_RAMS_ECC_ADDRESS_ROW 10:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL 0x0050465c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0_USE_TAG 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0_USE_TAG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0_USE_TAG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0_USE_TAG_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0_TAG_USE_SM_ID 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0_TAG_USE_SM_ID_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0_TAG_USE_SM_ID_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0_TAG_USE_SM_ID_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0TC_SLOW_REQUEST 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0TC_SLOW_REQUEST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0TC_SLOW_REQUEST_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0TC_SLOW_REQUEST_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TIF_PER_SM_TICKET 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TIF_PER_SM_TICKET_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TIF_PER_SM_TICKET_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TIF_PER_SM_TICKET_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD 6:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_4 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_8 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_16 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RCT_SHEAR_TRANSFORM_PRECISION 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RCT_SHEAR_TRANSFORM_PRECISION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RCT_SHEAR_TRANSFORM_PRECISION_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RCT_SHEAR_TRANSFORM_PRECISION_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_CNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_CNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_CNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TCKT_CLR_WAIT_ON_HPIPE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TCKT_CLR_WAIT_ON_HPIPE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TCKT_CLR_WAIT_ON_HPIPE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TCKT_CLR_WAIT_ON_HPIPE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0CC_REQ_HIGH_PRIORITY 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0CC_REQ_HIGH_PRIORITY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0CC_REQ_HIGH_PRIORITY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0CC_REQ_HIGH_PRIORITY_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD 14:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_CNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_CNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_CNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_MEMARB_L1C_HASH_USE_SM_ID 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_MEMARB_L1C_HASH_USE_SM_ID_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_MEMARB_L1C_HASH_USE_SM_ID_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_MEMARB_L1C_HASH_USE_SM_ID_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RTT_TRIANGLE_PAIR_SUPPORT 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RTT_TRIANGLE_PAIR_SUPPORT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RTT_TRIANGLE_PAIR_SUPPORT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RTT_TRIANGLE_PAIR_SUPPORT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE 19:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_VAL1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_VAL2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_VAL3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_VAL4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE 22:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_VAL1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_VAL2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_VAL3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_VAL4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RMU_RAY_ACTV_ERROR_CHECK 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RMU_RAY_ACTV_ERROR_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RMU_RAY_ACTV_ERROR_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RMU_RAY_ACTV_ERROR_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TIF_GREEDY_TCKT_ALLOCATE 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TIF_GREEDY_TCKT_ALLOCATE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TIF_GREEDY_TCKT_ALLOCATE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_TIF_GREEDY_TCKT_ALLOCATE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_MEMARB_L1C_HASH 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_MEMARB_L1C_HASH_CHOICE0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_MEMARB_L1C_HASH_CHOICE1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_MEMARB_L1C_HASH_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RCT_FRA_SUPPORT 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RCT_FRA_SUPPORT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RCT_FRA_SUPPORT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_RCT_FRA_SUPPORT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_SPARE 31:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL_SPARE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2 0x00504660 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_CLR_TCKT_ON_RFA_STATUS 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_CLR_TCKT_ON_RFA_STATUS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_CLR_TCKT_ON_RFA_STATUS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_CLR_TCKT_ON_RFA_STATUS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_CLR_RAY_ON_RFA_STATUS 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_CLR_RAY_ON_RFA_STATUS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_CLR_RAY_ON_RFA_STATUS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_CLR_RAY_ON_RFA_STATUS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_CLR_L0_ON_RFA_STATUS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_CLR_L0_ON_RFA_STATUS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_CLR_L0_ON_RFA_STATUS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_CLR_L0_ON_RFA_STATUS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_FORCE_TTU_TIMEOUT 4:4 /* -WIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_FORCE_TTU_TIMEOUT_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_FORCE_TTU_TIMEOUT_INIT 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC1_WATERMARK 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC1_WATERMARK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC1_WATERMARK_MIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC1_WATERMARK_MAX 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC1_WATERMARK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC2_WATERMARK 11:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC2_WATERMARK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC2_WATERMARK_MIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC2_WATERMARK_MAX 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC2_WATERMARK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC3_WATERMARK 15:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC3_WATERMARK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC3_WATERMARK_MIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC3_WATERMARK_MAX 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC3_WATERMARK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC4_WATERMARK 19:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC4_WATERMARK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC4_WATERMARK_MIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC4_WATERMARK_MAX 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_RESRC4_WATERMARK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_SPARE 31:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_CTRL2_SPARE_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL 0x00504664 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_DBG0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_DBG1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_DBG2 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_SINGLE_PASS0 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_SINGLE_PASS1 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_STATIC_PATTERN0 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_STATIC_PATTERN1 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_SIGDUMP_DEBUG 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP25 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP26 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP27 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP28 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP29 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP30 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP31 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP32 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_GRP33 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_APM_GROUP_7 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_APM_GROUP_6 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_APM_GROUP_5 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_APM_GROUP_4 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_APM_GROUP_3 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_APM_GROUP_2 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_APM_GROUP_1 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_APM_GROUP_0 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_ENABLE 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TTU_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS 0x00504670 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SFE 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SFE_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SFE_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SFE_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SFE_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SFE_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SFE_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SFE_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL0 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL0_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL0_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL1 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL1_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_SCTL1_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C0 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C0_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C0_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C1 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C1_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_L1C1_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM0 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM0_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM0_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM1 20:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM1_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXAM1_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF0 23:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF0_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF0_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF1 26:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF1_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TEXDF1_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TTU 29:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TTU_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TTU_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TTU_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TTU_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TTU_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TTU_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_STATUS_TTU_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS 0x00504674 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA0 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA0_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA0_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA1 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA1_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_RFA1_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_SMGR 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_SMGR_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_SMGR_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_SMGR_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_SMGR_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_SMGR_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_SMGR_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_SMGR_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_MMISC 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_MMISC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_MMISC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_MMISC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_MMISC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_MMISC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_MMISC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_MMISC_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PFET 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PFET_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PFET_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PFET_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PFET_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PFET_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PFET_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PFET_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_ICC 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_ICC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_ICC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_ICC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_ICC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_ICC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_ICC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_ICC_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_GIF 20:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_GIF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_GIF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_GIF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_GIF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_GIF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_GIF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_GIF_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER0 23:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER0_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER0_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER1 26:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER1_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_SFE_STATUS_PROFILER1_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEX_CTRL 0x00504214 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEX_CTRL_TEXAM_BLCG_INPUT_CTRL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEX_CTRL_TEXAM_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEX_CTRL_TEXAM_BLCG_INPUT_CTRL_INCLUDE_RFA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEX_CTRL_TEXAM_BLCG_INPUT_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEX_CTRL_TEXDF_BLCG_INPUT_CTRL 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEX_CTRL_TEXDF_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEX_CTRL_TEXDF_BLCG_INPUT_CTRL_INCLUDE_RFA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEX_CTRL_TEXDF_BLCG_INPUT_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEX_CTRL_SPARE 31:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM_TEX_CTRL_SPARE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_STATUS0 0x00504680 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_STATUS0_SM_IN_TRAP_MODE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_STATUS0_SM_IN_TRAP_MODE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_STATUS0_LOCKED_DOWN 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_STATUS0_LOCKED_DOWN_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_STATUS0_LOCKED_DOWN_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0 0x00504684 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_DEBUGGER_MODE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_DEBUGGER_MODE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_SINGLE_STEP_MODE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_SINGLE_STEP_MODE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_SINGLE_STEP_MODE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW 10:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW_256 0x8 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW 14:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT 29:29 /* -WIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_INIT 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_RUN_TRIGGER 30:30 /* -WIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_RUN_TRIGGER_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_RUN_TRIGGER_TASK_INIT 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_STOP_TRIGGER 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_WARP_VALID_MASK_0 0x00504688 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_WARP_VALID_MASK_0_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_WARP_VALID_MASK_1 0x0050468c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_WARP_VALID_MASK_1_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_BPT_PAUSE_MASK_0 0x00504690 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_BPT_PAUSE_MASK_0_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_BPT_PAUSE_MASK_1 0x00504694 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_BPT_PAUSE_MASK_1_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_BPT_TRAP_MASK_0 0x00504698 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_BPT_TRAP_MASK_0_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_BPT_TRAP_MASK_1 0x0050469c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_DBGR_BPT_TRAP_MASK_1_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_0 0x005046a0 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_0_LO_VALUE 31:0 /* R-IUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_0_LO_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_0_TEX_IDX 19:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_0_COMPONENTS 26:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_0_VA_IN_PAGE 24:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_0_REQ_TYPE 27:27 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_0_REQ_TYPE_SURFTEX 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_0_REQ_TYPE_LG 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_1 0x005046a4 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_1_HI_VALUE 31:0 /* R-IUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_1_HI_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_1_D_SLOT_ID 9:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_1_MASK_ROTATE_RIGHT 11:10 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_1_MEMORY_LAYOUT 12:12 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_1_SZ_SWAP 15:13 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_1_KIND 23:16 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_ADDR_1_APERTURE 25:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK 0x005046a8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_NACK 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_ARRIVE 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_ARRIVE_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_REPORT_MASK_ARRIVE_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK 0x005046ac /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR 0x005046b0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_NONE 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_API_STACK_ERROR 0x0002 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_MISALIGNED_PC 0x0005 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_PC_OVERFLOW 0x0006 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_MISALIGNED_REG 0x0008 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_ENCODING 0x0009 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_PARAM 0x000b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_OOR_REG 0x000d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_OOR_ADDR 0x000e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_MISALIGNED_ADDR 0x000f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_INVALID_ADDR_SPACE 0x0010 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_INVALID_CONST_ADDR_LDC 0x0012 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_MMU_FAULT 0x0017 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_TEX_FORMAT 0x0018 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_TEX_LAYOUT 0x0019 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_MMU_NACK 0x0020 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ERROR_ARRIVE 0x0021 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_WARP_ID 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_WARP_ID_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE 27:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_NONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_OVERFLOW_ADDR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_OVERFLOW_ADDR 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_WINDOW_BTWN_HI_LO 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_LOCAL_WINDOW_BTWN_HI_LO 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_GLOBAL_MISALIGN_ADDR 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_LOCAL_MISALIGN_ADDR 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_SURF_OOR_ADDR 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_FAULT 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_FORMAT 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_LAYOUT 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_NACK 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_SHARED_OVERFLOW_ADDR 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_SHARED_MISALIGN_ADDR 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR 0x005046b4 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_BPT_INT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_BPT_INT_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_BPT_INT_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_BPT_PAUSE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_BPT_PAUSE_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_ERROR_IN_TRAP_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_ERROR_IN_TRAP_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_POISON_DATA 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_POISON_DATA_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_GLOBAL_ESR_POISON_DATA_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_PC 0x005046b8 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_PC_VALUE 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_PC_HI 0x005046bc /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_WARP_ESR_PC_HI_VALUE 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_PM_SAMP_STATE 0x005046c0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_PM_SAMP_STATE_SUBP0 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_PM_SAMP_STATE_SUBP0_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_PM_SAMP_STATE_SUBP1 11:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_PM_SAMP_STATE_SUBP1_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_PM_SAMP_STATE_SUBP2 17:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_PM_SAMP_STATE_SUBP2_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_PM_SAMP_STATE_SUBP3 23:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_PM_SAMP_STATE_SUBP3_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_PM_SAMP_STATE_CORE 25:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_PM_SAMP_STATE_CORE_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET 0x005046e0 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET_SR64_PREEMPTION_SAVE 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET_SR64_PREEMPTION_RESTORE 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET_OBSERVE_CYA_0 24:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET_OBSERVE_CYA_1 25:25 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET_OBSERVE_CYA_2 26:26 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET_OBSERVE_CYA_3 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET_OBSERVE_CYA_4 28:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET_OBSERVE_CYA_5 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET_OBSERVE_CYA_6 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET_OBSERVE_CYA_7 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET_OBSERVE_CYA_8 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_ESR_FET_OBSERVE_CYA_9 23:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS 0x005046e4 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTUALLY_QUIESCENT 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS 0x005046e8 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_HALTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_FAULTEDED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_INFO 0x005046ec /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_INFO_VEID 5:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SMS_HWW_ESR_INFO_VEID_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_STATUS0 0x00504700 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_STATUS0_SM_IN_TRAP_MODE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_STATUS0_SM_IN_TRAP_MODE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_STATUS0_LOCKED_DOWN 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_STATUS0_LOCKED_DOWN_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_STATUS0_LOCKED_DOWN_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0 0x00504704 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_DEBUGGER_MODE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_DEBUGGER_MODE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_SINGLE_STEP_MODE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_SINGLE_STEP_MODE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_SINGLE_STEP_MODE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW 10:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW_256 0x8 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW 14:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT 29:29 /* -WIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_INIT 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_RUN_TRIGGER 30:30 /* -WIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_RUN_TRIGGER_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_RUN_TRIGGER_TASK_INIT 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_STOP_TRIGGER 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_WARP_VALID_MASK_0 0x00504708 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_WARP_VALID_MASK_0_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_WARP_VALID_MASK_1 0x0050470c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_WARP_VALID_MASK_1_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_BPT_PAUSE_MASK_0 0x00504710 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_BPT_PAUSE_MASK_0_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_BPT_PAUSE_MASK_1 0x00504714 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_BPT_PAUSE_MASK_1_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_BPT_TRAP_MASK_0 0x00504718 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_BPT_TRAP_MASK_0_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_BPT_TRAP_MASK_1 0x0050471c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_DBGR_BPT_TRAP_MASK_1_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_0 0x00504720 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_0_LO_VALUE 31:0 /* R-IUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_0_LO_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_0_TEX_IDX 19:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_0_COMPONENTS 26:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_0_VA_IN_PAGE 24:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_0_REQ_TYPE 27:27 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_0_REQ_TYPE_SURFTEX 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_0_REQ_TYPE_LG 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_1 0x00504724 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_1_HI_VALUE 31:0 /* R-IUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_1_HI_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_1_D_SLOT_ID 9:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_1_MASK_ROTATE_RIGHT 11:10 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_1_MEMORY_LAYOUT 12:12 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_1_SZ_SWAP 15:13 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_1_KIND 23:16 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_ADDR_1_APERTURE 25:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK 0x00504728 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_NACK 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_ARRIVE 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_ARRIVE_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_REPORT_MASK_ARRIVE_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK 0x0050472c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR 0x00504730 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_NONE 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_API_STACK_ERROR 0x0002 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_MISALIGNED_PC 0x0005 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_PC_OVERFLOW 0x0006 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_MISALIGNED_REG 0x0008 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_ENCODING 0x0009 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_PARAM 0x000b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_OOR_REG 0x000d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_OOR_ADDR 0x000e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_MISALIGNED_ADDR 0x000f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_INVALID_ADDR_SPACE 0x0010 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_INVALID_CONST_ADDR_LDC 0x0012 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_MMU_FAULT 0x0017 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_TEX_FORMAT 0x0018 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_TEX_LAYOUT 0x0019 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_MMU_NACK 0x0020 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ERROR_ARRIVE 0x0021 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_WARP_ID 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_WARP_ID_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE 27:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_NONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_OVERFLOW_ADDR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_OVERFLOW_ADDR 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_WINDOW_BTWN_HI_LO 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_LOCAL_WINDOW_BTWN_HI_LO 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_GLOBAL_MISALIGN_ADDR 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_LOCAL_MISALIGN_ADDR 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_SURF_OOR_ADDR 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_FAULT 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_FORMAT 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_LAYOUT 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_NACK 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_SHARED_OVERFLOW_ADDR 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_SHARED_MISALIGN_ADDR 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR 0x00504734 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_BPT_INT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_BPT_INT_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_BPT_INT_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_BPT_PAUSE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_BPT_PAUSE_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_ERROR_IN_TRAP_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_ERROR_IN_TRAP_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_POISON_DATA 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_POISON_DATA_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_GLOBAL_ESR_POISON_DATA_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_PC 0x00504738 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_PC_VALUE 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_PC_HI 0x0050473c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_WARP_ESR_PC_HI_VALUE 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_PM_SAMP_STATE 0x00504740 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_PM_SAMP_STATE_SUBP0 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_PM_SAMP_STATE_SUBP0_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_PM_SAMP_STATE_SUBP1 11:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_PM_SAMP_STATE_SUBP1_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_PM_SAMP_STATE_SUBP2 17:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_PM_SAMP_STATE_SUBP2_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_PM_SAMP_STATE_SUBP3 23:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_PM_SAMP_STATE_SUBP3_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_PM_SAMP_STATE_CORE 25:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_PM_SAMP_STATE_CORE_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET 0x00504760 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET_SR64_PREEMPTION_SAVE 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET_SR64_PREEMPTION_RESTORE 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET_OBSERVE_CYA_0 24:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET_OBSERVE_CYA_1 25:25 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET_OBSERVE_CYA_2 26:26 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET_OBSERVE_CYA_3 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET_OBSERVE_CYA_4 28:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET_OBSERVE_CYA_5 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET_OBSERVE_CYA_6 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET_OBSERVE_CYA_7 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET_OBSERVE_CYA_8 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_ESR_FET_OBSERVE_CYA_9 23:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS 0x00504764 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTUALLY_QUIESCENT 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS 0x00504768 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_HALTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_FAULTEDED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_INFO 0x0050476c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_INFO_VEID 5:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_SM0_HWW_ESR_INFO_VEID_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG 0x00504200 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_HEADER_TAGMODE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_HEADER_TAGMODE_AUTO 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_HEADER_TAGMODE_MISS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_SAMPLER_TAGMODE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_SAMPLER_TAGMODE_AUTO 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_SAMPLER_TAGMODE_MISS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FORCE_INVALIDATE 10:10 /* -WIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FORCE_INVALIDATE_RESET 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FORCE_INVALIDATE_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_TSL1_ENTRIES 15:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_TSL1_ENTRIES_FULL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_ZERO_OFFSET_OPT 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_ZERO_OFFSET_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_ZERO_OFFSET_OPT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_INVAL_3D_TSL1_ON_TEX_IN_2D 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_INVAL_3D_TSL1_ON_TEX_IN_2D_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_INVAL_3D_TSL1_ON_TEX_IN_2D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_TSL1_RVCH_INVALIDATE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_TSL1_RVCH_INVALIDATE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_TSL1_RVCH_INVALIDATE__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_SURFACE_USE_FAST_POINT_SAMPLE_PATH 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_SURFACE_USE_FAST_POINT_SAMPLE_PATH_ENABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_SURFACE_USE_FAST_POINT_SAMPLE_PATH_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_SNORM 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_SNORM_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_SNORM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_FP16_RETURN 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_FP16_RETURN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_FP16_RETURN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_ARRAY 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_ARRAY_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_ARRAY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_MIP_FILTER 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_MIP_FILTER_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_MIP_FILTER_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_BORDER_COLOR 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_BORDER_COLOR_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_BORDER_COLOR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_CACHE_LAYOUT 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_CACHE_LAYOUT_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_CACHE_LAYOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_1D_BUFFER 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_1D_BUFFER_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_1D_BUFFER_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_COLOR_KEY_OP 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_COLOR_KEY_OP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_COLOR_KEY_OP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG 0x00504204 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_CUBEMAP_ANISO 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_CUBEMAP_ANISO_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_CUBEMAP_ANISO_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_CUBESEAM_ANISO 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_CUBESEAM_ANISO_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_CUBESEAM_ANISO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_UNOPT_LOD_CLAMP 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_UNOPT_LOD_CLAMP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_UNOPT_LOD_CLAMP_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_SERIALIZE_TXL 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_SERIALIZE_TXL_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_SERIALIZE_TXL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_SERIALIZE_TXB 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_SERIALIZE_TXB_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_SERIALIZE_TXB_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_SERIALIZE_LC 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_SERIALIZE_LC_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_LOD_DBG_SERIALIZE_LC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG 0x00504208 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_NOP_OPT 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_NOP_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_NOP_OPT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_SAMPSTAT 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_SAMPSTAT_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_SAMPSTAT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_UNOPT_LOD_SPREAD 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_UNOPT_LOD_SPREAD_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_UNOPT_LOD_SPREAD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_COMPATIBILITY_PRECISION 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_COMPATIBILITY_PRECISION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_COMPATIBILITY_PRECISION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_FILTER_64B 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_FILTER_64B_FULL_SPEED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_FILTER_64B_HALF_SPEED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_FILTER_64B_ANISO_HALF_SPEED 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_W_WEIGHT_CG_OPT 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_W_WEIGHT_CG_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_DBG_W_WEIGHT_CG_OPT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL 0x005042b0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_SINGLE_PASS0 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_SINGLE_PASS_COMPUTE 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_STATIC_PATTERN0 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_STATIC_PATTERN1 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_SINGLE_PASS1 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_GRP28 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_APM_GROUP_7 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_APM_GROUP_6 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_APM_GROUP_5 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_APM_GROUP_4 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_APM_GROUP_3 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_APM_GROUP_2 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_APM_GROUP_1 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_APM_GROUP_0 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_ENABLE 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG 0x0050420c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SUBSET_PICK 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SUBSET_PICK_AUTO 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SUBSET_PICK_ZERO 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SUBSET_PICK_ZERO_TO_ONE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_1B 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_1B_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_2B 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_2B_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_4B 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_4B_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_8B 11:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_8B_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_12B 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_12B_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_16B 15:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_16B_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_DXT1 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_DXT1_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_DXT2 19:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_SETFUNC_DXT2_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_T2D_COMPRESSION 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_T2D_COMPRESSION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_T2D_COMPRESSION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_RLAT_DEPTH_DIV8 26:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_DBG_RLAT_DEPTH_DIV8_FULL 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_DBG 0x00504210 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_DBG_LATFIFO_DEPTH_DIV4 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_DBG_LATFIFO_DEPTH_DIV4_FULL 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG 0x0050421c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_ROWCOL_SERIAL 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_ROWCOL_SERIAL_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_ROWCOL_SERIAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_BANK_SERIAL 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_BANK_SERIAL_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_BANK_SERIAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_CONVERT_NEAREST_AS_TLD 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_CONVERT_NEAREST_AS_TLD_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_CONVERT_NEAREST_AS_TLD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_CONVERT_NEAREST_AS_TLD__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_FILTER_64B 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_FILTER_64B_FULL_SPEED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_FILTER_64B_HALF_SPEED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_FILTER_64B_ANISO_HALF_SPEED 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_COMPUTE_CONVERT_NEAREST_AS_TLD 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_COMPUTE_CONVERT_NEAREST_AS_TLD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_COMPUTE_CONVERT_NEAREST_AS_TLD_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_CACHE_QUIET_READ 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_CACHE_QUIET_READ_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_CACHE_QUIET_READ_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_SLCG_OVERRIDE 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_SLCG_OVERRIDE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_SLCG_OVERRIDE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_SLCG_IDLE_EN 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_SLCG_IDLE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_SLCG_IDLE_EN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_SLCG_STALL_EN 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_SLCG_STALL_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_SLCG_STALL_EN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_LG_EXPAND_BILERP 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_LG_EXPAND_BILERP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_DBG_LG_EXPAND_BILERP_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x005042cc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG 0x00504220 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_DRN_SUBP_OLDEST_BLOCK 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_DRN_SUBP_OLDEST_BLOCK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_DRN_SUBP_OLDEST_BLOCK_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_CP_DRNLOCK 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_CP_DRNLOCK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_CP_DRNLOCK_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_CP2_BOOST 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_CP2_BOOST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_CP2_BOOST_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_CP3_BOOST 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_CP3_BOOST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_CP3_BOOST_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_CP4_RECYCLE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_CP4_RECYCLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_CP4_RECYCLE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_NONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_2 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_8 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_16 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_24 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_32 0x5 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_64 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_128 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_FB_SECTOR_SERIAL 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_FB_SECTOR_SERIAL_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_FB_SECTOR_SERIAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_MIW_READ_PACKING_EN 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_MIW_READ_PACKING_EN_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_MIW_READ_PACKING_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_ONLY_ONE_FB_REQ 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_ONLY_ONE_FB_REQ_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_ONLY_ONE_FB_REQ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_L1TAG_DESC_EVICT_LAST 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_L1TAG_DESC_EVICT_LAST_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_L1TAG_DESC_EVICT_LAST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_INJECT_MEMBAR_PRIORITY 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_INJECT_MEMBAR_PRIORITY_HIGH 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_INJECT_MEMBAR_PRIORITY_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_FB_STENCIL_SERIAL 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_FB_STENCIL_SERIAL_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_FB_STENCIL_SERIAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_L1TAG_CTRL_CACHE_TTU 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_L1TAG_CTRL_CACHE_TTU_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_L1TAG_CTRL_CACHE_TTU_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_MIW_WRITE_CONCAT_EN 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_MIW_WRITE_CONCAT_EN_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_MIW_WRITE_CONCAT_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_MEMBAR_SYNC_IN_L1MISS 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_MEMBAR_SYNC_IN_L1MISS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_MEMBAR_SYNC_IN_L1MISS_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_NACK_RESP 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_NACK_RESP_KILL_ALL_BUT_MEMBAR_CORRECT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_NACK_RESP_KILL_ALL_CORRECT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_SCO_GPU_AS_STRONG 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_SCO_GPU_AS_STRONG_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_SCO_GPU_AS_STRONG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE 20:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE_OUT_OF_ORD 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE_TEXLG_LH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE_TEXLG_TQ01 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE_IN_ORDER 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_FPS_TEXTLD_AS_SURF 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_FPS_TEXTLD_AS_SURF_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_FPS_TEXTLD_AS_SURF_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_GNIC_POISON_IGNORE 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_GNIC_POISON_IGNORE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_GNIC_POISON_IGNORE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_SLCG_OVERRIDE 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_SLCG_OVERRIDE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_SLCG_OVERRIDE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_SLCG_IDLE_EN 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_SLCG_IDLE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_SLCG_IDLE_EN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_SLCG_STALL_EN 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_SLCG_STALL_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_SLCG_STALL_EN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_MIW_READ_CMD_HOLDOFF 30:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_MIW_READ_CMD_HOLDOFF_ZERO 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG_MIW_READ_CMD_HOLDOFF_INIT 0x07 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG2 0x0050423c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG2_L1TAG_DESC_INVERT_MASK 23:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG2_L1TAG_DESC_INVERT_MASK_DEFAULT 0x3718d /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG2_L1TAG_DESC_INVERT_MASK_GA100 0x3718d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG2_MIW_PAUSED_OVERRIDE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG2_MIW_PAUSED_OVERRIDE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_DBG2_MIW_PAUSED_OVERRIDE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_ROUTING 0x005042c4 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_ROUTING_SEL 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_ROUTING_SEL_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_ROUTING_SEL_PIPE0 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_ROUTING_SEL_PIPE1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_ROUTING_SEL__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE 0x005042c8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE_LG 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE_LG_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE_LG_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE_TEX 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE_TEX_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE_TEX_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE_RESET_L1 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE_RESET_L1_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE_RESET_L1_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE_CBUF_FLUSH 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE_CBUF_FLUSH_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_T_DBG2_L1_DATA_INVALIDATE_CBUF_FLUSH_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_DBG 0x00504230 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_DBG_MADD_64B_LANA_CYA 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_DBG_MADD_64B_LANA_CYA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_DBG_MADD_64B_LANA_CYA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_DBG_FP16_ROUNDING_MODE 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_DBG_FP16_ROUNDING_MODE_INSTR 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_DBG_FP16_ROUNDING_MODE_FORCE_RTZ 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_DBG_FP16_ROUNDING_MODE_FORCE_RTNE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_DBG_PS_BYPASS 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_DBG_PS_BYPASS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_DBG_PS_BYPASS_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x00504238 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TEXIN 10:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_F 13:11 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_F_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_F_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_F_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_F_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_F_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_D 16:14 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_D_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_D_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_D_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_D_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_D_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TM 19:17 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TM_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TM_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TM_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TM_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TM_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_X 22:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_X_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_X_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_X_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_X_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_X_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TEXIO 25:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_W 28:26 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_W_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_W_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_W_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_W_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_W_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_MIPB 31:29 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_MIPB_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_MIPB_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_MIPB_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_MIPB_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS_MIPB_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACT_INDEX 0x005042a8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACT_INDEX__PRIV_LEVEL_MASK 0x005042cc /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACT_INDEX_INDEX 7:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACT_INDEX_INDEX_ZERO 0x00 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACT_INDEX_INDEX_MIN 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACT_INDEX_INDEX_MAX 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACT_DATA 0x005042ac /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACT_DATA__PRIV_LEVEL_MASK 0x005042cc /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACT_DATA__APERTURE_INDEX_OFFSET 0xfffffffc /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACT_DATA_DATA 27:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_BLK_ACT_DATA_DATA_INIT 0x0000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_0 0x00504600 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_0_BASE_ADDR_43_12 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_0_BASE_ADDR_43_12_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_1 0x00504604 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_1_SIZE_DIV_128B 20:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_1_SIZE_DIV_128B_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_1_SIZE_DIV_128B_GRANULARITY 0x000080 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_1_BASE_ADDR_48_44 28:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_1_BASE_ADDR_48_44_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_1_LTC_CLASS 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_1_LTC_CLASS_PASS_THRU 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_1_LTC_CLASS_EVICT_LAST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_1_VALID 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_1_VALID_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_RM_CB_1_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG 0x00504240 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG1 0x00504244 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG1_SLCG 3:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG1_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG1_SLCG_DISABLED 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IN_CG1_SLCG__PROD 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG 0x00504248 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG1 0x0050424c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_SAMP_CG1_SLCG__PROD 0xfc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG 0x00504250 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG1 0x00504254 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG1_SLCG 5:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG1_SLCG_DISABLED 0x1f /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_X_CG1_SLCG__PROD 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG 0x00504258 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG1 0x0050425c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG1_SLCG 3:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG1_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG1_SLCG_DISABLED 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_W_CG1_SLCG__PROD 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG 0x00504260 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG1 0x00504264 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_D_CG1_SLCG__PROD 0xd3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG 0x00504268 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG1 0x0050426c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_IO_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG 0x00504278 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG1 0x0050427c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG1_SLCG 5:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG1_SLCG_DISABLED 0x1f /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_F_CG1_SLCG__PROD 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG 0x00504280 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG1 0x00504284 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG1_SLCG 3:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG1_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG1_SLCG_DISABLED 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_MIPB_CG1_SLCG__PROD 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG 0x00504270 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_IDLE_CG_DLY_CNT__PROD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_STALL_CG_DLY_CNT__PROD 0x05 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG1 0x00504274 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_AM_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG 0x00504288 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_IDLE_CG_DLY_CNT__PROD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_STALL_CG_DLY_CNT__PROD 0x05 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG1 0x0050428c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_TEX_DF_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC 0x0050447f:0x00504400 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG 0x00504400 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_SINGLE_ISBE_ALLOC 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_SINGLE_ISBE_ALLOC_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_SINGLE_ISBE_ALLOC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_BUNDLE_FILTER 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_BUNDLE_FILTER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_BUNDLE_FILTER_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_SET_COUNTERS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_SET_COUNTERS_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_SET_COUNTERS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_VSB_ISBE_SHARED 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_VSB_ISBE_SHARED_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_VSB_ISBE_SHARED_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_CYA_RESET_ISBE_BASE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_CYA_RESET_ISBE_BASE_ENABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_CYA_RESET_ISBE_BASE_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_FORCE_GLOBAL_CACHE 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_FORCE_GLOBAL_CACHE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_FORCE_GLOBAL_CACHE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_FORCE_GLOBAL_CACHE_USE_SPH 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_OCCUPANCY_SEL 10:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_OCCUPANCY_SEL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_OCCUPANCY_SEL_PIX_QUADS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_OCCUPANCY_SEL_PIX_DRAIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_OCCUPANCY_SEL_OVERALL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_OCCUPANCY_SEL_UNDEFINED 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_SPARE 31:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_DEBUG_SPARE_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG 0x00504404 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SINGLE_CTA 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SINGLE_CTA_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SINGLE_CTA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_PIXOUT_FPW_ILOCK 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_PIXOUT_FPW_ILOCK_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_PIXOUT_FPW_ILOCK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_COMP_BUNDLE_HOLD 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_COMP_BUNDLE_HOLD_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_COMP_BUNDLE_HOLD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_PIX_BUNDLE_HOLD 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_PIX_BUNDLE_HOLD_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_PIX_BUNDLE_HOLD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_ISC_INSTRUCTION 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_ISC_INSTRUCTION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_ISC_INSTRUCTION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_ISC_DATA 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_ISC_DATA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_ISC_DATA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_ISC_CONSTANT 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_ISC_CONSTANT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SCG_ISC_CONSTANT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_CTA_STEERING 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_CTA_STEERING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_CTA_STEERING_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_FORCE_GLOBAL_CACHE 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_FORCE_GLOBAL_CACHE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_FORCE_GLOBAL_CACHE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_FORCE_GLOBAL_CACHE_USE_SPH 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_CTA_QUAD_SKEW 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_CTA_QUAD_SKEW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_CTA_QUAD_SKEW_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_FIRST_SAMP_CENTROID 12:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_FIRST_SAMP_CENTROID_COVERED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_FIRST_SAMP_CENTROID_ALIASED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_FIRST_SAMP_CENTROID_ALWAYS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_CTA_SUBPARTITION_SKEW 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_CTA_SUBPARTITION_SKEW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_CTA_SUBPARTITION_SKEW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_FORCE_PFM_PFC_WORK_TO_ONE_SM 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_FORCE_PFM_PFC_WORK_TO_ONE_SM_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_FORCE_PFM_PFC_WORK_TO_ONE_SM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_2D_3DPFM_SUBTILES_MAX_IN_FLIGHT 21:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_2D_3DPFM_SUBTILES_MAX_IN_FLIGHT_DISABLE 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SPARE 31:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_DEBUG_SPARE_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG 0x00504408 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_USE_HALF_SM 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_USE_HALF_SM_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_USE_HALF_SM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_PIX_VTG_ARB_POLICY 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_PIX_VTG_ARB_POLICY_PIX_HIGHEST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_PIX_VTG_ARB_POLICY_VTG_CREDIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_PIX_VTG_ARB_POLICY_LOOSE_PS_TILE_LOCK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_BUG1693549_FIX 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_BUG1693549_FIX_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_BUG1693549_FIX_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_BUG1693549_STALL_COUNTER 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_BUG1693549_STALL_COUNTER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_BUG1693549_STALL_COUNTER_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING_WINDOW_SIZE_15 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING_WINDOW_SIZE_63 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING_WINDOW_SIZE_1023 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_VTG_WINDOW_ADJUST 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_VTG_WINDOW_ADJUST_AGGRESSIVE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_VTG_WINDOW_ADJUST_CONSERVATIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_PIX_WINDOW_ADJUST 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_PIX_WINDOW_ADJUST_AGGRESSIVE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_PIX_WINDOW_ADJUST_CONSERVATIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_CNT_SAT_POLICY 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_CNT_SAT_POLICY_STALL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_CNT_SAT_POLICY_NO_SQUASH_ONCE_SAT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_OPEN_2D_BLOCKS_COMP 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_OPEN_2D_BLOCKS_COMP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_OPEN_2D_BLOCKS_COMP_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_2D_COMP_MUTEX_IN_SM 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_2D_COMP_MUTEX_IN_SM_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_2D_COMP_MUTEX_IN_SM_DISABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_SPARE 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_DEBUG_SPARE_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL 0x0050440c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_STATUS_BLOCK 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_STATUS_SUBUNIT_0 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_STATUS_SUBUNIT_1 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PRI_PIX_OUTSTANDING 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PRI_VTG_OUTSTANDING_0 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PRI_VTG_OUTSTANDING_1 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_STATUS_CG_PG_WAKEUP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_EXT_IFC_0 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_EXT_IFC_1 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_EXT_IFC_2 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_EXT_IFC_3 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_FULL_FIFOS_0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_FULL_FIFOS_1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_FULL_FIFOS_2 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_INTERNAL_PVLD_PRDY_0 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_INTERNAL_PVLD_PRDY_1 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_3 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_4 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_5 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_ATTRIBUTES_REQUESTED_DIV4 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIXEL_RF_ALLOCATIONS 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_NUMBER_OF_SUBTILES_PRIMS_PIXEL_WARPS 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_VTG_THROUGHPUT_0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_VTG_THROUGHPUT_1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_WARP_LAUNCHES_0 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_WARP_LAUNCHES_1 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_WARP_LAUNCHES_2 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_COMPUTE_LAUNCHES 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_COMPUTE_RF_DIV8_ALLOCATED 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_ACTIVE_QUADS_IN_PIX_WARPS 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_0 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_1 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_2 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_3 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_WORK_REMOVAL_0 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_STALL_LIMIT_0 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_STALL_LIMIT_1 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_STALL_LIMIT_2 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_STALL_LIMIT_3 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIX_PIPE_STALL_WLU 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIX_PIPE_STALL_LAUNCH 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIX_PIPE_STALL_INPUT 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIX_PIPE_STALL_TRAM 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIX_DRAIN_OUTSTANDING_0 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIX_DRAIN_OUTSTANDING_1 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIX_DRAIN_OUTSTANDING_2 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIX_DRAIN_OUTSTANDING_3 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIX_STARTXY_OUTSTANDING 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIX_TRAMFILL_OUTSTANDING 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_RESOURCE_LIMIT_0 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_RESOURCE_LIMIT_1 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_INTERNAL_EVENTS_0 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_LATENCY_TRACKING_INTERNAL 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_0 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SM_RESOURCES_1 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_2 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SM_RESOURCES_3 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_4 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_5 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_6 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_7 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_8 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_9 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_10 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SM_RESOURCES_11 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_12 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_13 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_14 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_15 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_16 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SM_SHADER_TYPE_ACTIVE 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_ALPHA_BETA_CLOCKS 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_FIFOS_STALL_0 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_FIFOS_STALL_1 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_FIFOS_STALL_2 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_FIFOS_STALL_3 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_TPC_RESOURCES_0 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_TPC_RESOURCES_1 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_TPC_RESOURCES_3 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_TPC_RESOURCES_4 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_COMPUTE_PIPE_DEBUG_0_2XMIO 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_COMPUTE_PIPE_DEBUG_1_2XMIO 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_COMPUTE_PIPE_DEBUG_2_2XMIO 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_EXTERNAL_SCG_EVENTS 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_ACTIVE_WARP_OCCUPANCY_0 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_ACTIVE_WARP_OCCUPANCY_1 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_ACTIVE_WARP_OCCUPANCY_2 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_ACTIVE_WARP_OCCUPANCY_3 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_VTG_ISBE_OCCUPANCY 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIX_TRAM_OCCUPANCY 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_COMP_FSM_BLOCK_0 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_COMP_FSM_BLOCK_1 0x5e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_COMP_LAUNCH 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_STATIC_PATTERN_123_12_GROUP 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_STATIC_PATTERN_EDC_12_GROUP 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_CILP 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PREFUNC_LATENCIES_0 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PREFUNC_LATENCIES_1 0x64 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PREFUNC_LATENCIES_2 0x65 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PREFUNC_LATENCIES_3 0x66 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_MPC_SCG_DRAIN_GRAPHICS_PROTOCOL 0x67 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIXOUT_IF 0x68 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIXOUT_CANT_DRAIN_REASONS 0x69 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_PIX_COMP_ARB 0x6a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SCG_OCCUPANCY_0 0x6b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SCG_OCCUPANCY_1 0x6c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SCG_OCCUPANCY_2 0x6d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_ENHANCED_L1_0 0x6e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_ENHANCED_L1_1 0x6f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_INTERNAL_EVENTS_1 0x70 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_ARB 0x71 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_0 0x72 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_1 0x73 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_0 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_1 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_2 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_3 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_4 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_5 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_6 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_7 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_8 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_9 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_10 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_11 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_12 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_13 0x81 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_MESHLET_1 0x82 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_MESHLET_2 0x83 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_RMGR_DEBUG_1 0x84 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_RMGR_DEBUG_2 0x85 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_RMGR_DEBUG_3 0x86 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_WLU_ARB_DEBUG 0x87 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_COMPUTE_PERF_TRIAGE_0 0x88 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_COMPUTE_PERF_TRIAGE_1 0x89 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_COMPUTE_PERF_TRIAGE_2 0x8a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SM_PERF_RELATED 0x8b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_0 0x8c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_1 0x8d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_2 0x8e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_3 0x8f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_4 0x90 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_5 0x91 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_6 0x92 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_7 0x93 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_8 0x94 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_9 0x95 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_10 0x96 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_11 0x97 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_12 0x98 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_13 0x99 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_14 0x9a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_15 0x9b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_16 0x9c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_17 0x9d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_18 0x9e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_19 0x9f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_20 0xa0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_14 0xa1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_21 0xa2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_SPASS_0 0xa3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_SPASS_1 0xa4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_SMSCC_SPASS_2 0xa5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_2 0xa6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_3 0xa7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_4 0xa8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_5 0xa9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_APM_GRP_0 0xff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_APM_GRP_1 0xfe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_APM_GRP_2 0xfd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_APM_GRP_3 0xfc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_APM_GRP_4 0xfb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_APM_GRP_5 0xfa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_APM_GRP_6 0xf9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_APM_GRP_7 0xf8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_APM_GRP_8 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_APM_GRP_9 0xf6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_APM_GRP_10 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_APM_GRP_11 0xf4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_STATUS_BLOCK 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_STATUS_SUBUNIT_0 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_STATUS_SUBUNIT_1 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PRI_PIX_OUTSTANDING 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PRI_VTG_OUTSTANDING_0 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PRI_VTG_OUTSTANDING_1 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_STATUS_CG_PG_WAKEUP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_EXT_IFC_0 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_EXT_IFC_1 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_EXT_IFC_2 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_EXT_IFC_3 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_FULL_FIFOS_0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_FULL_FIFOS_1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_FULL_FIFOS_2 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_INTERNAL_PVLD_PRDY_0 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_INTERNAL_PVLD_PRDY_1 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_3 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_4 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_5 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_ATTRIBUTES_REQUESTED_DIV4 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIXEL_RF_ALLOCATIONS 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_NUMBER_OF_SUBTILES_PRIMS_PIXEL_WARPS 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_VTG_THROUGHPUT_0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_VTG_THROUGHPUT_1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_WARP_LAUNCHES_0 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_WARP_LAUNCHES_1 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_WARP_LAUNCHES_2 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_COMPUTE_LAUNCHES 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_COMPUTE_RF_DIV8_ALLOCATED 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_ACTIVE_QUADS_IN_PIX_WARPS 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_0 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_1 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_2 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_3 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_WORK_REMOVAL_0 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_STALL_LIMIT_0 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_STALL_LIMIT_1 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_STALL_LIMIT_2 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_STALL_LIMIT_3 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIX_PIPE_STALL_WLU 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIX_PIPE_STALL_LAUNCH 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIX_PIPE_STALL_INPUT 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIX_PIPE_STALL_TRAM 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIX_DRAIN_OUTSTANDING_0 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIX_DRAIN_OUTSTANDING_1 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIX_DRAIN_OUTSTANDING_2 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIX_DRAIN_OUTSTANDING_3 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIX_STARTXY_OUTSTANDING 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIX_TRAMFILL_OUTSTANDING 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_RESOURCE_LIMIT_0 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_RESOURCE_LIMIT_1 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_INTERNAL_EVENTS_0 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_LATENCY_TRACKING_INTERNAL 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_0 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SM_RESOURCES_1 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_2 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SM_RESOURCES_3 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_4 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_5 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_6 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_7 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_8 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_9 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_10 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SM_RESOURCES_11 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_12 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_13 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_14 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_15 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_16 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SM_SHADER_TYPE_ACTIVE 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_ALPHA_BETA_CLOCKS 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_FIFOS_STALL_0 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_FIFOS_STALL_1 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_FIFOS_STALL_2 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_FIFOS_STALL_3 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_TPC_RESOURCES_0 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_TPC_RESOURCES_1 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_TPC_RESOURCES_3 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_TPC_RESOURCES_4 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_COMPUTE_PIPE_DEBUG_0_2XMIO 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_COMPUTE_PIPE_DEBUG_1_2XMIO 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_COMPUTE_PIPE_DEBUG_2_2XMIO 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_EXTERNAL_SCG_EVENTS 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_ACTIVE_WARP_OCCUPANCY_0 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_ACTIVE_WARP_OCCUPANCY_1 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_ACTIVE_WARP_OCCUPANCY_2 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_ACTIVE_WARP_OCCUPANCY_3 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_VTG_ISBE_OCCUPANCY 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIX_TRAM_OCCUPANCY 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_COMP_FSM_BLOCK_0 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_COMP_FSM_BLOCK_1 0x5e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_COMP_LAUNCH 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_STATIC_PATTERN_123_12_GROUP 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_STATIC_PATTERN_EDC_12_GROUP 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_CILP 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PREFUNC_LATENCIES_0 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PREFUNC_LATENCIES_1 0x64 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PREFUNC_LATENCIES_2 0x65 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PREFUNC_LATENCIES_3 0x66 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_MPC_SCG_DRAIN_GRAPHICS_PROTOCOL 0x67 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIXOUT_IF 0x68 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIXOUT_CANT_DRAIN_REASONS 0x69 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_PIX_COMP_ARB 0x6a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SCG_OCCUPANCY_0 0x6b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SCG_OCCUPANCY_1 0x6c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SCG_OCCUPANCY_2 0x6d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_ENHANCED_L1_0 0x6e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_ENHANCED_L1_1 0x6f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_INTERNAL_EVENTS_1 0x70 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_ARB 0x71 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_0 0x72 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_1 0x73 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_0 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_1 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_2 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_3 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_4 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_5 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_6 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_7 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_8 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_9 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_10 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_11 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_12 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_13 0x81 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_MESHLET_1 0x82 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_MESHLET_2 0x83 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_RMGR_DEBUG_1 0x84 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_RMGR_DEBUG_2 0x85 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_RMGR_DEBUG_3 0x86 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_WLU_ARB_DEBUG 0x87 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_COMPUTE_PERF_TRIAGE_0 0x88 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_COMPUTE_PERF_TRIAGE_1 0x89 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_COMPUTE_PERF_TRIAGE_2 0x8a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SM_PERF_RELATED 0x8b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_0 0x8c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_1 0x8d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_2 0x8e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_3 0x8f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_4 0x90 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_5 0x91 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_6 0x92 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_7 0x93 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_8 0x94 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_9 0x95 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_10 0x96 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_11 0x97 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_12 0x98 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_13 0x99 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_14 0x9a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_15 0x9b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_16 0x9c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_17 0x9d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_18 0x9e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_19 0x9f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_20 0xa0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_14 0xa1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_21 0xa2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_SPASS_0 0xa3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_SPASS_1 0xa4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_SMSCC_SPASS_2 0xa5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_2 0xa6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_3 0xa7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_4 0xa8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_5 0xa9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_APM_GRP_0 0xff /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_APM_GRP_1 0xfe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_APM_GRP_2 0xfd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_APM_GRP_3 0xfc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_APM_GRP_4 0xfb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_APM_GRP_5 0xfa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_APM_GRP_6 0xf9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_APM_GRP_7 0xf8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_APM_GRP_8 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_APM_GRP_9 0xf6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_APM_GRP_10 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_APM_GRP_11 0xf4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_STATUS_BLOCK 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_STATUS_SUBUNIT_0 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_STATUS_SUBUNIT_1 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PRI_PIX_OUTSTANDING 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PRI_VTG_OUTSTANDING_0 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PRI_VTG_OUTSTANDING_1 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_STATUS_CG_PG_WAKEUP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_EXT_IFC_0 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_EXT_IFC_1 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_EXT_IFC_2 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_EXT_IFC_3 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_FULL_FIFOS_0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_FULL_FIFOS_1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_FULL_FIFOS_2 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_INTERNAL_PVLD_PRDY_0 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_INTERNAL_PVLD_PRDY_1 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_3 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_4 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_5 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_ATTRIBUTES_REQUESTED_DIV4 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIXEL_RF_ALLOCATIONS 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_NUMBER_OF_SUBTILES_PRIMS_PIXEL_WARPS 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_VTG_THROUGHPUT_0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_VTG_THROUGHPUT_1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_WARP_LAUNCHES_0 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_WARP_LAUNCHES_1 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_WARP_LAUNCHES_2 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_COMPUTE_LAUNCHES 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_COMPUTE_RF_DIV8_ALLOCATED 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_ACTIVE_QUADS_IN_PIX_WARPS 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_0 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_1 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_2 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_3 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_WORK_REMOVAL_0 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_STALL_LIMIT_0 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_STALL_LIMIT_1 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_STALL_LIMIT_2 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_STALL_LIMIT_3 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIX_PIPE_STALL_WLU 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIX_PIPE_STALL_LAUNCH 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIX_PIPE_STALL_INPUT 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIX_PIPE_STALL_TRAM 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIX_DRAIN_OUTSTANDING_0 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIX_DRAIN_OUTSTANDING_1 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIX_DRAIN_OUTSTANDING_2 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIX_DRAIN_OUTSTANDING_3 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIX_STARTXY_OUTSTANDING 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIX_TRAMFILL_OUTSTANDING 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_RESOURCE_LIMIT_0 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_RESOURCE_LIMIT_1 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_INTERNAL_EVENTS_0 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_LATENCY_TRACKING_INTERNAL 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_0 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SM_RESOURCES_1 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_2 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SM_RESOURCES_3 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_4 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_5 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_6 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_7 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_8 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_9 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_10 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SM_RESOURCES_11 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_12 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_13 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_14 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_15 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_16 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SM_SHADER_TYPE_ACTIVE 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_ALPHA_BETA_CLOCKS 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_FIFOS_STALL_0 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_FIFOS_STALL_1 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_FIFOS_STALL_2 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_FIFOS_STALL_3 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_TPC_RESOURCES_0 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_TPC_RESOURCES_1 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_TPC_RESOURCES_3 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_TPC_RESOURCES_4 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_COMPUTE_PIPE_DEBUG_0_2XMIO 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_COMPUTE_PIPE_DEBUG_1_2XMIO 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_COMPUTE_PIPE_DEBUG_2_2XMIO 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_EXTERNAL_SCG_EVENTS 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_ACTIVE_WARP_OCCUPANCY_0 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_ACTIVE_WARP_OCCUPANCY_1 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_ACTIVE_WARP_OCCUPANCY_2 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_ACTIVE_WARP_OCCUPANCY_3 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_VTG_ISBE_OCCUPANCY 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIX_TRAM_OCCUPANCY 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_COMP_FSM_BLOCK_0 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_COMP_FSM_BLOCK_1 0x5e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_COMP_LAUNCH 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_STATIC_PATTERN_123_12_GROUP 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_STATIC_PATTERN_EDC_12_GROUP 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_CILP 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PREFUNC_LATENCIES_0 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PREFUNC_LATENCIES_1 0x64 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PREFUNC_LATENCIES_2 0x65 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PREFUNC_LATENCIES_3 0x66 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_MPC_SCG_DRAIN_GRAPHICS_PROTOCOL 0x67 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIXOUT_IF 0x68 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIXOUT_CANT_DRAIN_REASONS 0x69 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_PIX_COMP_ARB 0x6a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SCG_OCCUPANCY_0 0x6b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SCG_OCCUPANCY_1 0x6c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SCG_OCCUPANCY_2 0x6d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_ENHANCED_L1_0 0x6e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_ENHANCED_L1_1 0x6f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_INTERNAL_EVENTS_1 0x70 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_ARB 0x71 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_GENERAL_PERF_TRIAGE_0 0x72 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_GENERAL_PERF_TRIAGE_1 0x73 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_0 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_1 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_2 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_3 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_4 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_5 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_6 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_7 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_8 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_9 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_10 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_11 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_12 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_13 0x81 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_MESHLET_1 0x82 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_MESHLET_2 0x83 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_RMGR_DEBUG_1 0x84 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_RMGR_DEBUG_2 0x85 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_RMGR_DEBUG_3 0x86 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_WLU_ARB_DEBUG 0x87 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_COMPUTE_PERF_TRIAGE_0 0x88 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_SM_PERF_RELATED 0x89 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_ENABLE 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM0_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_ENABLE 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_SM1_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_ENABLE 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_TPC_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PM_CTRL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_STATUS 0x00504410 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_STATUS_TOP_STATUS 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_STATUS_VTG_STATUS 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_STATUS_PIX_STATUS 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_STATUS_WLU_STATUS 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_STATUS_COMP_STATUS 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_STATUS_RMGR_STATUS 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS 0x00504414 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_ALPHA_STATUS 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_BETA_STATUS 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_ISBMGR0_STATUS 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_ISBMGR1_STATUS 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_SMIO_STATUS 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_MODE 15:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_MODE_ALPHA 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_MODE_BETA 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_VAFA_OUTSTANDING 16:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_VAFB_OUTSTANDING 17:17 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_VSC_ALPHA_OUTSTANDING 20:20 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_VAF_BETA_OUTSTANDING 21:21 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_TGBFILL_OUTSTANDING 22:22 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_GSPILL_OUTSTANDING 23:23 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_VSC_BETA_OUTSTANDING 24:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_VSA_WARP_OUTSTANDING 25:25 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_VSB_WARP_OUTSTANDING 26:26 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_TI_WARP_OUTSTANDING 27:27 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_TS_WARP_OUTSTANDING 28:28 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_GS_WARP_OUTSTANDING 29:29 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_CBMGR_OUTSTANDING 30:30 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS 0x00504418 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_TRAM_STATUS 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_INPUT_STATUS 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_LAUNCH_STATUS 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_OUTPUT_STATUS 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_UNEXPECTED_TRAM_DEALLOC 14:14 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_TRAMFILL_OUTSTANDING 15:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_START_XY_OUTSTANDING 16:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_PS_WARP_OUTSTANDING 17:17 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_DQUAD_UNLOAD_OUTSTANDING 18:18 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_TRAM_STATE 23:19 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_INPUT_STATE 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_2D_PIXOUT_CMD_DONE_OUTSTANDING 27:27 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_STATUS_RCVD_3D_AFTER_CONTEXT_SWITCH 29:28 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_STATUS 0x0050441c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_STATUS_VTG_STATUS 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_STATUS_PIX_STATUS 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_WLU_STATUS_COMP_STATUS 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CYA_BUNDLE_FILTER 0x00504420 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CYA_BUNDLE_FILTER_START_ADDR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CYA_BUNDLE_FILTER_START_ADDR_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CYA_BUNDLE_FILTER_END_ADDR 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CYA_BUNDLE_FILTER_END_ADDR_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_PREFUNC_WATERMARK 0x00504424 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_PREFUNC_WATERMARK_ALPHA_VSA 4:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_PREFUNC_WATERMARK_ALPHA_VSA_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_PREFUNC_WATERMARK_ALPHA_VSB 9:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_PREFUNC_WATERMARK_ALPHA_VSB_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_PREFUNC_WATERMARK_BETA_VAF 14:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_PREFUNC_WATERMARK_BETA_VAF_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_PREFUNC_WATERMARK_BETA_TS 19:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_PREFUNC_WATERMARK_BETA_TS_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_MAINFUNC_WATERMARK 0x00504428 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_MAINFUNC_WATERMARK_VSA 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_MAINFUNC_WATERMARK_VSA_INIT 0x3e /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_MAINFUNC_WATERMARK_VSB 11:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_MAINFUNC_WATERMARK_VSB_INIT 0x3e /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_MAINFUNC_WATERMARK_TI 17:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_MAINFUNC_WATERMARK_TI_INIT 0x3e /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_MAINFUNC_WATERMARK_TS 23:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_MAINFUNC_WATERMARK_TS_INIT 0x3e /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_MAINFUNC_WATERMARK_GS 29:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_MAINFUNC_WATERMARK_GS_INIT 0x3e /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_CB_GLOBAL_BASE_ADDR 0x0050442c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_CB_GLOBAL_BASE_ADDR_V 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_CB_GLOBAL_BASE_ADDR_V_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR 0x00504430 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_VTG_ERR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_VTG_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_VTG_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_SKEDCHECK34_OOB_SHARED_MEM_CONFIG 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_SKEDCHECK34_OOB_SHARED_MEM_CONFIG_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_SKEDCHECK34_OOB_SHARED_MEM_CONFIG_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_VTG_ERR_EN 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_VTG_ERR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_VTG_ERR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_EN 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_EN 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_EN 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_SKEDCHECK19_EN 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_SKEDCHECK19_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_SKEDCHECK19_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_SKEDCHECK34_EN 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_SKEDCHECK34_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_SKEDCHECK34_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_RESET_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_RESET_TRIGGER 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_INFO 0x00504434 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_INFO_VEID 5:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_HWW_ESR_INFO_VEID_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_WTC 0x00504438 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_WTC_ALPHA 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_WTC_ALPHA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_WTC_ALPHA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_WTC_BETA 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_WTC_BETA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_WTC_BETA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_WTC_WATERMARK_ALPHA 12:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_WTC_WATERMARK_ALPHA_INIT 0x1ff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_WTC_WATERMARK_BETA 24:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_WTC_WATERMARK_BETA_INIT 0x1ff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_HOLD_CNT 0x0050443c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_HOLD_CNT_3D_WARPS 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_HOLD_CNT_3D_WARPS_INIT 0x19 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_HOLD_CNT_3DPFM_SUBTILES 13:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_PIX_HOLD_CNT_3DPFM_SUBTILES_INIT 0x19 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS 0x0050444c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_INPUT_STATUS 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_LAUNCH_STATUS 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_OUTPUT_STATUS 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_INPUT_STATE 12:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_CTA_IN_PROG 13:13 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_GOT_ALPHA_DRAIN 14:14 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_GOT_BETA_DRAIN 15:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_GOT_PIX_DRAIN 16:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_SHM_CONFIG 20:17 /* R-IVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_SHM_CONFIG_0KB 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_SHM_CONFIG_8KB 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_SHM_CONFIG_16KB 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_SHM_CONFIG_32KB 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_SHM_CONFIG_64KB 0x4 /* R-I-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_SHM_CONFIG_96KB 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_SHM_CONFIG_100KB 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_SHM_CONFIG_132KB 0x8 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_STATUS_SHM_CONFIG_164KB 0x9 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG 0x00504450 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SCG_ISC_INSTRUCTION 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SCG_ISC_INSTRUCTION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SCG_ISC_INSTRUCTION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SCG_ISC_DATA 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SCG_ISC_DATA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SCG_ISC_DATA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SCG_ISC_CONSTANT 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SCG_ISC_CONSTANT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SCG_ISC_CONSTANT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SMSCG_RR_ARB 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SMSCG_RR_ARB_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SMSCG_RR_ARB_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_CTA_REQ_WARP_DONE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_CTA_REQ_WARP_DONE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_CTA_REQ_WARP_DONE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_16 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_32 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_64 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_128 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_256 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_512 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_1K 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_DIS 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SPARE 31:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_COMP_DEBUG_SPARE_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM 0x00504454 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_ALPHA_MPIPEFE 3:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_STAGE0_PREFUNC 4:4 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_STAGE0_MAINFUNC 5:5 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_STAGE1_PREFUNC 6:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_STAGE1_MAINFUNC 7:7 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_STAGE2_PREFUNC 8:8 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_STAGE2_MAINFUNC 9:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_BETA_MPIPEFE 13:10 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_STAGE3_TGB 14:14 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_STAGE3_PREFUNC 16:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_STAGE3_MAINFUNC 17:17 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_STAGE4_TGB 18:18 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_STAGE4_PREFUNC 20:19 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_STAGE4_MAINFUNC 21:21 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_ISBMGR0 24:22 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_ISBMGR1 27:25 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_SMIO 30:28 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_VTG_STATUS_FSM_SMIO_FGS_ILOCK 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_OCCUPANCY 0x00504440 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_OCCUPANCY_GFX_DENOMINATOR 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_OCCUPANCY_COMPUTE_DENOMINATOR 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL 0x00504444 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_AVG_WINDOW 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_AVG_WINDOW_MIN 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_AVG_WINDOW_MAX 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_AVG_WINDOW_INIT 0x06 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_SAMPLE_DURATION 11:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_SAMPLE_DURATION_MIN 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_SAMPLE_DURATION_MAX 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_SAMPLE_DURATION_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_IDLE_DETECT_HYS 17:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_IDLE_DETECT_HYS_MAX 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_IDLE_DETECT_HYS_MIN 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_IDLE_DETECT_HYS_INIT 0x08 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_VTG_WARP_PRIORITY_CYA 19:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_VTG_WARP_PRIORITY_CYA_DIS 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_PIX_WARP_PRIORITY_CYA 21:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_PIX_WARP_PRIORITY_CYA_DIS 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_COMP_WARP_PRIORITY_CYA 23:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_COMP_WARP_PRIORITY_CYA_DIS 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_CTA_BYPASS_SUBTILE 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_CTA_BYPASS_SUBTILE_EN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_CTA_BYPASS_SUBTILE_DIS 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_STATS_MODE 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_STATS_MODE_AVG 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_STATS_MODE_INST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_IGNORE_SMSCC_QMD_FIELDS 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_IGNORE_SMSCC_QMD_FIELDS_DIS 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_IGNORE_SMSCC_QMD_FIELDS_EN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_STALL_FOR_LAUNCH_INPROG_CYA 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_STALL_FOR_LAUNCH_INPROG_CYA_DIS 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_STALL_FOR_LAUNCH_INPROG_CYA_EN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_SPARE 31:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SMSCG_CNTRL_SPARE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_PARAM 0x00504448 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_PARAM_DATA 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_PARAM_DATA_INIT 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_PARAM_INDEX 29:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_PARAM_INDEX_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_PARAM_READ 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_PARAM_READ_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_PARAM_READ_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_PARAM_WRITE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_PARAM_WRITE_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_PARAM_WRITE_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_CLOCK_SEL 0x00504458 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_CLOCK_SEL_V 2:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_CLOCK_SEL_V_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_CLOCK_DATA_HI 0x0050445c /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_CLOCK_DATA_HI_V 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_CLOCK_DATA_HI_V_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_CLOCK_DATA_LO 0x00504460 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_CLOCK_DATA_LO_V 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_SCG_CLOCK_DATA_LO_V_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG 0x00504470 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG1 0x00504474 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG1_SLCG 4:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG1_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG1_SLCG_DISABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_MPC_CG1_SLCG__PROD 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU 0x005041ff:0x00504180 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL(i) (0x00504180+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_MODE 0:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_MODE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_MODE_STREAMING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_AGGREGATE_SCTL 2:2 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_AGGREGATE_SCTL_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_AGGREGATE_SCTL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TRIGGER_ENABLE_T_PULSE 4:4 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TRIGGER_ENABLE_T_PULSE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TRIGGER_ENABLE_T_PULSE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES 8:5 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_1K 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_2K 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_4K 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_8K 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_16K 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_32K 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_64K 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_128K 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_256K 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_512K 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_1024K 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_2048K 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_4096K 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_8192K 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TIMEBASE_CYCLES_16384K 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TRIGGER_ENABLE_PMA_TRIGGER 9:9 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TRIGGER_ENABLE_PMA_TRIGGER_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TRIGGER_ENABLE_PMA_TRIGGER_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES 14:12 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_1K 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_4K 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_16K 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_64K 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_256K 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_1024K 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_4096K 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_QUIESCENT_KEEP_RECORD 15:15 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_QUIESCENT_KEEP_RECORD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_QUIESCENT_KEEP_RECORD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_COREMIO 16:16 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_COREMIO_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_COREMIO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_SCTL0 17:17 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_SCTL0_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_SCTL0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_SCTL1 18:18 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_SCTL1_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_SCTL1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_SCTL2 19:19 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_SCTL2_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_SCTL2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_SCTL3 20:20 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_SCTL3_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_INPUT_SCTL3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TRIG_SKIP_COUNT 31:22 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROL_TRIG_SKIP_COUNT_ZERO 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CTXSW(i) (0x00504184+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CTXSW__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CTXSW_MODE 0:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CTXSW_MODE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CTXSW_MODE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CTXSW_TIMER 1:1 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CTXSW_TIMER_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CTXSW_TIMER_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PERFMONID(i) (0x00504188+(i)*64) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PERFMONID__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PERFMONID_PERFMONID 10:0 /* RWXUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PERFMONID_PERFMONID_INIT 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CYCLECNT_LSB(i) (0x0050418c+(i)*64) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CYCLECNT_LSB__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CYCLECNT_LSB_COUNT 31:0 /* RWXUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CYCLECNT_MSB(i) (0x00504190+(i)*64) /* RW-4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CYCLECNT_MSB__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CYCLECNT_MSB_COUNT 7:0 /* RWXUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_TOTAL_TRIG_RCV(i) (0x00504194+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_TOTAL_TRIG_RCV__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_TRIG_STATE(i) (0x005041b8+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_TRIG_STATE__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_TRIG_STATE_INCR_COUNT 9:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_TRIG_STATE_INCR_COUNT_ZERO 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_STATE(i) (0x00504198+(i)*64) /* R--4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_STATE__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_STATE_SAMPLECNT 8:0 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_STATE_DELAY 9:9 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_STATE_PER_SMPC_OVERFLOW 14:10 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_STATE_PER_SMPC_QUIESCENT_TIMEOUT 19:15 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_STATE_PER_SMPC_SPURIOUS_SM_DATA 24:20 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_ENGINESTATUS(i) (0x0050419c+(i)*64) /* R--4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_ENGINESTATUS__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_ENGINESTATUS_STATUS_EMPTY 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_ENGINESTATUS_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_ENGINESTATUS_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_ENGINESTATUS_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_ENGINESTATUS_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_ENGINESTATUS_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_ENGINESTATUS_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CG2_SLCG(i) (0x005041a0+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CG2_SLCG__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CG2_SLCG_ENABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CG2_SLCG_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CG2_SLCG_ENABLE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CG2_SLCG_ENABLE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROLB(i) (0x005041a4+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROLB__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROLB_FLUSH_RECORD 0:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROLB_FLUSH_RECORD_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROLB_FLUSH_RECORD_DOIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROLB_SOFT_RESET 1:1 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROLB_SOFT_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_CONTROLB_SOFT_RESET_DOIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN(i) (0x005041a8+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_ENABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_SINGLE_DP 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_SINGLE_DP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_TRIGGER_MODE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_TRIGGER_MODE_IGNORE_PMA_TRIGGER 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_TRIGGER_MODE_ONLY_PMA_TRIGGER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_TRIGGER_MODE_ONLY_TPULSE_TRIGGER 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_TRIGGER_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_MODE 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_MODE_ZEROS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_MODE_COUNT_UP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_MODE_COUNT_DOWN 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_MODE_RANDOM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_OVERFLOW_ENABLE 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_OVERFLOW_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_MODE_SEED 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_MODE_SEED_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_NUM_TRIGGERS 22:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_NUM_TRIGGERS_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_DWORDS 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_DWORDS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_TRIGGER_DELAY 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DATA_GEN_TRIGGER_DELAY_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM(i) (0x005041ac+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE0_STATUS 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE0_SM_GRP0 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE0_SM_GRP1 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE0_SM_GRP2 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE0_SM_GRP3 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE0_SM_GRP4 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE0_SM_GRP5 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE0_SM_GRP6 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE0_SM_GRP7 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE0_SM_GRP8 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE0_SM_GRP9 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE0_PMM_GRP0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE1_STATUS 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE1_SM_GRP0 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE1_SM_GRP1 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE1_SM_GRP2 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE1_SM_GRP3 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE1_SM_GRP4 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE1_SM_GRP5 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE1_SM_GRP6 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE1_SM_GRP7 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE1_SM_GRP8 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE1_SM_GRP9 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_SLICE1_PMM_GRP0 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_CTL_EN 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_CTL_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_CTL_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_PM_SELECT_CTL_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG(i) (0x005041b0+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG_TOTAL_RECORDS_SENT 31:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG_TOTAL_RECORDS_SENT_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG2(i) (0x005041b4+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG2__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG2_TOTAL_DROPPED_TRIGGERS 3:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG2_TOTAL_DROPPED_TRIGGERS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG2_TOTAL_T_PULSE_TRIGGERS 7:4 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG2_TOTAL_T_PULSE_TRIGGERS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG2_TOTAL_OVERFLOW 11:8 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG2_TOTAL_OVERFLOW_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG2_TOTAL_CTXSW_FREEZE 15:12 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG2_TOTAL_CTXSW_FREEZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG2_CYA_REGS 31:16 /* RWEUF */ #define NV_PGRAPH_PRI_GPC0_TPC0_CAU_DEBUG2_CYA_REGS_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_TPC1 0x00504800 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_TPC1_SM_CONFIG 0x00504e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC2 0x00505000 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_TPC2_SM_CONFIG 0x00505608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC3 0x00505800 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_TPC3_SM_CONFIG 0x00505e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC4 0x00506000 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_TPC4_SM_CONFIG 0x00506608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPC5 0x00506800 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_TPC5_SM_CONFIG 0x00506e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_TPCS 0x00501800 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_TPCS_SM_CONFIG 0x00501e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0 0x00503000 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES 0x0050307f:0x00503000 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00503050 /* RWB4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLKCG_CG 0x00503000 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLKCG_CG__PRIV_LEVEL_MASK 0x00503050 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLKCG_CG_BLKACTIVITY_ENABLE 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLKCG_CG_BLKACTIVITY_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLKCG_CG_BLKACTIVITY_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLKCG_CG_BLKACTIVITY_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLKCG_CG_BLKACTIVITY_ERR 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLKCG_CG_BLKACTIVITY_ERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLKCG_CG_BLKACTIVITY_ERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLKCG_CG_BLKACTIVITY_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP 0x00503004 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_STIPPLE_DISABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_STIPPLE_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_STIPPLE_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_STIPPLE_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_FETCH_REPACK 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_FETCH_REPACK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_FETCH_REPACK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_FETCH_REPACK_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_DISABLE_LFO 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_DISABLE_LFO_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_DISABLE_LFO_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_DISABLE_LFO_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_DISABLE_NODEN 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_DISABLE_NODEN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_DISABLE_NODEN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_DISABLE_NODEN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_DISABLE_NAN_DEL 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_DISABLE_NAN_DEL_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_DISABLE_NAN_DEL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_DISABLE_NAN_DEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_SPARE5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_SPARE5_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_SPARE5_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_SPARE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_SPARE6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_SPARE6_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_SPARE6_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_SPARE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_SPARE7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_SPARE7_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_SPARE7_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CLIP_SPARE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC 0x00503008 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CULL_DISABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CULL_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CULL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_CULL_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_MPC_CULL_DISABLE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_MPC_CULL_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_MPC_CULL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_MPC_CULL_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_FAST_MODE_SWITCH_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_FAST_MODE_SWITCH_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_FAST_MODE_SWITCH_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_TIER_1_STYLE_LINES_AND_POINTS 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_TIER_1_STYLE_LINES_AND_POINTS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_TIER_1_STYLE_LINES_AND_POINTS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_TIER_1_STYLE_LINES_AND_POINTS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_MAX_VIEWPORT_BBOX_FOR_CLAMPED_PRIMS 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_MAX_VIEWPORT_BBOX_FOR_CLAMPED_PRIMS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_MAX_VIEWPORT_BBOX_FOR_CLAMPED_PRIMS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_MAX_VIEWPORT_BBOX_FOR_CLAMPED_PRIMS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_WID_RECTS_CULL 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_WID_RECTS_CULL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_WID_RECTS_CULL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_WID_RECTS_CULL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_L1 0x0050300c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_L1_DM_CACHE_DISABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_L1_DM_CACHE_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_L1_DM_CACHE_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_L1_DM_CACHE_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_L1_SWITCH_SM_LIMIT 4:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_L1_SWITCH_SM_LIMIT_INIT 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG 0x00503010 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_CULL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_CULL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_CULL_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_CULL_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_DIAMOND_CULL_EN 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_DIAMOND_CULL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_DIAMOND_CULL_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_DIAMOND_CULL_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SMALL_LINE_CULL_EN 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SMALL_LINE_CULL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SMALL_LINE_CULL_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SMALL_LINE_CULL_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FLIP_BBOX_CULL 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FLIP_BBOX_CULL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FLIP_BBOX_CULL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FLIP_BBOX_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FLIP_DIAMOND_CULL 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FLIP_DIAMOND_CULL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FLIP_DIAMOND_CULL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FLIP_DIAMOND_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FLIP_SMALL_LINE_CULL 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FLIP_SMALL_LINE_CULL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FLIP_SMALL_LINE_CULL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FLIP_SMALL_LINE_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_CULL_VC_MODES 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_CULL_VC_MODES_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_CULL_VC_MODES_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_CULL_VC_MODES_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_CLIP_SINGLE_TRI 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_CLIP_SINGLE_TRI_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_CLIP_SINGLE_TRI_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_CLIP_SINGLE_TRI_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SURFACE_CULL_EN 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SURFACE_CULL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SURFACE_CULL_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SURFACE_CULL_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SCISSOR_CULL_EN 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SCISSOR_CULL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SCISSOR_CULL_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SCISSOR_CULL_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_SHRINK_DISABLE 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_SHRINK_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_SHRINK_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_SHRINK_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BACKFACE_CULL_EN 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BACKFACE_CULL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BACKFACE_CULL_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BACKFACE_CULL_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BROADCAST_STIPPLE_EN 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BROADCAST_STIPPLE_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BROADCAST_STIPPLE_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BROADCAST_STIPPLE_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SET_COUNTERS 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SET_COUNTERS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SET_COUNTERS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SET_COUNTERS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SEND_CULLED_POLYGONS 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SEND_CULLED_POLYGONS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SEND_CULLED_POLYGONS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SEND_CULLED_POLYGONS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_BLOAT_AA_POINT 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_BLOAT_AA_POINT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_BLOAT_AA_POINT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_BLOAT_AA_POINT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SCOUNT_EMAX_EN 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SCOUNT_EMAX_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SCOUNT_EMAX_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SCOUNT_EMAX_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SCISSOR_CULL_BLOAT 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SCISSOR_CULL_BLOAT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SCISSOR_CULL_BLOAT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_SCISSOR_CULL_BLOAT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_24_BIT_STIPPLE_PHASE 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_24_BIT_STIPPLE_PHASE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_24_BIT_STIPPLE_PHASE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_24_BIT_STIPPLE_PHASE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_DIAMOND_EXIT 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_DIAMOND_EXIT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_DIAMOND_EXIT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_DIAMOND_EXIT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_SMOOTH_LINES 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_SMOOTH_LINES_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_SMOOTH_LINES_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_SMOOTH_LINES_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_ROTATED_GRID 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_ROTATED_GRID_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_ROTATED_GRID_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_ROTATED_GRID_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_SM_LINE_DIAMOND 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_SM_LINE_DIAMOND_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_SM_LINE_DIAMOND_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_BBOX_SM_LINE_DIAMOND_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_CBE_WRITE_SLOWDOWN 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_CBE_WRITE_SLOWDOWN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_CBE_WRITE_SLOWDOWN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_CBE_WRITE_SLOWDOWN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_DISABLE_NIC_CG_FIX 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_DISABLE_NIC_CG_FIX_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_DISABLE_NIC_CG_FIX_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_DISABLE_NIC_CG_FIX_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_CLIP_BBOX_TO_SCISSOR 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_CLIP_BBOX_TO_SCISSOR_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_CLIP_BBOX_TO_SCISSOR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_CLIP_BBOX_TO_SCISSOR_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_TIGHTEN_SCISSOR_BBOX 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_TIGHTEN_SCISSOR_BBOX_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_TIGHTEN_SCISSOR_BBOX_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_TIGHTEN_SCISSOR_BBOX_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FIX_BMAP_COUNTER 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FIX_BMAP_COUNTER_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FIX_BMAP_COUNTER_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FIX_BMAP_COUNTER_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_PE2MPCDONE_ORDER_DISABLE 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_PE2MPCDONE_ORDER_DISABLE_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_PE2MPCDONE_ORDER_DISABLE_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_PE2MPCDONE_ORDER_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FGS_PROV_LOOKAHEAD 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FGS_PROV_LOOKAHEAD_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FGS_PROV_LOOKAHEAD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FGS_PROV_LOOKAHEAD_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FGS_2BATCH_CBE_OPT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FGS_2BATCH_CBE_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FGS_2BATCH_CBE_OPT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FGS_2BATCH_CBE_OPT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FGS_2BATCH_VCACHE_OPT 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FGS_2BATCH_VCACHE_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FGS_2BATCH_VCACHE_OPT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_VPC_DEBUG_FGS_2BATCH_VCACHE_OPT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM 0x00503014 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_TG 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_VSC 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_PEM 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_CG_STATUS_TG 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_CG_STATUS_VSC 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_CG_STATUS 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_BLK_ACTIVITY 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_WAKEUP 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_CPO_GRP_0 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_CPO_GRP_1 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_SSYNC_GRP_0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STREAM_GRP_0 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STREAM_GRP_1 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STREAM_GRP_2 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STREAM_GRP_3 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_3 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_4 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_5 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_6 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_7 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_9 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_10 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_11 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_12 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_13 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_14 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_15 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_16 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_17 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_TG_GRP_18 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_0 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_1 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_2 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_3 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_4 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_5 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_6 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_7 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_8 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PVLDRDY1 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PVLDRDY2 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PVLDRDY3 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PVLDRDY4 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VALID1 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VALID2 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VALID3 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PVLDRDY5 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PVLDRDY6 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_9 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_10 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_11 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PG_STATUS 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_1 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_2 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_3 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_4 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_5 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_6 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_7 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_8 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_9 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_10 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_11 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_12 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_13 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_14 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_15 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_16 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_17 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_18 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_19 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_20 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_21 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_22 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_23 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_24 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_25 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_26 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_27 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_28 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_29 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_30 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_31 0x5e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_32 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_33 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_34 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_35 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_36 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_37 0x64 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_38 0x65 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_39 0x66 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_40 0x67 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_41 0x68 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_42 0x69 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_43 0x6a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_44 0x6b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_45 0x6c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_46 0x6d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_PEM_GRP_47 0x6e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_12 0x70 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_13 0x71 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_14 0x72 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_15 0x73 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_16 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_17 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_18 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_19 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_20 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_VPC_GRP_21 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_GRP_19 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_GRP_20 0x81 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_GRP_21 0x82 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_GRP_22 0x83 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_GRP_23 0x84 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_GRP_24 0x85 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_GRP_25 0x86 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_GRP_26 0x87 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_GRP_27 0x88 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATUS_GRP_28 0x89 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_BA_GRP_1 0x90 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_BA_GRP_2 0x91 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_BA_GRP_3 0x92 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_SINGLE_PASS_GRP1 0x93 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATIC_PATTERN_2A_6_GROUP 0xa0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_STATIC_PATTERN_15_6_GROUP 0xa1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_CTL_EN 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_CTL_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_CTL_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_PM_SELECT_CTL_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x00503018 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS 0x0050301c /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS_PES 2:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS_PES_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS_TGA 5:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS_TGA_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS_VSC 8:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS_VSC_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS_TGB 11:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS_TGB_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS_PEM 14:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS_PEM_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS_CACHE 17:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_STATUS_CACHE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS 0x00503020 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_IFACE 2:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_IFACE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_SYNC 5:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_SYNC_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_SCOUNT 8:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_SCOUNT_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_PFETCH 11:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_PFETCH_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_CLIP 14:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_CLIP_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_CULL 17:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_CULL_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_CBMGR 20:18 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_CBMGR_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_WWDX 23:21 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_WWDX_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_DOUT 26:24 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_DOUT_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_NIC 29:27 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STATUS_NIC_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG 0x00503024 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_USE_SW_COMPUTED_GS_CONSTRAINT_V 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_USE_SW_COMPUTED_GS_CONSTRAINT_V_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_CONSTRAINT_BALANCE_LOAD 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_CONSTRAINT_BALANCE_LOAD_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_CONSTRAINT_BALANCE_LOAD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_CONSTRAINT_BALANCE_LOAD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_SCAN_INTERIOR_HORIZONTALLY 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_SCAN_INTERIOR_HORIZONTALLY_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_VERTEX_REORDERING 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_VERTEX_REORDERING_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_VERTEX_REORDERING_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_VERTEX_REORDERING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_WINDING_SWAP 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_WINDING_SWAP_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_WINDING_SWAP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_TG_WINDING_SWAP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_MODES 0x00503054 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_MODES_FORCE_SWIZZLE_NEG_W_TO_ONE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_MODES_FORCE_SWIZZLE_NEG_W_TO_ONE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_MODES_FORCE_SWIZZLE_NEG_W_TO_ONE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_MODES_FORCE_SWIZZLE_NEG_W_TO_ONE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_MODES_PROVOKING_FIRST_DX_MODE 2:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_MODES_PROVOKING_FIRST_DX_MODE_NO_ROTATE_DEFAULT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_MODES_PROVOKING_FIRST_DX_MODE_ROTATE_DEPENDS_ON_BARYCENTRICS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_MODES_PROVOKING_FIRST_DX_MODE_ROTATE_LEGACY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_MODES_PROVOKING_FIRST_DX_MODE_ROTATE_RESERVED 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_MODES_PROVOKING_FIRST_DX_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG 0x00503028 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG1 0x0050302c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_CG1_SLCG__PROD 0x0208afe0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR 0x00503038 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P01_ERR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P02_ERR 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P12_ERR 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P01_ERR 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P02_ERR 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P12_ERR 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P01_ERR 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P02_ERR 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P12_ERR 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_BD_P01_ERR 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_BD_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_BD_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_BD_P02_ERR 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_BD_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_BD_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_BD_P12_ERR 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_BD_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_BD_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_TK_P01_ERR 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_TK_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_TK_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_TK_P02_ERR 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_TK_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_TK_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_TK_P12_ERR 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_TK_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_TK_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_WK_P01_ERR 15:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_WK_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_WK_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_WK_P02_ERR 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_WK_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_WK_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_WK_P12_ERR 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_WK_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_VSC_BETA_WK_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_BD_P01_ERR 18:18 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_BD_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_BD_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_BD_P02_ERR 19:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_BD_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_BD_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_BD_P12_ERR 20:20 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_BD_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_BD_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_TK_P01_ERR 21:21 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_TK_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_TK_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_TK_P02_ERR 22:22 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_TK_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_TK_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_TK_P12_ERR 23:23 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_TK_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_TK_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_WK_P01_ERR 24:24 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_WK_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_WK_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_WK_P02_ERR 25:25 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_WK_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_WK_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_WK_P12_ERR 26:26 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_WK_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_PEM_TGB_FILL_WK_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_RESET_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_RESET_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_HWW_ESR_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_A 0x0050303c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_A__PRIV_LEVEL_MASK 0x00503050 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_A_1 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_A_1_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_A_2 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_A_2_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_A_3 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_A_3_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_B 0x00503040 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_B__PRIV_LEVEL_MASK 0x00503050 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_B_4 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_B_4_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_B_5 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_B_5_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_B_6 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_B_6_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_C 0x00503044 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_C__PRIV_LEVEL_MASK 0x00503050 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_C_7 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_C_7_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_C_8 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_C_8_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_C_9 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_C_9_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_D 0x00503048 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_D__PRIV_LEVEL_MASK 0x00503050 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_D_10 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_D_10_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_D_11 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_D_11_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_D_12 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_D_12_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_E 0x0050304c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_E__PRIV_LEVEL_MASK 0x00503050 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_E_13 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_E_13_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_E_14 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_E_14_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_E_15 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_PES_BLK_ACTIVITY_WEIGHTS_E_15_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX 0x005031ff:0x00503100 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP(i) (0x00503100+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP__SIZE_1 43 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP_TILE0 4:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP_TILE0_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP_TILE1 9:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP_TILE1_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP_TILE2 14:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP_TILE2_INIT 0x02 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP_TILE3 19:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP_TILE3_INIT 0x03 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP_TILE4 24:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP_TILE4_INIT 0x04 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP_TILE5 29:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_GPC_MAP_TILE5_INIT 0x05 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG 0x005031d0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET_INIT 0x03 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE_INIT 0x4 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_SM_NUM_RCP 0x005031d4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_SM_NUM_RCP_CONSERVATIVE_MAX 0x800000 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_SM_NUM_RCP_CONSERVATIVE_INIT 0x800000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM 0x005031dc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_DEBUG_SIGNAL_GPC_INSTANCE_ID_GROUP 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_DEBUG_SIGNAL_TPC_INSTANCE_ID_GROUP 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_STATIC_PATTERN_2AAA_15_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_STATIC_PATTERN_5555_15_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_SELECT_MAX 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG 0x005031e0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_CACHETILE_COVERAGE_BBOX 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_CACHETILE_COVERAGE_BBOX_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_CACHETILE_COVERAGE_BBOX_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_RESERVED 21:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_RESERVED_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_FORCE_CBE_ADDR_TO_ALL_GPCS 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_FORCE_CBE_ADDR_TO_ALL_GPCS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_FORCE_CBE_ADDR_TO_ALL_GPCS_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_FORCE_CBE_ADDR_TO_ALL_GPCS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_FORCE_PRIMS_TO_ALL_GPCS 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_FORCE_PRIMS_TO_ALL_GPCS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_FORCE_PRIMS_TO_ALL_GPCS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_PRIORITIZE_ALPHA_CBES 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_PRIORITIZE_ALPHA_CBES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_PRIORITIZE_ALPHA_CBES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_TASK_FIFO_REDUCE_DIV32 28:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_TASK_FIFO_REDUCE_DIV32_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_TASK_FIFO_REDUCE_DIV32_FULLSIZE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_PRIM_FIFO_REDUCE_DIV32 30:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_PRIM_FIFO_REDUCE_DIV32_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_PRIM_FIFO_REDUCE_DIV32_FULLSIZE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_TILED_CACHING 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_TILED_CACHING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_TILED_CACHING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CONFIG_TILED_CACHING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_COEFF(i) (0x005031b0+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_COEFF__SIZE_1 5 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_COEFF_0_MOD_VALUE 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_COEFF_0_MOD_VALUE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_COEFF_1_MOD_VALUE 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_COEFF_1_MOD_VALUE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_COEFF_2_MOD_VALUE 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_COEFF_2_MOD_VALUE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_COEFF_3_MOD_VALUE 31:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_MAP_TABLE_CONFIG_COEFF_3_MOD_VALUE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG 0x005031e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG1 0x005031ec /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_WWDX_CG1_SLCG__PROD 0x7ffffff8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM 0x005030ff:0x005030c0 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE 0x005030c0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V 21:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_DEFAULT 0x000480 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_GFXP 0x000d28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_GRANULARITY 0x000020 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE 0x005030e4 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_DEFAULT 0x0800 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_GRANULARITY 0x0020 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_OFFSET 0x005030f4 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_OFFSET_V 21:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_OFFSET_V_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_OFFSET 0x005030f8 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_OFFSET_V 21:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_OFFSET_V_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_STEADY_STATE_CB_SIZE 0x005030f0 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_STEADY_STATE_CB_SIZE_V 21:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_STEADY_STATE_CB_SIZE_V_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_STEADY_STATE_CB_SIZE_V_DEFAULT 0x000480 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_STEADY_STATE_CB_SIZE_V_GRANULARITY 0x000020 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_CTRL 0x005030fc /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_CTRL_CBES_RESERVE 11:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_CTRL_CBES_RESERVE_NON_GFXP 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_CTRL_CBES_RESERVE_GFXP 0x100 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG 0x005030c4 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_INVALIDATE_ALPHA 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_INVALIDATE_ALPHA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_INVALIDATE_ALPHA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_INVALIDATE_BETA 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_INVALIDATE_BETA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_INVALIDATE_BETA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_DELETE_ARB 26:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_DELETE_ARB_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_DELETE_ARB_ROUND_ROBIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_DELETE_ARB_PRIM_PRIORITY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_DELETE_ARB_TASK_PRIORITY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_RESERVED 31:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_DEBUG_RESERVED_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_INDEX 0x005030c8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_INDEX_INDEX 2:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_INDEX_INDEX_MIN 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_INDEX_INDEX_MAX 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_INDEX_READINCR 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_INDEX_READINCR_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_INDEX_READINCR_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE 0x005030dc /* R--4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE__APERTURE_INDEX 0x005030c8 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_0_ALPHA_FSM 21:18 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_0_BETA_FSM 25:22 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_0_WWDX2CBMGR 28:26 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_0_AB_MERGE 31:29 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_1_ALPHA_COUNT 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_1_BETA_COUNT 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_ALPHA_ALLOC 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_ALPHA_ALLOC_ALLOC 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_ALPHA_ALLOC_INVFIFO 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_BETA_ALLOC 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_BETA_ALLOC_ALLOC 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_BETA_ALLOC_INVFIFO 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_PE2CBMGR_VSC 20:18 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_CBMGR2PE_VSC 23:21 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_CBMGR2PE_PIN 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_PE2CBMGR_INVACK 29:27 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_ALPHA_SIZE_GT_MAX_HANG 30:30 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_ALPHA_SIZE_GT_MAX_HANG_NOT_HUNG 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_ALPHA_SIZE_GT_MAX_HANG_HUNG 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_BETA_SIZE_GT_MAX_HANG 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_BETA_SIZE_GT_MAX_HANG_NOT_HUNG 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_2_BETA_SIZE_GT_MAX_HANG_HUNG 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_3_MPC2CBMGR0 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_3_CBMGR2MPC0 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_3_MPC2CBMGR1 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_3_CBMGR2MPC1 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_3_MPC2CBMGR2 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_3_CBMGR2MPC2 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_3_MPC2CBMGR3 20:18 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_3_CBMGR2MPC3 23:21 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_3_MPC2CBMGR4 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_3_CBMGR2MPC4 29:27 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_4_ALPHA_ALLOC_SPACE 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_STATUS_APERTURE_4_BETA_ALLOC_SPACE 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM 0x005030cc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_DEBUG_SIGNAL_GPC_INSTANCE_ID_GROUP 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_DEBUG_SIGNAL_TPC_INSTANCE_ID_GROUP 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_STATIC_PATTERN_2AAA_14_GROUP 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_STATIC_PATTERN_1555_14_GROUP 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_SELECT_MAX 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG 0x005030d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG1 0x005030d4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CG1_SLCG__PROD 0x7ffffffc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_PPC1 0x00503200 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_PPC2 0x00503400 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_PPCS 0x00503e00 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_ROP0 0x00503800 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP 0x0050385f:0x00503800 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1 0x00503800 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZRD_NO_COND_READ 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZRD_NO_COND_READ_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZRD_NO_COND_READ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZRD_NO_COND_READ_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_CLEAR 11:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_CLEAR_ALL_BUNDLES_ALL_GLOBAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_CLEAR_FLUSHBUNDLES_ALL_GLOBAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_CLEAR_LITE_FLUSHBUNDLES_PERGPC 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_CLEAR_NO_BUNDLES 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_CLEAR_INIT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_Z 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_Z_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_Z_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_Z_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_FORCE_L2_WAKE 31:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_FORCE_L2_WAKE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_FORCE_L2_WAKE_ON_NONIDLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_FORCE_L2_WAKE_ALWAYS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG1_FORCE_L2_WAKE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2 0x00503804 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_FORCE_VISIBLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_FORCE_VISIBLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_FORCE_VISIBLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_FORCE_VISIBLE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_RTL_KNOBS 27:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_RTL_KNOBS_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_WRITE_FULL_BE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_WRITE_FULL_BE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_WRITE_FULL_BE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_WRITE_FULL_BE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_DISABLE_FULL_WE_OPT 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG2_ZWR_DISABLE_FULL_WE_OPT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3 0x00503808 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_INNER_IL_COVG_AWARE 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_INNER_IL_COVG_AWARE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_INNER_IL_COVG_AWARE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_INNER_IL_COVG_AWARE_ONLY_1_STAGE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_INNER_IL_COVG_AWARE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8 7:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8_NOREDUCE 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8_FULLSIZE 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_HASHENTRIES_REDUCE_DIV8 12:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_HASHENTRIES_REDUCE_DIV8_FULLSIZE 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_HASHENTRIES_REDUCE_DIV8_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_RTL_KNOBS 27:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_RTL_KNOBS_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_COALESCE_WRITES 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_COALESCE_WRITES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_COALESCE_WRITES_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG3_COALESCE_WRITES_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4 0x0050380c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_PM_LOCAL_TRIGGER_GPC 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_PM_LOCAL_TRIGGER_GPC_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_S8_COALESCER_LIMIT 11:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_S8_COALESCER_LIMIT_MAX 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_S8_COALESCER_LIMIT_ZERO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_S8_COALESCER_LIMIT_INIT 0x7 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_S8_COALESCER_TIMEOUT 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_S8_COALESCER_TIMEOUT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_S8_COALESCER_TIMEOUT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_BURSTY_MIN_GEAR 18:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_BURSTY_MIN_GEAR_DISABLE_BURSTING 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_BURSTY_MIN_GEAR_FULL_RANGE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_BURSTY_MIN_GEAR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_RTL_KNOBS 26:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_RTL_KNOBS_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW 28:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW_NONE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW_S8_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW_ALL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_SPARE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG4_SPARE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5 0x00503810 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5_SRCPKTFIFO_REDUCE_DIV256 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5_SRCPKTFIFO_REDUCE_DIV256_FULLSIZE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5_HASHENTRIES_REDUCE_DIV256 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5_HASHENTRIES_REDUCE_DIV256_FULLSIZE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT0 17:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT0_ORIGINAL_GALOIS 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT0_AVOID_ROPSLICE_MAP_A 0x255 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT0_AVOID_ROPSLICE_MAP_B 0x015 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT1 27:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT1_ORIGINAL_GALOIS 0x2f6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT1_AVOID_ROPSLICE_MAP_A 0x2c4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT1_AVOID_ROPSLICE_MAP_B 0x0c4 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM 0x00503814 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_STATIC_PATTERN_25_6_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_STATIC_PATTERN_1A_6_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2 13:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_STATIC_PATTERN_25_6_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_STATIC_PATTERN_1A_6_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_GROUP_SEL2_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP10 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP11 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP12 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP13 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP14 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_STATIC_PATTERN_25_6_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_GRP15 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_STATIC_PATTERN_1A_6_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2 25:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP10 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP11 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP12 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP13 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP14 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_STATIC_PATTERN_25_6_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_GRP15 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_STATIC_PATTERN_1A_6_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_COUNT_SEL2_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PPM_ENABLE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG 0x00503818 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG1 0x0050381c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS 0x00503820 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_DECODER_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_DECODER_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_DECODER_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_DECODER_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_DECODER_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_DECODER_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_DECODER_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_DECODER_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZRDPIPE_STATUS 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_LTCTRACK_STATUS 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_LTCTRACK_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_LTCTRACK_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_LTCTRACK_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_LTCTRACK_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_LTCTRACK_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_LTCTRACK_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_LTCTRACK_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZSUB_STATUS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZSUB_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZSUB_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZSUB_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZSUB_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZSUB_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZSUB_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZSUB_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_BPC_STATUS 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_BPC_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_BPC_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_BPC_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_BPC_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_BPC_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_BPC_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_BPC_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PACKETIZER_STATUS 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PACKETIZER_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PACKETIZER_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PACKETIZER_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PACKETIZER_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PACKETIZER_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PACKETIZER_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PACKETIZER_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PIPE_STATUS 20:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PIPE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PIPE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PIPE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PIPE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PIPE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PIPE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_PIPE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZWR_STATUS 23:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZWR_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZWR_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZWR_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZWR_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZWR_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZWR_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZWR_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_RETIRE_STATUS 26:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_RETIRE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_RETIRE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_RETIRE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_RETIRE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_RETIRE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_RETIRE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_RETIRE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZCULL_STATUS 29:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZCULL_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZCULL_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZCULL_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZCULL_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZCULL_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZCULL_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_ZCULL_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_WACKFIFO_STATE 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_WACKFIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS_WACKFIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2 0x00503824 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2_TOP 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2_TOP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2_TOP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2_TOP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2_TOP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2_TOP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2_TOP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2_TOP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2_TAGS_IN_USE_COUNT 11:3 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2_ILQUEUE_ENTRY_COUNT 18:12 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2_ZSUB_ENTRY_COUNT 27:19 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_STATUS2_VALID_CACHETILES_COUNT 31:28 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG_COUNT_REQUESTS 0x00503828 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG_COUNT_REQUESTS_ZRD2RRH_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG_COUNT_REQUESTS_ZRD2RRH_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG_COUNT_REQUESTS_ZWR2RRH_PACKETS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG_COUNT_REQUESTS_ZWR2RRH_PACKETS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG_COUNT_RESPONSES 0x0050382c /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZRD_RDAT_PACKETS_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZRD_RDAT_PACKETS_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZWR_ACKS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZWR_ACKS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR 0x00503838 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_DEAD_TAGS 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_DEAD_TAGS_NOT_PRESENT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_DEAD_TAGS_PRESENT 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_DEAD_TAGS_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_RDAT_ORPHANS 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_RDAT_ORPHANS_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_RDAT_ORPHANS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_RDAT_ORPHANS_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_EOZP_MISMATCH 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_EOZP_MISMATCH_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_EOZP_MISMATCH_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_EOZP_MISMATCH_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_ZWRRAM_ORPHANS 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_ZWRRAM_ORPHANS_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_ZWRRAM_ORPHANS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_ZWRRAM_ORPHANS_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_BLKACTIVITY_ERROR 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_BLKACTIVITY_ERROR_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_BLKACTIVITY_ERROR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_BLKACTIVITY_ERROR_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_HWW_ESR_EN_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF 0x00503854 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_FULLSPEED 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_03125 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_06250 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_09375 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_12500 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_15625 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_18750 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_21875 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_25000 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_28125 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_31250 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_34375 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_37500 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_40625 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_43750 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_46875 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_50000 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_53125 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_56250 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_59375 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_62500 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_65625 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_68750 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_71875 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_75000 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_78125 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_81250 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_84375 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_87500 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_90625 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_93750 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_PERF_THROTTLE_PIPE_0_96875 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00503840 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_A 0x00503844 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_A__PRIV_LEVEL_MASK 0x00503840 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_A_INTERCEPT 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_A_INTERCEPT_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_A_WEIGHT_1 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_A_WEIGHT_1_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_A_WEIGHT_2 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_A_WEIGHT_2_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_B 0x00503848 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_B__PRIV_LEVEL_MASK 0x00503840 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_B_WEIGHT_3 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_B_WEIGHT_3_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_B_WEIGHT_4 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_B_WEIGHT_4_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_B_WEIGHT_5 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_B_WEIGHT_5_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_C 0x0050384c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_C__PRIV_LEVEL_MASK 0x00503840 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_C_WEIGHT_6 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_C_WEIGHT_6_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_C_WEIGHT_7 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_C_WEIGHT_7_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_C_WEIGHT_8 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_C_WEIGHT_8_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_D 0x00503850 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_D__PRIV_LEVEL_MASK 0x00503840 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_D_WEIGHT_9 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_D_WEIGHT_9_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_D_WEIGHT_10 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_D_WEIGHT_10_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_D_WEIGHT_11 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_ZROP_BLK_ACTIVITY_D_WEIGHT_11_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH 0x0050387f:0x00503860 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0 0x00503860 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RRA_FAVOR_IL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RRA_FAVOR_IL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RRA_FAVOR_IL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RRA_FAVOR_Z 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RRA_FAVOR_Z_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RRA_FAVOR_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RRA_IL_DELAY 5:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RRA_IL_DELAY_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RC_FAVOR_IL 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RC_FAVOR_IL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RC_FAVOR_IL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RC_FAVOR_Z 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RC_FAVOR_Z_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RC_FAVOR_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_WRA_FAVOR_Z 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_WRA_FAVOR_Z_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_WRA_FAVOR_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RW_ARB_BURST_SIZE 12:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RW_ARB_BURST_SIZE_ONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_RW_ARB_BURST_SIZE_INIT 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA_4TO1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA_8TO1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_CONCAT_WRITE_COMP 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_CONCAT_WRITE_COMP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_CONCAT_WRITE_COMP_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_CONCAT_WRITE_UNCOMP 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_CONCAT_WRITE_UNCOMP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_CONCAT_WRITE_UNCOMP_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_CONCAT_WRITE_FCLR 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_CONCAT_WRITE_FCLR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_CONCAT_WRITE_FCLR_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_C 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_C_WARM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_C_NONE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_Z 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_Z_WARM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_Z_NONE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_FE_MSG_FIFO_REDUCE 25:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_FE_MSG_FIFO_REDUCE_FULLSIZE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_WRITE_REQ_SB_REDUCE_DIV8 31:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG0_WRITE_REQ_SB_REDUCE_DIV8_FULLSIZE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1 0x00503864 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_TOTAL_SLOTS_REDUCE_DIV8 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_TOTAL_SLOTS_REDUCE_DIV8_FULLSIZE 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_TOTAL_SLOTS_REDUCE_DIV8_LOW_CLAMP 0x030 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_TOTAL_SUBREQS_REDUCE_DIV8 16:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_TOTAL_SUBREQS_REDUCE_DIV8_FULLSIZE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_TOTAL_SUBREQS_REDUCE_DIV8_LOW_CLAMP 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_RESERVED_SLOTS_DIV4 22:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_RESERVED_SLOTS_DIV4_INIT 0x02 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_RESERVED_SLOTS_DIV4_LOW_CLAMP 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_RESERVED_SUBREQS_DIV4 27:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_RESERVED_SUBREQS_DIV4_INIT 0x02 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_RESERVED_SUBREQS_DIV4_LOW_CLAMP 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_SLOTMAN_ALLOCATION 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_SLOTMAN_ALLOCATION_NORMAL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_SLOTMAN_ALLOCATION_OVERRIDE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_SAFEGUARDS 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_SAFEGUARDS_ALLOW_NORMAL_OPERATION 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_SAFEGUARDS_SUPPRESS_MEMORY_ACCESS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_SAFEGUARDS_SUPPRESS_ALL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_Z_SYNC 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_Z_SYNC_COUPLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_Z_SYNC_DECOUPLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG1_Z_SYNC__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS 0x00503868 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_TOP_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_TOP_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_TOP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_TOP_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_TOP_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_TOP_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_TOP_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_TOP_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_FAULTING_OR_HALTING 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_FAULTING_OR_HALTING_NOT_IN_PROGRESS 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_FAULTING_OR_HALTING_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_SYNCHRONIZING_C_SIDE 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_SYNCHRONIZING_C_SIDE_NOT_IN_PROGRESS 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_SYNCHRONIZING_C_SIDE_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_SYNCHRONIZING_Z_SIDE 5:5 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_SYNCHRONIZING_Z_SIDE_NOT_IN_PROGRESS 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_SYNCHRONIZING_Z_SIDE_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CNIL 6:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CIL 7:7 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZNIL 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZIL 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_WRA_STATUS_SHORT 11:10 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_WRA_STATUS_SHORT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_WRA_STATUS_SHORT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_WRA_STATUS_SHORT_STALLED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_WRA_STATUS_SHORT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_WRS_STATUS_SHORT 13:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_WRS_STATUS_SHORT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_WRS_STATUS_SHORT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_WRS_STATUS_SHORT_STALLED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_WRS_STATUS_SHORT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_RWA_STATUS 16:14 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_RWA_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_RWA_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_RWA_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_RWA_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_RWA_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_RWA_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_RRH_RWA_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_ACK 17:17 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_ACK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_ACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_CREDIT 18:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_CREDIT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_CREDIT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_MSG_FIFO 19:19 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_MSG_FIFO_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_MSG_FIFO_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_MEMBAR_ACK 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_MEMBAR_ACK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_MEMBAR_ACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_SCOREBOARD_ID 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_SCOREBOARD_ID_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_SCOREBOARD_ID_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_WDAT 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_WDAT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_WAIT_FOR_WDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_SCOREBOARD_NONEMPTY 23:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_SCOREBOARD_NONEMPTY_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_WRS_SCOREBOARD_NONEMPTY_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CIL 24:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CNIL 25:25 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZIL 26:26 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZNIL 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READPIPE_STATE 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READPIPE_STATE_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READPIPE_STATE_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READPIPE_STATE_STALLED_BY_RWA 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READPIPE_STATE_AWAITING_MEMSYS_RESPONSE 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READPIPE_STATE_STALLED_RRH2CRD_CNIL 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READPIPE_STATE_STALLED_RRH2CRD_CIL 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READPIPE_STATE_STALLED_RRH2ZRD_ZNIL 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READPIPE_STATE_STALLED_RRH2ZRD_ZIL 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READPIPE_STATE_SYNC_STALL 0x8 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_STATUS_READPIPE_STATE_OTHER 0x9 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0 0x0050386c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_RD 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_WR 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_RD 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_WR 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_MEMBAR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_MEMBAR_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_RD 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_WR 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_MEMBAR 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_MEMBAR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_RD 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_WR 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_RD 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_WR 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_RD 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_WR 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD_FORCE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR_FORCE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_MEMBAR 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_MEMBAR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_MEMBAR_FORCE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_BLOCK_RD 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_MEMBAR 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_MEMBAR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_RD 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_WR 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_MEMBAR 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_MEMBAR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM 0x00503870 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL_GRP_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2 13:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_GROUP_SEL2_GRP_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_PPM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG 0x00503874 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG1 0x00503878 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG3 0x0050387c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_256 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_1024 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_4096 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_16384 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP 0x005038ff:0x00503880 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1 0x00503880 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CRD_COND_READ 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CRD_COND_READ_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CRD_COND_READ_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CRD_CREAD 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CRD_CREAD_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CRD_CREAD_FORCE_CREAD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CRD_CREAD_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_KNOBS 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_KNOBS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_RDSUPPRESS 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_RDSUPPRESS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_RDSUPPRESS_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_RDSUPPRESS_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_WRSUPPRESS 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_WRSUPPRESS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_WRSUPPRESS_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_WRSUPPRESS_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_CLEAR 16:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_CLEAR_ALL_BUNDLES_ALL_GLOBAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_CLEAR_FLUSHBUNDLES_ALL_GLOBAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_CACHE_CLEAR_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_WRITE_FULL_BE 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_WRITE_FULL_BE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_WRITE_FULL_BE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG1_WRITE_FULL_BE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2 0x00503884 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_CACHE_ENTRY_ID_LIMIT 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_CACHE_ENTRY_ID_LIMIT_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT 17:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_ONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_TWO 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_THREE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_FOUR 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_FIVE 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_SIX 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_SEVEN 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_DISABLE 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_INIT 0x7 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_WR_OPT 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_WR_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_WR_OPT_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG2_WR_OPT_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3 0x00503888 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_BLENDOPT_KILL 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_BLENDOPT_KILL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_BLENDOPT_KILL_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_BLENDOPT_FILL_OVERRIDE 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_BLENDOPT_FILL_OVERRIDE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_BLENDOPT_FILL_OVERRIDE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_C8_C16_DISABLE_COND_READ 4:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_NEVER 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_FOR_C8_1XAA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_FOR_CLEAR 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_ALWAYS 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_ARITHMETIC_SUCCESS 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_ARITHMETIC_SUCCESS_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_ARITHMETIC_SUCCESS_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_REDUCTION_SUCCESS 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_REDUCTION_SUCCESS_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_REDUCTION_SUCCESS_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_ARITHMETIC_DISABLE 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_ARITHMETIC_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_ARITHMETIC_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_REDUCTION_DISABLE 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_REDUCTION_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_REDUCTION_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_PROCESS_REDUCED_DISABLE 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_PROCESS_REDUCED_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_PROCESS_REDUCED_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_BOTH_DISABLE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_BOTH_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_BOTH_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_TIE_UP 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_TIE_UP_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_TIE_UP_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_ZBC_DISABLE 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_ZBC_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_ZBC_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_CC_DISABLE 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_CC_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_CC_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_UCOMP_MIXED_DISABLE 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_UCOMP_MIXED_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_UCOMP_MIXED_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT 23:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_128K 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_512K 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_2M 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_8M 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_32M 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_64M 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_128M 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_256M 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_512M 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_768M 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_1024M 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_1536M 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_2048M 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_NEVER 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_INIT 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA 25:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA_4TO1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA_8TO1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_TAG_FLUSH_CTL 27:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_TAG_FLUSH_CTL_ENTER_DECOMP_IN_PLACE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_TAG_FLUSH_CTL_CHANGE_DECOMP_IN_PLACE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_TAG_FLUSH_CTL_CHANGE_CLEAR_MODE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_TAG_FLUSH_CTL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4 0x0050388c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_SRCPKTFIFO_REDUCE_DIV8 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_SRCPKTFIFO_REDUCE_DIV8_FULLSIZE 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_SRCPKTFIFO_REDUCE_DIV8_INIT 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_HASHENTRIES_REDUCE_DIV8 17:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_HASHENTRIES_REDUCE_DIV8_FULLSIZE 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_HASHENTRIES_REDUCE_DIV8_INIT 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_CLAMP_FP_BLEND 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_RMW_DISABLE_FORCE_ZERO 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_RMW_DISABLE_FORCE_ZERO_NO_FORCE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_RMW_DISABLE_FORCE_ZERO_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_PITCH_FORCE_DISALLOW_PLC 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_PITCH_FORCE_DISALLOW_PLC_NO_FORCE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_PITCH_FORCE_DISALLOW_PLC_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM 0x00503894 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_STATIC_PATTERN_A55A_16_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_STATIC_PATTERN_5AA5_16_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2 13:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_STATIC_PATTERN_A55A_16_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_STATIC_PATTERN_5AA5_16_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_GROUP_SEL2_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PPM_ENABLE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG 0x00503898 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG1 0x0050389c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1 0x005038a0 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_RETIRE_STATUS 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_RETIRE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_RETIRE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_RETIRE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_RETIRE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_RETIRE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_RETIRE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_RETIRE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CSUB_STATUS 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CSUB_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CSUB_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CSUB_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CSUB_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CSUB_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CSUB_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CSUB_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_PIPE_STATUS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_PIPE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_PIPE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_PIPE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_PIPE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_PIPE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_PIPE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_PIPE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CWR_STATUS 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CWR_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CWR_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CWR_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CWR_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CWR_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CWR_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CWR_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_DECOMP_STATUS 16:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_DECOMP_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_DECOMP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_DECOMP_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_DECOMP_STATUS_STALLED 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_COMP_STATUS 18:17 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_COMP_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_COMP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_COMP_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_COMP_STATUS_STALLED 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_BLEND_STATUS 19:19 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_BLEND_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_BLEND_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_IL_NIL_FIFO_STATE 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_IL_NIL_FIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_IL_NIL_FIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_SEMAACK_FIFO_STATE 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_SEMAACK_FIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_SEMAACK_FIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_WACKFIFO_STATE 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_WACKFIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_WACKFIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_CC_STATE 26:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_CC_STATE_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_CC_STATE_GLOBAL_FLUSH_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_CC_STATE_PASS_PKTS 0xa /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_CC_STATE_PASS_BUNDLES 0xb /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_CC_STATE_PASS_EARLY_QUADS 0xc /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_TILE_IN_FLIGHT 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_TILE_IN_FLIGHT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_TILE_IN_FLIGHT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION 30:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRNL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRNL_1 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRNM 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRTM 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRNL 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRNL_1 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRNM 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRTM 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_WAITING_FOR_FLUSH 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_WAITING_FOR_FLUSH_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS1_CRD_WAITING_FOR_FLUSH_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS2 0x005038a4 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS2_TOP 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS2_TOP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS2_TOP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS2_TOP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS2_TOP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS2_TOP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS2_TOP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS2_TOP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS2_TAGS_IN_USE_COUNT 12:3 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS2_ILQUEUE_ENTRY_COUNT 22:13 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS2_CSUB_ENTRY_COUNT 31:23 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3 0x005038a8 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_RED_PREFETCH_ILOCK 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_RED_PREFETCH_ILOCK_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_RED_PREFETCH_ILOCK_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_WAIT_FOR_RDAT 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_WAIT_FOR_RDAT_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_WAIT_FOR_RDAT_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_SAMPLE_CONFLICT_ILOCK 2:2 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_SAMPLE_CONFLICT_ILOCK_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_SAMPLE_CONFLICT_ILOCK_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_SURFACE_KIND 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_SURFACE_KIND_BL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_SURFACE_KIND_PITCH 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_S0_STATE 5:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_S0_STATE_FIRST_OF_TILE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_S0_STATE_FIRST_OF_QUAD 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_S0_STATE_EXPAND_QUAD 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_S0_STATE_CUM_FILL 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CWR_RETIRE_QUEUE 7:7 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CWR_RETIRE_QUEUE_HASROOM 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CWR_RETIRE_QUEUE_FULL 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_INT_COMPUTE_ILOCK 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_INT_COMPUTE_ILOCK_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_CPROC_INT_COMPUTE_ILOCK_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_VALID_CACHETILES_COUNT 14:9 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_SPARE 31:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_STATUS3_SPARE_DEFAULT 0x00000 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG_COUNT_REQUESTS 0x005038ac /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG_COUNT_REQUESTS_CRD2RRH_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG_COUNT_REQUESTS_CRD2RRH_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG_COUNT_REQUESTS_CWR2RRH_PACKETS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG_COUNT_REQUESTS_CWR2RRH_PACKETS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG_COUNT_RESPONSES 0x005038b0 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG_COUNT_RESPONSES_RRH2CRD_RDAT_PACKETS_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG_COUNT_RESPONSES_RRH2CRD_RDAT_PACKETS_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG_COUNT_RESPONSES_RRH2CWR_ACKS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUG_COUNT_RESPONSES_RRH2CWR_ACKS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR 0x005038bc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_DEAD_TAGS 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_DEAD_TAGS_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_DEAD_TAGS_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_CACHE_HIT_FROM_OTHER_GPC 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_CACHE_HIT_FROM_OTHER_GPC_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_CACHE_HIT_FROM_OTHER_GPC_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_LONG_WAIT_ON_FREE_TAGS 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_LONG_WAIT_ON_FREE_TAGS_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_LONG_WAIT_ON_FREE_TAGS_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_LONG_WAIT_ON_WRITEACK 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_LONG_WAIT_ON_WRITEACK_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_LONG_WAIT_ON_WRITEACK_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_NO_FREE_CLEAN_CACHE_ENTRY 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_NO_FREE_CLEAN_CACHE_ENTRY_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_NO_FREE_CLEAN_CACHE_ENTRY_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_L2ACK_BUT_WACKFIFO_EMPTY 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_L2ACK_BUT_WACKFIFO_EMPTY_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CRD_L2ACK_BUT_WACKFIFO_EMPTY_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CPROC_LONG_WAIT_ON_RDAT 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CPROC_LONG_WAIT_ON_RDAT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CPROC_LONG_WAIT_ON_RDAT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_BLEND_FP32_NO_CHANNEL_EN 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_BLEND_FP32_NO_CHANNEL_EN_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_BLEND_FP32_NO_CHANNEL_EN_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_BLEND_SKID 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_BLEND_SKID_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_BLEND_SKID_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CWR_NO_EOCP_BW_TILES 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CWR_NO_EOCP_BW_TILES_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_CWR_NO_EOCP_BW_TILES_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_BLKACTIVITY_ERROR 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_BLKACTIVITY_ERROR_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_BLKACTIVITY_ERROR_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_HWW_ESR_EN_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF 0x005038c0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_FULLSPEED 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_03125 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_06250 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_09375 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_12500 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_15625 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_18750 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_21875 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_25000 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_28125 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_31250 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_34375 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_37500 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_40625 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_43750 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_46875 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_50000 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_53125 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_56250 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_59375 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_62500 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_65625 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_68750 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_71875 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_75000 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_78125 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_81250 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_84375 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_87500 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_90625 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_93750 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_PERF_THROTTLE_PIPE_0_96875 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x005038c4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_A 0x005038c8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_A__PRIV_LEVEL_MASK 0x005038c4 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_A_INTERCEPT 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_A_INTERCEPT_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_A_WT_1 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_A_WT_1_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_A_WT_2 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_A_WT_2_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_B 0x005038cc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_B__PRIV_LEVEL_MASK 0x005038c4 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_B_WT_3 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_B_WT_3_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_B_WT_4 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_B_WT_4_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_B_WT_5 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_B_WT_5_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_C 0x005038d0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_C__PRIV_LEVEL_MASK 0x005038c4 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_C_WT_6 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_C_WT_6_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_C_WT_7 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_C_WT_7_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_C_WT_8 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_C_WT_8_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_D 0x005038d4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_D__PRIV_LEVEL_MASK 0x005038c4 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_D_WT_9 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_D_WT_9_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_D_WT_10 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_D_WT_10_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_D_WT_11 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_D_WT_11_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_E 0x005038d8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_E__PRIV_LEVEL_MASK 0x005038c4 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_E_WT_12 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_E_WT_12_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_E_WT_13 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_E_WT_13_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_E_WT_14 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_E_WT_14_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_F 0x005038dc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_F__PRIV_LEVEL_MASK 0x005038c4 /* */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_F_WT_15 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_F_WT_15_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_F_WT_16 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_BLK_ACT_F_WT_16_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP 0x005038e0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_PART2_SEL 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_PART2_SEL_DECOMP 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_PART2_SEL_COMP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_SPARE 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_SPARE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL 12:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_PART2_SEL 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_PART2_SEL_DECOMP 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_PART2_SEL_COMP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_SPARE 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_SPARE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL 18:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_CRD 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_CRD_CACHE_CTRL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_PIPE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_PIPE_BLEND 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_CWR 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_COMP_DECOMP 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_SPARE 31:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_GROUP_SPARE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_TRIGGER 0x005038e4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_TRIGGER_MASK 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_TRIGGER_MASK_NONE 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_TRIGGER_VALUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_DEBUGPORT_TRIGGER_VALUE_ZERO 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_SETTINGS 0x005038e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_SETTINGS_BLENDER_LANA_OPT 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_SETTINGS_BLENDER_LANA_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_SETTINGS_BLENDER_LANA_OPT_ONE_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_SETTINGS_BLENDER_LANA_OPT_TWO_ONLY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_SETTINGS_BLENDER_LANA_OPT_ENABLED 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_INDEX 0x005038b4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_INDEX_ADDRESS 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_INDEX_ADDRESS_RESERVED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_INDEX_ADDRESS_MIN 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_INDEX_ADDRESS_MAX 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_INDEX_ADDRESS_NUM_LEGAL_INDICES_MINUS_ONE 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_0 0x005038ec /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_0_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_0_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_1 0x005038f0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_1_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_1_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_2 0x005038f4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_2_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_2_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_3 0x005038f8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_3_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_3_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_VALID_FLAGS 0x005038fc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_VALID_FLAGS_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROP0_CROP_ZBC_VALID_FLAGS_V_ALL_INVALID 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROP1 0x00503a00 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_ROPS 0x00503c00 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP 0x00503c5f:0x00503c00 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1 0x00503c00 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZRD_NO_COND_READ 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZRD_NO_COND_READ_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZRD_NO_COND_READ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZRD_NO_COND_READ_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_CLEAR 11:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_CLEAR_ALL_BUNDLES_ALL_GLOBAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_CLEAR_FLUSHBUNDLES_ALL_GLOBAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_CLEAR_LITE_FLUSHBUNDLES_PERGPC 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_CLEAR_NO_BUNDLES 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_CLEAR_INIT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_Z 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_Z_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_Z_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_Z_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_FORCE_L2_WAKE 31:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_FORCE_L2_WAKE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_FORCE_L2_WAKE_ON_NONIDLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_FORCE_L2_WAKE_ALWAYS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG1_FORCE_L2_WAKE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2 0x00503c04 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_FORCE_VISIBLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_FORCE_VISIBLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_FORCE_VISIBLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_FORCE_VISIBLE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_RTL_KNOBS 27:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_RTL_KNOBS_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_WRITE_FULL_BE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_WRITE_FULL_BE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_WRITE_FULL_BE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_WRITE_FULL_BE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_DISABLE_FULL_WE_OPT 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG2_ZWR_DISABLE_FULL_WE_OPT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3 0x00503c08 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_INNER_IL_COVG_AWARE 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_INNER_IL_COVG_AWARE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_INNER_IL_COVG_AWARE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_INNER_IL_COVG_AWARE_ONLY_1_STAGE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_INNER_IL_COVG_AWARE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8 7:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8_NOREDUCE 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8_FULLSIZE 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_HASHENTRIES_REDUCE_DIV8 12:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_HASHENTRIES_REDUCE_DIV8_FULLSIZE 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_HASHENTRIES_REDUCE_DIV8_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_RTL_KNOBS 27:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_RTL_KNOBS_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_COALESCE_WRITES 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_COALESCE_WRITES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_COALESCE_WRITES_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG3_COALESCE_WRITES_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4 0x00503c0c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_PM_LOCAL_TRIGGER_GPC 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_PM_LOCAL_TRIGGER_GPC_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_S8_COALESCER_LIMIT 11:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_S8_COALESCER_LIMIT_MAX 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_S8_COALESCER_LIMIT_ZERO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_S8_COALESCER_LIMIT_INIT 0x7 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_S8_COALESCER_TIMEOUT 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_S8_COALESCER_TIMEOUT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_S8_COALESCER_TIMEOUT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_BURSTY_MIN_GEAR 18:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_BURSTY_MIN_GEAR_DISABLE_BURSTING 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_BURSTY_MIN_GEAR_FULL_RANGE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_BURSTY_MIN_GEAR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_RTL_KNOBS 26:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_RTL_KNOBS_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW 28:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW_NONE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW_S8_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW_ALL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_SPARE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG4_SPARE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5 0x00503c10 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5_SRCPKTFIFO_REDUCE_DIV256 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5_SRCPKTFIFO_REDUCE_DIV256_FULLSIZE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5_HASHENTRIES_REDUCE_DIV256 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5_HASHENTRIES_REDUCE_DIV256_FULLSIZE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT0 17:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT0_ORIGINAL_GALOIS 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT0_AVOID_ROPSLICE_MAP_A 0x255 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT0_AVOID_ROPSLICE_MAP_B 0x015 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT1 27:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT1_ORIGINAL_GALOIS 0x2f6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT1_AVOID_ROPSLICE_MAP_A 0x2c4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT1_AVOID_ROPSLICE_MAP_B 0x0c4 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM 0x00503c14 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_STATIC_PATTERN_25_6_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_STATIC_PATTERN_1A_6_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2 13:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_STATIC_PATTERN_25_6_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_STATIC_PATTERN_1A_6_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_GROUP_SEL2_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP10 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP11 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP12 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP13 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP14 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_STATIC_PATTERN_25_6_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_GRP15 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_STATIC_PATTERN_1A_6_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2 25:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP10 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP11 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP12 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP13 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP14 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_STATIC_PATTERN_25_6_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_GRP15 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_STATIC_PATTERN_1A_6_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_COUNT_SEL2_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PPM_ENABLE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG 0x00503c18 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG1 0x00503c1c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS 0x00503c20 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_DECODER_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_DECODER_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_DECODER_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_DECODER_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_DECODER_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_DECODER_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_DECODER_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_DECODER_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZRDPIPE_STATUS 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_LTCTRACK_STATUS 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_LTCTRACK_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_LTCTRACK_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_LTCTRACK_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_LTCTRACK_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_LTCTRACK_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_LTCTRACK_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_LTCTRACK_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZSUB_STATUS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZSUB_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZSUB_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZSUB_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZSUB_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZSUB_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZSUB_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZSUB_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_BPC_STATUS 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_BPC_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_BPC_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_BPC_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_BPC_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_BPC_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_BPC_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_BPC_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PACKETIZER_STATUS 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PACKETIZER_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PACKETIZER_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PACKETIZER_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PACKETIZER_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PACKETIZER_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PACKETIZER_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PACKETIZER_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PIPE_STATUS 20:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PIPE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PIPE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PIPE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PIPE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PIPE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PIPE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_PIPE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZWR_STATUS 23:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZWR_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZWR_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZWR_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZWR_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZWR_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZWR_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZWR_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_RETIRE_STATUS 26:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_RETIRE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_RETIRE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_RETIRE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_RETIRE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_RETIRE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_RETIRE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_RETIRE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZCULL_STATUS 29:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZCULL_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZCULL_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZCULL_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZCULL_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZCULL_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZCULL_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_ZCULL_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_WACKFIFO_STATE 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_WACKFIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS_WACKFIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2 0x00503c24 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2_TOP 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2_TOP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2_TOP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2_TOP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2_TOP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2_TOP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2_TOP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2_TOP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2_TAGS_IN_USE_COUNT 11:3 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2_ILQUEUE_ENTRY_COUNT 18:12 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2_ZSUB_ENTRY_COUNT 27:19 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_STATUS2_VALID_CACHETILES_COUNT 31:28 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG_COUNT_REQUESTS 0x00503c28 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG_COUNT_REQUESTS_ZRD2RRH_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG_COUNT_REQUESTS_ZRD2RRH_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG_COUNT_REQUESTS_ZWR2RRH_PACKETS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG_COUNT_REQUESTS_ZWR2RRH_PACKETS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG_COUNT_RESPONSES 0x00503c2c /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZRD_RDAT_PACKETS_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZRD_RDAT_PACKETS_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZWR_ACKS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZWR_ACKS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR 0x00503c38 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_DEAD_TAGS 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_DEAD_TAGS_NOT_PRESENT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_DEAD_TAGS_PRESENT 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_DEAD_TAGS_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_RDAT_ORPHANS 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_RDAT_ORPHANS_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_RDAT_ORPHANS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_RDAT_ORPHANS_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_EOZP_MISMATCH 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_EOZP_MISMATCH_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_EOZP_MISMATCH_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_EOZP_MISMATCH_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_ZWRRAM_ORPHANS 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_ZWRRAM_ORPHANS_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_ZWRRAM_ORPHANS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_ZWRRAM_ORPHANS_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_BLKACTIVITY_ERROR 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_BLKACTIVITY_ERROR_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_BLKACTIVITY_ERROR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_BLKACTIVITY_ERROR_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_HWW_ESR_EN_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF 0x00503c54 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_FULLSPEED 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_03125 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_06250 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_09375 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_12500 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_15625 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_18750 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_21875 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_25000 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_28125 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_31250 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_34375 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_37500 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_40625 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_43750 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_46875 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_50000 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_53125 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_56250 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_59375 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_62500 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_65625 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_68750 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_71875 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_75000 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_78125 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_81250 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_84375 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_87500 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_90625 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_93750 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_PERF_THROTTLE_PIPE_0_96875 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00503c40 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_A 0x00503c44 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_A__PRIV_LEVEL_MASK 0x00503c40 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_A_INTERCEPT 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_A_INTERCEPT_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_A_WEIGHT_1 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_A_WEIGHT_1_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_A_WEIGHT_2 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_A_WEIGHT_2_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_B 0x00503c48 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_B__PRIV_LEVEL_MASK 0x00503c40 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_B_WEIGHT_3 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_B_WEIGHT_3_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_B_WEIGHT_4 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_B_WEIGHT_4_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_B_WEIGHT_5 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_B_WEIGHT_5_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_C 0x00503c4c /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_C__PRIV_LEVEL_MASK 0x00503c40 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_C_WEIGHT_6 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_C_WEIGHT_6_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_C_WEIGHT_7 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_C_WEIGHT_7_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_C_WEIGHT_8 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_C_WEIGHT_8_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_D 0x00503c50 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_D__PRIV_LEVEL_MASK 0x00503c40 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_D_WEIGHT_9 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_D_WEIGHT_9_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_D_WEIGHT_10 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_D_WEIGHT_10_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_D_WEIGHT_11 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_ZROP_BLK_ACTIVITY_D_WEIGHT_11_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH 0x00503c7f:0x00503c60 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0 0x00503c60 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RRA_FAVOR_IL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RRA_FAVOR_IL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RRA_FAVOR_IL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RRA_FAVOR_Z 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RRA_FAVOR_Z_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RRA_FAVOR_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RRA_IL_DELAY 5:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RRA_IL_DELAY_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RC_FAVOR_IL 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RC_FAVOR_IL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RC_FAVOR_IL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RC_FAVOR_Z 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RC_FAVOR_Z_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RC_FAVOR_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_WRA_FAVOR_Z 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_WRA_FAVOR_Z_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_WRA_FAVOR_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RW_ARB_BURST_SIZE 12:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RW_ARB_BURST_SIZE_ONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_RW_ARB_BURST_SIZE_INIT 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA_4TO1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA_8TO1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_CONCAT_WRITE_COMP 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_CONCAT_WRITE_COMP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_CONCAT_WRITE_COMP_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_CONCAT_WRITE_UNCOMP 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_CONCAT_WRITE_UNCOMP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_CONCAT_WRITE_UNCOMP_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_CONCAT_WRITE_FCLR 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_CONCAT_WRITE_FCLR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_CONCAT_WRITE_FCLR_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_C 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_C_WARM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_C_NONE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_Z 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_Z_WARM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_Z_NONE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_FE_MSG_FIFO_REDUCE 25:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_FE_MSG_FIFO_REDUCE_FULLSIZE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_WRITE_REQ_SB_REDUCE_DIV8 31:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG0_WRITE_REQ_SB_REDUCE_DIV8_FULLSIZE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1 0x00503c64 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_TOTAL_SLOTS_REDUCE_DIV8 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_TOTAL_SLOTS_REDUCE_DIV8_FULLSIZE 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_TOTAL_SLOTS_REDUCE_DIV8_LOW_CLAMP 0x030 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_TOTAL_SUBREQS_REDUCE_DIV8 16:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_TOTAL_SUBREQS_REDUCE_DIV8_FULLSIZE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_TOTAL_SUBREQS_REDUCE_DIV8_LOW_CLAMP 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_RESERVED_SLOTS_DIV4 22:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_RESERVED_SLOTS_DIV4_INIT 0x02 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_RESERVED_SLOTS_DIV4_LOW_CLAMP 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_RESERVED_SUBREQS_DIV4 27:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_RESERVED_SUBREQS_DIV4_INIT 0x02 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_RESERVED_SUBREQS_DIV4_LOW_CLAMP 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_SLOTMAN_ALLOCATION 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_SLOTMAN_ALLOCATION_NORMAL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_SLOTMAN_ALLOCATION_OVERRIDE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_SAFEGUARDS 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_SAFEGUARDS_ALLOW_NORMAL_OPERATION 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_SAFEGUARDS_SUPPRESS_MEMORY_ACCESS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_SAFEGUARDS_SUPPRESS_ALL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_Z_SYNC 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_Z_SYNC_COUPLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_Z_SYNC_DECOUPLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG1_Z_SYNC__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS 0x00503c68 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_TOP_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_TOP_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_TOP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_TOP_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_TOP_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_TOP_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_TOP_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_TOP_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_FAULTING_OR_HALTING 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_FAULTING_OR_HALTING_NOT_IN_PROGRESS 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_FAULTING_OR_HALTING_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_SYNCHRONIZING_C_SIDE 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_SYNCHRONIZING_C_SIDE_NOT_IN_PROGRESS 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_SYNCHRONIZING_C_SIDE_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_SYNCHRONIZING_Z_SIDE 5:5 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_SYNCHRONIZING_Z_SIDE_NOT_IN_PROGRESS 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_SYNCHRONIZING_Z_SIDE_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CNIL 6:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CIL 7:7 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZNIL 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZIL 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_WRA_STATUS_SHORT 11:10 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_WRA_STATUS_SHORT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_WRA_STATUS_SHORT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_WRA_STATUS_SHORT_STALLED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_WRA_STATUS_SHORT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_WRS_STATUS_SHORT 13:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_WRS_STATUS_SHORT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_WRS_STATUS_SHORT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_WRS_STATUS_SHORT_STALLED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_WRS_STATUS_SHORT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_RWA_STATUS 16:14 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_RWA_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_RWA_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_RWA_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_RWA_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_RWA_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_RWA_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_RRH_RWA_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_ACK 17:17 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_ACK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_ACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_CREDIT 18:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_CREDIT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_CREDIT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_MSG_FIFO 19:19 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_MSG_FIFO_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_MSG_FIFO_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_MEMBAR_ACK 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_MEMBAR_ACK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_MEMBAR_ACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_SCOREBOARD_ID 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_SCOREBOARD_ID_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_SCOREBOARD_ID_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_WDAT 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_WDAT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_WAIT_FOR_WDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_SCOREBOARD_NONEMPTY 23:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_SCOREBOARD_NONEMPTY_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_WRS_SCOREBOARD_NONEMPTY_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CIL 24:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CNIL 25:25 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZIL 26:26 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZNIL 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READPIPE_STATE 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READPIPE_STATE_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READPIPE_STATE_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READPIPE_STATE_STALLED_BY_RWA 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READPIPE_STATE_AWAITING_MEMSYS_RESPONSE 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READPIPE_STATE_STALLED_RRH2CRD_CNIL 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READPIPE_STATE_STALLED_RRH2CRD_CIL 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READPIPE_STATE_STALLED_RRH2ZRD_ZNIL 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READPIPE_STATE_STALLED_RRH2ZRD_ZIL 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READPIPE_STATE_SYNC_STALL 0x8 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_STATUS_READPIPE_STATE_OTHER 0x9 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0 0x00503c6c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_RD 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_WR 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_RD 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_WR 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_MEMBAR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_MEMBAR_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_RD 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_WR 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_MEMBAR 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_MEMBAR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_RD 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_WR 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_RD 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_WR 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_RD 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_WR 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD_FORCE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR_FORCE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_MEMBAR 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_MEMBAR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_MEMBAR_FORCE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_BLOCK_RD 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_MEMBAR 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_MEMBAR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_RD 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_WR 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_MEMBAR 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_MEMBAR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM 0x00503c70 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL_GRP_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2 13:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_GROUP_SEL2_GRP_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_PPM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG 0x00503c74 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG1 0x00503c78 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG3 0x00503c7c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_256 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_1024 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_4096 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_16384 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP 0x00503cff:0x00503c80 /* RW--L */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1 0x00503c80 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CRD_COND_READ 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CRD_COND_READ_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CRD_COND_READ_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CRD_CREAD 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CRD_CREAD_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CRD_CREAD_FORCE_CREAD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CRD_CREAD_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_KNOBS 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_KNOBS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_RDSUPPRESS 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_RDSUPPRESS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_RDSUPPRESS_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_RDSUPPRESS_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_WRSUPPRESS 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_WRSUPPRESS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_WRSUPPRESS_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_WRSUPPRESS_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_CLEAR 16:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_CLEAR_ALL_BUNDLES_ALL_GLOBAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_CLEAR_FLUSHBUNDLES_ALL_GLOBAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_CACHE_CLEAR_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_WRITE_FULL_BE 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_WRITE_FULL_BE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_WRITE_FULL_BE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG1_WRITE_FULL_BE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2 0x00503c84 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_CACHE_ENTRY_ID_LIMIT 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_CACHE_ENTRY_ID_LIMIT_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT 17:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_ONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_TWO 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_THREE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_FOUR 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_FIVE 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_SIX 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_SEVEN 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_DISABLE 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_INIT 0x7 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_WR_OPT 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_WR_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_WR_OPT_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG2_WR_OPT_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3 0x00503c88 /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_BLENDOPT_KILL 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_BLENDOPT_KILL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_BLENDOPT_KILL_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_BLENDOPT_FILL_OVERRIDE 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_BLENDOPT_FILL_OVERRIDE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_BLENDOPT_FILL_OVERRIDE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_C8_C16_DISABLE_COND_READ 4:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_NEVER 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_FOR_C8_1XAA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_FOR_CLEAR 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_ALWAYS 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_ARITHMETIC_SUCCESS 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_ARITHMETIC_SUCCESS_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_ARITHMETIC_SUCCESS_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_REDUCTION_SUCCESS 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_REDUCTION_SUCCESS_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_REDUCTION_SUCCESS_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_ARITHMETIC_DISABLE 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_ARITHMETIC_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_ARITHMETIC_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_REDUCTION_DISABLE 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_REDUCTION_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_REDUCTION_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_PROCESS_REDUCED_DISABLE 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_PROCESS_REDUCED_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_PROCESS_REDUCED_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_BOTH_DISABLE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_BOTH_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_BOTH_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_TIE_UP 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_TIE_UP_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_TIE_UP_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_ZBC_DISABLE 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_ZBC_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_ZBC_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_CC_DISABLE 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_CC_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_CC_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_UCOMP_MIXED_DISABLE 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_UCOMP_MIXED_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_UCOMP_MIXED_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT 23:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_128K 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_512K 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_2M 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_8M 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_32M 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_64M 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_128M 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_256M 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_512M 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_768M 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_1024M 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_1536M 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_2048M 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_NEVER 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_INIT 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA 25:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA_4TO1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA_8TO1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_TAG_FLUSH_CTL 27:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_TAG_FLUSH_CTL_ENTER_DECOMP_IN_PLACE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_TAG_FLUSH_CTL_CHANGE_DECOMP_IN_PLACE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_TAG_FLUSH_CTL_CHANGE_CLEAR_MODE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_TAG_FLUSH_CTL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4 0x00503c8c /* RWI4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_SRCPKTFIFO_REDUCE_DIV8 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_SRCPKTFIFO_REDUCE_DIV8_FULLSIZE 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_SRCPKTFIFO_REDUCE_DIV8_INIT 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_HASHENTRIES_REDUCE_DIV8 17:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_HASHENTRIES_REDUCE_DIV8_FULLSIZE 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_HASHENTRIES_REDUCE_DIV8_INIT 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_CLAMP_FP_BLEND 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_RMW_DISABLE_FORCE_ZERO 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_RMW_DISABLE_FORCE_ZERO_NO_FORCE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_RMW_DISABLE_FORCE_ZERO_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_PITCH_FORCE_DISALLOW_PLC 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_PITCH_FORCE_DISALLOW_PLC_NO_FORCE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_PITCH_FORCE_DISALLOW_PLC_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM 0x00503c94 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_STATIC_PATTERN_A55A_16_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_STATIC_PATTERN_5AA5_16_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2 13:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_STATIC_PATTERN_A55A_16_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_STATIC_PATTERN_5AA5_16_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_GROUP_SEL2_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PPM_ENABLE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG 0x00503c98 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG1 0x00503c9c /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1 0x00503ca0 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_RETIRE_STATUS 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_RETIRE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_RETIRE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_RETIRE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_RETIRE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_RETIRE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_RETIRE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_RETIRE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CSUB_STATUS 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CSUB_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CSUB_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CSUB_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CSUB_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CSUB_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CSUB_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CSUB_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_PIPE_STATUS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_PIPE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_PIPE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_PIPE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_PIPE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_PIPE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_PIPE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_PIPE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CWR_STATUS 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CWR_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CWR_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CWR_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CWR_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CWR_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CWR_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CWR_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_DECOMP_STATUS 16:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_DECOMP_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_DECOMP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_DECOMP_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_DECOMP_STATUS_STALLED 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_COMP_STATUS 18:17 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_COMP_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_COMP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_COMP_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_COMP_STATUS_STALLED 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_BLEND_STATUS 19:19 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_BLEND_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_BLEND_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_IL_NIL_FIFO_STATE 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_IL_NIL_FIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_IL_NIL_FIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_SEMAACK_FIFO_STATE 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_SEMAACK_FIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_SEMAACK_FIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_WACKFIFO_STATE 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_WACKFIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_WACKFIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_CC_STATE 26:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_CC_STATE_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_CC_STATE_GLOBAL_FLUSH_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_CC_STATE_PASS_PKTS 0xa /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_CC_STATE_PASS_BUNDLES 0xb /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_CC_STATE_PASS_EARLY_QUADS 0xc /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_TILE_IN_FLIGHT 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_TILE_IN_FLIGHT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_TILE_IN_FLIGHT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION 30:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRNL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRNL_1 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRNM 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRTM 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRNL 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRNL_1 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRNM 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRTM 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_WAITING_FOR_FLUSH 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_WAITING_FOR_FLUSH_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS1_CRD_WAITING_FOR_FLUSH_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS2 0x00503ca4 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS2_TOP 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS2_TOP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS2_TOP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS2_TOP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS2_TOP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS2_TOP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS2_TOP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS2_TOP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS2_TAGS_IN_USE_COUNT 12:3 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS2_ILQUEUE_ENTRY_COUNT 22:13 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS2_CSUB_ENTRY_COUNT 31:23 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3 0x00503ca8 /* R--4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_RED_PREFETCH_ILOCK 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_RED_PREFETCH_ILOCK_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_RED_PREFETCH_ILOCK_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_WAIT_FOR_RDAT 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_WAIT_FOR_RDAT_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_WAIT_FOR_RDAT_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_SAMPLE_CONFLICT_ILOCK 2:2 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_SAMPLE_CONFLICT_ILOCK_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_SAMPLE_CONFLICT_ILOCK_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_SURFACE_KIND 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_SURFACE_KIND_BL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_SURFACE_KIND_PITCH 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_S0_STATE 5:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_S0_STATE_FIRST_OF_TILE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_S0_STATE_FIRST_OF_QUAD 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_S0_STATE_EXPAND_QUAD 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_S0_STATE_CUM_FILL 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CWR_RETIRE_QUEUE 7:7 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CWR_RETIRE_QUEUE_HASROOM 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CWR_RETIRE_QUEUE_FULL 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_INT_COMPUTE_ILOCK 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_INT_COMPUTE_ILOCK_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_CPROC_INT_COMPUTE_ILOCK_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_VALID_CACHETILES_COUNT 14:9 /* R-XUF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_SPARE 31:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_STATUS3_SPARE_DEFAULT 0x00000 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG_COUNT_REQUESTS 0x00503cac /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG_COUNT_REQUESTS_CRD2RRH_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG_COUNT_REQUESTS_CRD2RRH_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG_COUNT_REQUESTS_CWR2RRH_PACKETS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG_COUNT_REQUESTS_CWR2RRH_PACKETS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG_COUNT_RESPONSES 0x00503cb0 /* R-E4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG_COUNT_RESPONSES_RRH2CRD_RDAT_PACKETS_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG_COUNT_RESPONSES_RRH2CRD_RDAT_PACKETS_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG_COUNT_RESPONSES_RRH2CWR_ACKS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUG_COUNT_RESPONSES_RRH2CWR_ACKS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR 0x00503cbc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_DEAD_TAGS 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_DEAD_TAGS_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_DEAD_TAGS_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_CACHE_HIT_FROM_OTHER_GPC 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_CACHE_HIT_FROM_OTHER_GPC_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_CACHE_HIT_FROM_OTHER_GPC_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_LONG_WAIT_ON_FREE_TAGS 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_LONG_WAIT_ON_FREE_TAGS_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_LONG_WAIT_ON_FREE_TAGS_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_LONG_WAIT_ON_WRITEACK 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_LONG_WAIT_ON_WRITEACK_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_LONG_WAIT_ON_WRITEACK_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_NO_FREE_CLEAN_CACHE_ENTRY 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_NO_FREE_CLEAN_CACHE_ENTRY_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_NO_FREE_CLEAN_CACHE_ENTRY_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_L2ACK_BUT_WACKFIFO_EMPTY 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_L2ACK_BUT_WACKFIFO_EMPTY_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CRD_L2ACK_BUT_WACKFIFO_EMPTY_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CPROC_LONG_WAIT_ON_RDAT 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CPROC_LONG_WAIT_ON_RDAT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CPROC_LONG_WAIT_ON_RDAT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_BLEND_FP32_NO_CHANNEL_EN 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_BLEND_FP32_NO_CHANNEL_EN_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_BLEND_FP32_NO_CHANNEL_EN_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_BLEND_SKID 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_BLEND_SKID_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_BLEND_SKID_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CWR_NO_EOCP_BW_TILES 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CWR_NO_EOCP_BW_TILES_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_CWR_NO_EOCP_BW_TILES_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_BLKACTIVITY_ERROR 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_BLKACTIVITY_ERROR_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_BLKACTIVITY_ERROR_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_HWW_ESR_EN_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF 0x00503cc0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_FULLSPEED 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_03125 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_06250 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_09375 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_12500 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_15625 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_18750 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_21875 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_25000 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_28125 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_31250 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_34375 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_37500 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_40625 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_43750 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_46875 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_50000 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_53125 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_56250 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_59375 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_62500 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_65625 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_68750 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_71875 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_75000 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_78125 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_81250 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_84375 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_87500 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_90625 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_93750 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_PERF_THROTTLE_PIPE_0_96875 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00503cc4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_A 0x00503cc8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_A__PRIV_LEVEL_MASK 0x00503cc4 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_A_INTERCEPT 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_A_INTERCEPT_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_A_WT_1 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_A_WT_1_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_A_WT_2 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_A_WT_2_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_B 0x00503ccc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_B__PRIV_LEVEL_MASK 0x00503cc4 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_B_WT_3 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_B_WT_3_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_B_WT_4 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_B_WT_4_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_B_WT_5 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_B_WT_5_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_C 0x00503cd0 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_C__PRIV_LEVEL_MASK 0x00503cc4 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_C_WT_6 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_C_WT_6_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_C_WT_7 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_C_WT_7_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_C_WT_8 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_C_WT_8_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_D 0x00503cd4 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_D__PRIV_LEVEL_MASK 0x00503cc4 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_D_WT_9 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_D_WT_9_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_D_WT_10 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_D_WT_10_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_D_WT_11 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_D_WT_11_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_E 0x00503cd8 /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_E__PRIV_LEVEL_MASK 0x00503cc4 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_E_WT_12 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_E_WT_12_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_E_WT_13 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_E_WT_13_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_E_WT_14 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_E_WT_14_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_F 0x00503cdc /* RW-4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_F__PRIV_LEVEL_MASK 0x00503cc4 /* */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_F_WT_15 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_F_WT_15_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_F_WT_16 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_BLK_ACT_F_WT_16_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP 0x00503ce0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_PART2_SEL 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_PART2_SEL_DECOMP 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_PART2_SEL_COMP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_SPARE 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_SPARE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL 12:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_PART2_SEL 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_PART2_SEL_DECOMP 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_PART2_SEL_COMP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_SPARE 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_SPARE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL 18:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_CRD 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_CRD_CACHE_CTRL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_PIPE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_PIPE_BLEND 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_CWR 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_COMP_DECOMP 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_SPARE 31:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_GROUP_SPARE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_TRIGGER 0x00503ce4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_TRIGGER_MASK 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_TRIGGER_MASK_NONE 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_TRIGGER_VALUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_DEBUGPORT_TRIGGER_VALUE_ZERO 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_SETTINGS 0x00503ce8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_SETTINGS_BLENDER_LANA_OPT 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_SETTINGS_BLENDER_LANA_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_SETTINGS_BLENDER_LANA_OPT_ONE_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_SETTINGS_BLENDER_LANA_OPT_TWO_ONLY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_SETTINGS_BLENDER_LANA_OPT_ENABLED 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_INDEX 0x00503cb4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_INDEX_ADDRESS 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_INDEX_ADDRESS_RESERVED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_INDEX_ADDRESS_MIN 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_INDEX_ADDRESS_MAX 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_INDEX_ADDRESS_NUM_LEGAL_INDICES_MINUS_ONE 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_0 0x00503cec /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_0_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_0_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_1 0x00503cf0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_1_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_1_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_2 0x00503cf4 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_2_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_2_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_3 0x00503cf8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_3_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_3_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_VALID_FLAGS 0x00503cfc /* RWE4R */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_VALID_FLAGS_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPC0_ROPS_CROP_ZBC_VALID_FLAGS_V_ALL_INVALID 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPC1 0x00508000 /* RW--L */ #define NV_PGRAPH_PRI_GPC1_GPCCS_FS_GPC 0x0050a608 /* R--4R */ #define NV_PGRAPH_PRI_GPC1_GPCCS_CG 0x0050a890 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_ZCULL_CG 0x00508970 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_SWDX_CG 0x00508e0c /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_MMU_CG 0x00508898 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_PROP_CG 0x00508500 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_FRSTR_CG 0x00508608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_WIDCLIP_CG 0x00508688 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TC_CG 0x00508718 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_RASTERARB_PM_CTRL 0x00508384 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_SETUP_CG 0x00508828 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_CRSTR_CG 0x00508bbc /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_GPM_PD_PES_TPC_ID_MASK(i) (0x00508c30+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_GPC1_GPM_PD_PES_TPC_ID_MASK__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPC1_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC1_GPM_PD_CG 0x00508c70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_GPM_SD_CG 0x00508cf0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_GPM_RPT_CG 0x00508d70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_WDXPS_CG 0x00508f0c /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_GCC_CG 0x00509020 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC0_TPCCS_TPC_ACTIVITY0 0x0050c500 /* R--4R */ #define NV_PGRAPH_PRI_GPC1_TPC0_TPCCS_DEBUG 0x0050c510 /* RW-4R */ #define NV_PGRAPH_PRI_GPC1_TPC0_PE_CG 0x0050c068 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC0_SM_PM_CTRL 0x0050c304 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC0_SM_CONFIG 0x0050c608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC0_TEX_D_CG 0x0050c260 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC0_MPC_CG 0x0050c470 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC1_TPCCS_DEBUG 0x0050cd10 /* RW-4R */ #define NV_PGRAPH_PRI_GPC1_TPC1_PE_CG 0x0050c868 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC1_SM_PM_CTRL 0x0050cb04 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC1_SM_CONFIG 0x0050ce08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC1_TEX_W_CG 0x0050ca58 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC1_TEX_D_CG 0x0050ca60 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC1_MPC_CG 0x0050cc70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC2_PE_CG 0x0050d068 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC2_SM_CONFIG 0x0050d608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC2_TEX_D_CG 0x0050d260 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC2_MPC_CG 0x0050d470 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC3_PE_CG 0x0050d868 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC3_SM_CONFIG 0x0050de08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC3_TEX_D_CG 0x0050da60 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC3_MPC_CG 0x0050dc70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC4_PE_CG 0x0050e068 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC4_SM_CONFIG 0x0050e608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC4_TEX_D_CG 0x0050e260 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC4_MPC_CG 0x0050e470 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPC5_SM_CONFIG 0x0050ee08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_TPCS_SM_CONFIG 0x00509e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_PPC0_PES_CG 0x0050b028 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_PPC0_WWDX_CG 0x0050b1e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_PPC0_CBM_CG 0x0050b0d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_PPC1_PES_CG 0x0050b228 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_PPC1_WWDX_CG 0x0050b3e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_PPC1_CBM_CG 0x0050b2d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_PPC2_PES_CG 0x0050b428 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_PPC2_WWDX_CG 0x0050b5e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC1_PPC2_CBM_CG 0x0050b4d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2 0x00510000 /* RW--L */ #define NV_PGRAPH_PRI_GPC2_GPCCS_FS_GPC 0x00512608 /* R--4R */ #define NV_PGRAPH_PRI_GPC2_GPCCS_CG 0x00512890 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_ZCULL_CG 0x00510970 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_SWDX_CG 0x00510e0c /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_MMU_CG 0x00510898 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_PROP_CG 0x00510500 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_FRSTR_CG 0x00510608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_WIDCLIP_CG 0x00510688 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TC_CG 0x00510718 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_RASTERARB_PM_CTRL 0x00510384 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_SETUP_CG 0x00510828 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_CRSTR_CG 0x00510bbc /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_GPM_PD_PES_TPC_ID_MASK(i) (0x00510c30+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_GPC2_GPM_PD_PES_TPC_ID_MASK__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPC2_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC2_GPM_PD_CG 0x00510c70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_GPM_SD_CG 0x00510cf0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_GPM_RPT_CG 0x00510d70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_WDXPS_CG 0x00510f0c /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_GCC_CG 0x00511020 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC0_TPCCS_DEBUG 0x00514510 /* RW-4R */ #define NV_PGRAPH_PRI_GPC2_TPC0_PE_CG 0x00514068 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC0_SM_PM_CTRL 0x00514304 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC0_SM_CONFIG 0x00514608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC0_TEX_D_CG 0x00514260 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC0_MPC_CG 0x00514470 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC1_TPCCS_DEBUG 0x00514d10 /* RW-4R */ #define NV_PGRAPH_PRI_GPC2_TPC1_PE_CG 0x00514868 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC1_SM_PM_CTRL 0x00514b04 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC1_SM_CONFIG 0x00514e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC1_TEX_W_CG 0x00514a58 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC1_TEX_D_CG 0x00514a60 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC1_MPC_CG 0x00514c70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC2_PE_CG 0x00515068 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC2_SM_CONFIG 0x00515608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC2_TEX_D_CG 0x00515260 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC2_MPC_CG 0x00515470 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC3_PE_CG 0x00515868 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC3_SM_CONFIG 0x00515e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC3_TEX_D_CG 0x00515a60 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC3_MPC_CG 0x00515c70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC4_PE_CG 0x00516068 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC4_SM_CONFIG 0x00516608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC4_TEX_D_CG 0x00516260 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC4_MPC_CG 0x00516470 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPC5_SM_CONFIG 0x00516e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_TPCS_SM_CONFIG 0x00511e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_PPC0_PES_CG 0x00513028 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_PPC0_WWDX_CG 0x005131e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_PPC0_CBM_CG 0x005130d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_PPC1_PES_CG 0x00513228 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_PPC1_WWDX_CG 0x005133e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_PPC1_CBM_CG 0x005132d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_PPC2_PES_CG 0x00513428 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_PPC2_WWDX_CG 0x005135e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC2_PPC2_CBM_CG 0x005134d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3 0x00518000 /* RW--L */ #define NV_PGRAPH_PRI_GPC3_GPCCS_FS_GPC 0x0051a608 /* R--4R */ #define NV_PGRAPH_PRI_GPC3_GPCCS_CG 0x0051a890 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_ZCULL_CG 0x00518970 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_SWDX_CG 0x00518e0c /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_MMU_CG 0x00518898 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_PROP_CG 0x00518500 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_FRSTR_CG 0x00518608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_WIDCLIP_CG 0x00518688 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TC_CG 0x00518718 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_RASTERARB_PM_CTRL 0x00518384 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_SETUP_CG 0x00518828 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_CRSTR_CG 0x00518bbc /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_GPM_PD_PES_TPC_ID_MASK(i) (0x00518c30+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_GPC3_GPM_PD_PES_TPC_ID_MASK__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPC3_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC3_GPM_PD_CG 0x00518c70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_GPM_SD_CG 0x00518cf0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_GPM_RPT_CG 0x00518d70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_WDXPS_CG 0x00518f0c /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_GCC_CG 0x00519020 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC0_TPCCS_DEBUG 0x0051c510 /* RW-4R */ #define NV_PGRAPH_PRI_GPC3_TPC0_PE_CG 0x0051c068 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC0_SM_PM_CTRL 0x0051c304 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC0_SM_CONFIG 0x0051c608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC0_TEX_W_CG 0x0051c258 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC0_TEX_D_CG 0x0051c260 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC0_MPC_CG 0x0051c470 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC1_PE_CG 0x0051c868 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC1_SM_PM_CTRL 0x0051cb04 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC1_SM_CONFIG 0x0051ce08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC1_TEX_W_CG 0x0051ca58 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC1_TEX_D_CG 0x0051ca60 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC1_MPC_CG 0x0051cc70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC2_PE_CG 0x0051d068 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC2_SM_CONFIG 0x0051d608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC2_TEX_D_CG 0x0051d260 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC2_MPC_CG 0x0051d470 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC3_PE_CG 0x0051d868 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC3_SM_CONFIG 0x0051de08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC3_TEX_D_CG 0x0051da60 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC3_MPC_CG 0x0051dc70 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC4_PE_CG 0x0051e068 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC4_SM_CONFIG 0x0051e608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC4_TEX_D_CG 0x0051e260 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC4_MPC_CG 0x0051e470 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPC5_SM_CONFIG 0x0051ee08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_TPCS_SM_CONFIG 0x00519e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_PPC0_PES_CG 0x0051b028 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_PPC0_WWDX_CG 0x0051b1e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_PPC0_CBM_CG 0x0051b0d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_PPC1_PES_CG 0x0051b228 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_PPC1_WWDX_CG 0x0051b3e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_PPC1_CBM_CG 0x0051b2d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_PPC2_PES_CG 0x0051b428 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_PPC2_WWDX_CG 0x0051b5e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPC3_PPC2_CBM_CG 0x0051b4d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPC4 0x00520000 /* RW--L */ #define NV_PGRAPH_PRI_GPC4_GPCCS_FS_GPC 0x00522608 /* R--4R */ #define NV_PGRAPH_PRI_GPC4_GPM_PD_PES_TPC_ID_MASK(i) (0x00520c30+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_GPC4_GPM_PD_PES_TPC_ID_MASK__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPC4_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC4_TPC0_SM_CONFIG 0x00524608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC4_TPC1_SM_CONFIG 0x00524e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC4_TPC2_SM_CONFIG 0x00525608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC4_TPC3_SM_CONFIG 0x00525e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC4_TPC4_SM_CONFIG 0x00526608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC4_TPC5_SM_CONFIG 0x00526e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC4_TPCS_SM_CONFIG 0x00521e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC5 0x00528000 /* RW--L */ #define NV_PGRAPH_PRI_GPC5_GPCCS_FS_GPC 0x0052a608 /* R--4R */ #define NV_PGRAPH_PRI_GPC5_GPM_PD_PES_TPC_ID_MASK(i) (0x00528c30+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_GPC5_GPM_PD_PES_TPC_ID_MASK__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPC5_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 /* R--VF */ #define NV_PGRAPH_PRI_GPC5_TPC0_SM_CONFIG 0x0052c608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC5_TPC1_SM_CONFIG 0x0052ce08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC5_TPC2_SM_CONFIG 0x0052d608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC5_TPC3_SM_CONFIG 0x0052de08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC5_TPC4_SM_CONFIG 0x0052e608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC5_TPC5_SM_CONFIG 0x0052ee08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC5_TPCS_SM_CONFIG 0x00529e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC6 0x00530000 /* RW--L */ #define NV_PGRAPH_PRI_GPC6_TPC0_SM_CONFIG 0x00534608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC6_TPC1_SM_CONFIG 0x00534e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC6_TPC2_SM_CONFIG 0x00535608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC6_TPC3_SM_CONFIG 0x00535e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC6_TPC4_SM_CONFIG 0x00536608 /* RWE4R */ #define NV_PGRAPH_PRI_GPC6_TPC5_SM_CONFIG 0x00536e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPC6_TPCS_SM_CONFIG 0x00531e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS 0x00418000 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_ATOM_SIZE 4096 #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_ATOM_SIZE_LG2 0xC #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK 0x0041a280 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK 0x0041a284 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK 0x0041a288 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK 0x0041a28c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK 0x0041a290 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK 0x0041a294 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK 0x0041a0e8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK 0x0041a298 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x8 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK 0x0041a29c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK 0x0041a3d0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK 0x0041a3f0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK 0x0041a3f4 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK 0x0041a3f8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK 0x0041a3fc /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(i) (0x0041a18c+(i)*16) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(i) (0x0041a2b0+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK 0x0041a190 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK 0x0041a194 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK 0x0041a198 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK 0x0041a19c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK 0x0041a1a0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK 0x0041a1a4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK 0x0041a1a8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK 0x0041a1b0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK 0x0041a1bc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK 0x0041a1e0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK 0x0041a1e4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK 0x0041a1e8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK 0x0041a1ec /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK 0x0041a1f0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK 0x0041a1f4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK 0x0041a1f8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK 0x0041a1fc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK 0x0041a220 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK 0x0041a224 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK 0x0041a22c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET 0x0041a000 /* -W-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_GPTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_WDTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_MTHD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_HALT 4:4 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_HALT_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXTERR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_SWGEN0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_SWGEN1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT 15:8 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ1 8:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ1_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ2 9:9 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ2_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ3 10:10 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ3_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ4 11:11 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ4_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ5 12:12 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ5_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ6 13:13 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ6_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ7 14:14 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ7_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ8 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ8_SET 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_DMA 16:16 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSSET_DMA_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR 0x0041a004 /* -W-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_GPTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_WDTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_MTHD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_HALT_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXTERR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_SWGEN0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_SWGEN1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT 15:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCLR_DMA_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT 0x0041a008 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_GPTMR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_GPTMR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_WDTMR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_WDTMR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_MTHD_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_MTHD_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_CTXSW_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_CTXSW_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_HALT_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_HALT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXTERR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXTERR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_SWGEN0_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_SWGEN0_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_SWGEN1_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_SWGEN1_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT 15:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_DMA_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSTAT_DMA_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE 0x0041a00c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE__PRIV_LEVEL_MASK 0x0041a290 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_GPTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_MTHD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_MTHD_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_MTHD_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_CTXSW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_HALT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_HALT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_HALT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXTERR_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_INIT 0xfc /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ1 8:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ2 9:9 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ3 10:10 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ4 11:11 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ5 12:12 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ6 13:13 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ7 14:14 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ8 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_DMA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_DMA_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMODE_LVL_DMA_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK 0x0041a0e0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK__PRIV_LEVEL_MASK 0x0041a1a4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_GPTMR_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_GPTMR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_WDTMR_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_WDTMR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_MTHD_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_MTHD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_CTXSW_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_CTXSW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_HALT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_HALT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXTERR_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXTERR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_ENABLE 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_DISABLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ1 8:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ2 9:9 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ3 10:10 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ4 11:11 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ4_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ4_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ5 12:12 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ5_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ5_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ6 13:13 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ6_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ6_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ7 14:14 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ7_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ7_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ8 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ8_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ8_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_DMA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQSCMASK_DMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET 0x0041a010 /* -W-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET__PRIV_LEVEL_MASK 0x0041a290 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_GPTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_WDTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_MTHD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_HALT 4:4 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_HALT_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXTERR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_SWGEN0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_SWGEN1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT 15:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_DMA 16:16 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMSET_DMA_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR 0x0041a014 /* -W-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR__PRIV_LEVEL_MASK 0x0041a290 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_GPTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_WDTMR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_MTHD_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_CTXSW_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_HALT_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXTERR_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_SWGEN0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_SWGEN1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT 15:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMCLR_DMA_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK 0x0041a018 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_GPTMR_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_GPTMR_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_WDTMR_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_WDTMR_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_MTHD_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_MTHD_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_CTXSW_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_CTXSW_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_HALT 4:4 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_HALT_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_HALT_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXTERR_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXTERR_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_SWGEN0_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_SWGEN0_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_SWGEN1_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_SWGEN1_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT 15:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_DMA 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_DMA_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQMASK_DMA_DISABLE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST 0x0041a01c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST__PRIV_LEVEL_MASK 0x0041a290 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_GPTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_GPTMR_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_WDTMR_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_MTHD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_MTHD_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_MTHD_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_CTXSW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_CTXSW_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_HALT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_HALT_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_HALT_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXTERR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXTERR_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT 15:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_MTHD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_HALT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT 31:24 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST2 0x0041a03c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST2__PRIV_LEVEL_MASK 0x0041a290 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST2_HOST_DMA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST2_HOST_DMA_FALCON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST2_HOST_DMA_HOST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST2_TARGET_DMA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRINT 0x0041a020 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRINT__PRIV_LEVEL_MASK 0x0041a1a0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRVAL 0x0041a024 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRVAL__PRIV_LEVEL_MASK 0x0041a1a0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRCTL 0x0041a028 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRCTL__PRIV_LEVEL_MASK 0x0041a1a0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRCTL_GPTMREN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER0 0x0041a02c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER0__PRIV_LEVEL_MASK 0x0041a1bc /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER0_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER1 0x0041a030 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER1__PRIV_LEVEL_MASK 0x0041a1bc /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PTIMER1_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRVAL 0x0041a034 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRVAL__PRIV_LEVEL_MASK 0x0041a29c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRCTL 0x0041a038 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRCTL__PRIV_LEVEL_MASK 0x0041a29c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRCTL_WDTMREN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDDATA 0x0041a064 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDDATA__PRIV_LEVEL_MASK 0x0041a294 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDID 0x0041a068 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDID__PRIV_LEVEL_MASK 0x0041a294 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDID_ID 11:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDID_PRIV 15:15 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDID_PRIV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDID_PRIV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDID_WPEND 16:16 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDID_WPEND_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDID_WPEND_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDWDAT 0x0041a06c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDWDAT__PRIV_LEVEL_MASK 0x0041a294 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCOUNT 0x0041a070 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK 0x0041a294 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDCOUNT_COUNT_INIT 0x0000 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDPOP 0x0041a074 /* -W-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDPOP__PRIV_LEVEL_MASK 0x0041a294 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDPOP_POP 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDPOP_POP_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDPOP_POP_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDRAMSZ 0x0041a078 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK 0x0041a294 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX 0x0041a050 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX__PRIV_LEVEL_MASK 0x0041a294 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX_CTXVLD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX_CTXVLD_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX_CTXVLD_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX_CTXTGT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CURCTX_CTXPTR_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX 0x0041a054 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX__PRIV_LEVEL_MASK 0x0041a294 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX_CTXVLD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX_CTXVLD_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX_CTXVLD_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX_CTXTGT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_NXTCTX_CTXPTR_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CTXACK 0x0041a058 /* -W-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CTXACK__PRIV_LEVEL_MASK 0x0041a294 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CTXACK_SAVE_ACK_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CTXACK_SAVE_ACK_CLEAR 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CTXACK_REST_ACK_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CTXACK_REST_ACK_CLEAR 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MAILBOX0 0x0041a040 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MAILBOX1 0x0041a044 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN 0x0041a048 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN__PRIV_LEVEL_MASK 0x0041a294 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_CTXEN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_CTXEN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_CTXEN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_MTHDEN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_MTHDEN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_MTHDEN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_PRIV_POSTWR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_CTXSW_NACK_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_CTXSW_NACK_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE 0x0041a04c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE__PRIV_LEVEL_MASK 0x0041a1e0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_FHSTATE 0x0041a05c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_FHSTATE__PRIV_LEVEL_MASK 0x0041a1e4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_FHSTATE_STALL_REQ_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_FHSTATE_STALL_REQ_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE 0x0041a060 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE__PRIV_LEVEL_MASK 0x0041a3d0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRIVSTATE_PRIV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SFTRESET 0x0041a07c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SFTRESET__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SFTRESET_EXT 0:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SFTRESET_EXT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SFTRESET_EXT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL 0x0041a0a4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_STALLREQ_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_STALLREQ_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_STALLACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ENGCTL_STALLACK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR 0x0041a0ac /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB 11:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_EXT 11:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x0041a10c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFBASE 0x0041a110 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFBASE__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFMOFFS 0x0041a114 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFMOFFS_OFFS_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD 0x0041a118 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_FULL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_FULL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_IDLE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_IDLE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_IMEM_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_IMEM_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_WRITE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_WRITE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_NOTIFY_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_NOTIFY_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SIZE_4B 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SIZE_8B 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SIZE_16B 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SIZE_32B 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SIZE_64B 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SIZE_128B 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SIZE_256B 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_ERROR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_ERROR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFFBOFFS 0x0041a11c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB 0x0041a120 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP 0x0041a124 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_LOW 0x0041a2c0 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_HIGH 0x0041a2c4 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_LOW 0x0041a2c8 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_HIGH 0x0041a2cc /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_LOW 0x0041a2d0 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_HIGH 0x0041a2d4 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_LOW 0x0041a2d8 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_HIGH 0x0041a2dc /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL 0x0041a2e0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_ERR_TAG_HIGH 0x0041a2e4 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_ERR_TAG_LOW 0x0041a2e8 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK 0x0041a190 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x0041a180+(i)*16) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 23:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCR 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_SECURE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_SECURE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_SEC_LOCK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_SEC_LOCK_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x0041a184+(i)*16) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x0041a188+(i)*16) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_FAULT_CORRECTED 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_FAULT_CORRECTED_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_FAULT_UNCORRECTED 17:17 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_FAULT_UNCORRECTED_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x0041a1c0+(i)*8) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_ADDRESS_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS_INIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 23:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK_INIT 0x0000 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCR 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_SETTAG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_SETTAG_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_SETTAG_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_SETLVL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_SETLVL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_SETLVL_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_VA 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_VA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_VA_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_VA_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_MISS 29:29 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_MISS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_MISS_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_MULTIHIT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_MULTIHIT_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_LVLERR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_LVLERR_FALSE 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x0041a1c4+(i)*8) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMT(i) (0x0041a210+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMT__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMT__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMT_TAG 15:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMT_FAULTED 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMT_FAULTED_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEML(i) (0x0041a2a0+(i)*4) /* -W-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEML__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEML__PRIV_LEVEL_MASK NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEML_LVL 2:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_DUMMY 0x0041a258 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK 0x0041a284 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_DUMMY 0x0041a1b4 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK 0x0041a280 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x0041a300+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK 0x0041a3f0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x0041a310+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK 0x0041a3f4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x0041a320+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x0041a3f8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x0041a330+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK 0x0041a3fc /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRGNVER 0x0041a3d4 /* R-I4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRGNVER_MAJOR_DEFT 0x2 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRGNVER_MINOR_DEFT 0x0000 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PRGNVER_BUGFIX_DEFT 0x0000 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x0041a108 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1 0x0041a12c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_INIT 0x6 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_1_0 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_2_0 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_3_0 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_4_0 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_5_0 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_6_0 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_7_0 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x2 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_IMEM_PORTS_INIT 0x1 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_DMEM_PORTS_INIT 0x4 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_TAG_WIDTH_INIT 0x10 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x1 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2 0x0041a0f4 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_SHA 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_SHA_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_SHA_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_BMEM 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_BMEM_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_BMEM_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_PKCBOOT_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_PKCBOOT_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_DBGMODE_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_DBGMODE_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_KMEM 4:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_KMEM_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_KMEM_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_VHR 7:7 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_VHR_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_VHR_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_HS 8:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_HS_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_HS_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_SECUREBUS_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_SECUREBUS_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_RISCV 10:10 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_RISCV_ENABLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_RISCV_DISABLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG3 0x0041a278 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CGCTL 0x0041a0a0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CGCTL_CG_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2 0x0041a134 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2__PRIV_LEVEL_MASK 0x0041a1e8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG 17:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_ENABLED 0x00000 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_DISABLED 0x1ffff /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG__PROD 0x000a0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FBIF_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG2_SLCG_FBIF_DISABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL 0x0041a240 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL__PRIV_LEVEL_MASK 0x0041a298 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_LSMODE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_LSMODE_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_LSMODE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_HSMODE 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_HSMODE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_HSMODE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_LSMODE_LEVEL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_UCODE_LEVEL 5:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_UCODE_LEVEL_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_AUTH_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL_AUTH_EN_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL1 0x0041a250 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL1__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL1_CSBLVL_MASK_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SCTL1_EXTLVL_MASK_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL 0x0041a0e4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL__PRIV_LEVEL_MASK 0x0041a0e8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_TRACEPC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_TRACEPC_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_SP_MIN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HSCTL_SP_MIN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_ERB 0x0041a2ec /* -W-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_ERB_DATA 31:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_ERB_DATA_CORRECTED_ERR 0xeafe0c00 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_ERB_DATA_UNCORRECTED_ERR 0xeafe1cff /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX 0x0041a2f0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_DATA 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRADDR 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRADDR_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE 31:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_PF 0xf0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_PF 0xf1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_SCP 0xf2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_SCP 0xf3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_SCP 0xf3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_DMA 0xf4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_DMA 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_DMA 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_PMB 0xf6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_PMB 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_PMB 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_LDST 0xf8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_PMB 0xf9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_DMA 0xfa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_SCP 0xfb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_CORRECTED_SHA 0xfc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_UNCORRECTED_SHA 0xfd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_CORRECTED_RISCV 0xfe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_UNCORRECTED_RISCV 0xff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IROM 0xe0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IROM 0xe1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL 0x0041a2f4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL__PRIV_LEVEL_MASK 0x0041a1b0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_FUSE_OPT_ECC_EN 16:16 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_FUSE_OPT_ECC_EN_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_IMEM_ECC_DIS 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_IMEM_ECC_DIS_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_CTRL_IMEM_ECC_DIS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_ERR_ADDR 0x0041a2f8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_ERR_ADDR_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_ERR_ADDR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_ERR_ADDR_HI 0x0041a2fc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_ERR_ADDR_HI_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SAFETY_ERR_ADDR_HI_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_OS 0x0041a080 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_OS_VERSION 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RM 0x0041a084 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RM_CONFIG 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SOFT_PM 0x0041a088 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SOFT_PM__PRIV_LEVEL_MASK 0x0041a1ec /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SOFT_PM_TRIGGER_START_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SOFT_PM_TRIGGER_END_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SOFT_PM_PROBE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SOFT_MODE 0x0041a08c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SOFT_MODE__PRIV_LEVEL_MASK 0x0041a1ec /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SOFT_MODE_PROBE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM 0x0041a0a8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM__PRIV_LEVEL_MASK 0x0041a1ec /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_CODE 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_IPND 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_SB 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL 19:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_RREQ 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_WREQ 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_RREQ_SC 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_WREQ_SC 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT_SC 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY_SC 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1 0x0041a090 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1__PRIV_LEVEL_MASK 0x0041a294 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x0040 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1_CTXSW_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUGINFO 0x0041a094 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN 0x0041a270 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN__PRIV_LEVEL_MASK 0x0041a1f0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SP_MIN_VALUE_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI 0x0041a0d0 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI__PRIV_LEVEL_MASK 0x0041a1f4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXPC 19:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_TRAP0 0x00 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_TRAP1 0x01 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_TRAP2 0x02 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_TRAP3 0x03 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_ILL_INS 0x08 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_INV_INS 0x09 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_MISS_INS 0x0a /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0b /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0d /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0f /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x10 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x11 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x12 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x13 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_FAULT_INS 0x14 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI2 0x0041a0bc /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI2__PRIV_LEVEL_MASK 0x0041a1f4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR 0x0041a0d4 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR__PRIV_LEVEL_MASK 0x0041a1f8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_SIGPASS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_SVEC_SPR_SIGPASS_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x0041a100 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL__PRIV_LEVEL_MASK 0x0041a288 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_IINVAL_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_IINVAL_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_SRESET_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_SRESET_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_HRESET_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_HRESET_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_HALTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_HALTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STOPPED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STOPPED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_ALIAS_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_ALIAS_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_ALIAS_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_ALIAS 0x0041a130 /* -W-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_STACKCFG 0x0041a138 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_STACKCFG__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_STACKCFG_BOTTOM_INIT 0x000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_STACKCFG_SPEXC_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_STACKCFG_SPEXC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_STACKCFG_SPEXC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC 0x0041a104 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC__PRIV_LEVEL_MASK 0x0041a194 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL 0x0041a254 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL__PRIV_LEVEL_MASK 0x0041a1a8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_VAL 9:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_VAL_INIT 0x000 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_TRACE_MODE_FULL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_TRACE_MODE_STACK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_CYA 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_CYA_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DBGCTL_CYA_ENABLE 0x8afe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1 0x0041a098 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1__PRIV_LEVEL_MASK 0x0041a1fc /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT1_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2 0x0041a09c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2__PRIV_LEVEL_MASK 0x0041a1fc /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT2_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3 0x0041a0b0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3__PRIV_LEVEL_MASK 0x0041a1fc /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT3_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4 0x0041a0b4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4__PRIV_LEVEL_MASK 0x0041a1fc /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT4_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5 0x0041a0b8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5__PRIV_LEVEL_MASK 0x0041a1fc /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_PC 23:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_PC_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_SKIP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_EN 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IBRKPT5_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD 0x0041a200 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD__PRIV_LEVEL_MASK 0x0041a220 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_STOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_RUN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_JRUN 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_RUNB 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_JRUNB 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_STEP 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_JSTEP 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_EMASK 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_RREG 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_WREG 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_RDM 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_WDM 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_RCM 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_WCM 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_RSTAT 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_OPC_SBU 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_SZ_B 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_SZ_HW 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_SZ_W 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_REG15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_IV0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_IV1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_EV 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_SP 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_PC 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_IMB 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_DMB 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_CSW 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_CCR 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_SEC 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_CTX 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_EXCI 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_SEC1 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_IMB1 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_DMB1 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_RSTAT0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_RSTAT1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_RSTAT2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_RSTAT3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_RSTAT4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_RSTAT5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_WB0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_WB1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_WB2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_IDX_WB3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_FAULTED 13:13 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_FAULTED_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_FAULTED_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_FAULTED_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_ERROR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_ERROR_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_RDVLD_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_RDVLD_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_PARM 31:16 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK 31:16 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_ADDR 0x0041a204 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_ADDR__PRIV_LEVEL_MASK 0x0041a220 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_WDATA 0x0041a208 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_WDATA__PRIV_LEVEL_MASK 0x0041a220 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA 0x0041a20c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA__PRIV_LEVEL_MASK 0x0041a220 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 0x2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 0x2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 0x2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 0x2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 0x2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 0x3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 0x4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 0x5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 0x6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 0x7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 0x2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 0x3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 0x2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0 0x0041a0d8 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0__PRIV_LEVEL_MASK 0x0041a224 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_VALID 28:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3 0x0041a0dc /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEIDX 0x0041a148 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEIDX__PRIV_LEVEL_MASK 0x0041a19c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEIDX_CNT_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEIDX_IDX_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEPC 0x0041a14c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEPC__PRIV_LEVEL_MASK 0x0041a19c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEPC_PC 23:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEINFO 0x0041a17c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEINFO__PRIV_LEVEL_MASK 0x0041a19c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL 0x0041a140 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_CMD 26:24 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_CMD_NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_CMD_IMINV 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_CMD_IMBLK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_CMD_IMTAG 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_DEBUG 0x0041a15c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_DEBUG_CMD_NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMSTAT 0x0041a144 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMSTAT__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMSTAT_VAL 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLRNG0 0x0041a150 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLRNG0_TAG_LO 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLRNG0_TAG_LO_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLRNG0_TAG_HI 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLRNG0_TAG_HI_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLRNG1 0x0041a154 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLRNG1_TAG_LO 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLRNG1_TAG_LO_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLRNG1_TAG_HI 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLRNG1_TAG_HI_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLCTL 0x0041a158 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLCTL__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMFILLCTL_NBLOCKS_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMCTL 0x0041a260 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMCTL__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMCTL_CMD 26:24 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMCTL_CMD_NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMCTL_CMD_DMINV 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMCTL_CMD_DMBLK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMCTL_CMD_DMTAG 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMCTL_CMD_DMCLEAN 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMCTL_CMD_DMLVL 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMSTAT 0x0041a264 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMSTAT__PRIV_LEVEL_MASK 0x0041a28c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMSTAT_VAL 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMVACTL 0x0041a268 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMVACTL__PRIV_LEVEL_MASK 0x0041a198 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMVACTL_BOUND_INIT 0x00000014 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERRSTAT 0x0041a244 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK 0x0041a22c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERRSTAT_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERRSTAT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERRSTAT_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERRSTAT_VALID_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERRSTAT_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERRSTAT_VALID_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_ADDR 0x0041a24c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK 0x0041a22c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_INFO 0x0041a248 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK 0x0041a22c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_DATA 0x0041a500 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_DATA_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_DATA_V_ELPG_LIST 0x00000001 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_DATA_V_GPCRG_LIST 0x00000002 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_DATA_A 0x0041a50c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_DATA_A_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH 0x0041a504 /* -W-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_PRIV 31:31 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR 11:0 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_NOP 0x000 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_WFI_SAVE 0x001 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_WFI_RESTORE 0x002 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_BIND_POINTER 0x003 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_BIND_POINTER_ONLY 0x060 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_HALT_PIPELINE 0x004 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_HALT_PIPELINE_NEW 0x007 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_UNHALT_PIPELINE 0x005 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_CONTEXT_RESET 0x006 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 0x010 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_PREPARE_FOR_INITIALIZATION 0x011 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_WFI_SAVE_ONLY 0x008 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 0x009 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_WFI_SAVE_RESTORE 0x00a /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_WFI 0x00b /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_NOCHSW_MODE 0x00c /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_ALLOW_SWDX_DIRECT_CTXSW_SKIP 0x00d /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_DISABLE_RAMCHAIN_SCRUB 0x00e /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_DISABLE_SWDX_DIRECT_CTXSW_SCRUB 0x00f /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_RESTORE_GOLDEN 0x015 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 0x016 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x025 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_DISCOVER_PREEMPTION_IMAGE_SIZE 0x01a /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_INIT_MME_SHADOW_RAM 0x02a /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_INIT_BUNDLE_DECODERS 0x02b /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_LO 0x02c /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_HI 0x02d /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SET_SMC_LTS_MASK_INDEX 0x02e /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_ASSIGN_SMC_LTS_MASK 0x02f /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x030 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x031 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x032 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SAVE_REGLIST 0x033 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_RESTORE_REGLIST 0x034 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_UCODE_RECONFIG 0x035 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_CHECK_GPCCS_INIT_COMPLETE 0x036 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_STOP_CTXSW 0x038 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_START_CTXSW 0x039 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_CONFIGURE_INTERRUPT_COMPLETION_OPTION 0x03a /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_DISABLE_ACCESS_COUNTER 0x03c /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_INSTANCE 0x03d /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_VIRTUAL_ADDRESS_LO 0x03e /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_VIRTUAL_ADDRESS_HI 0x03f /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_METHOD_INIT 0x040 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_BUNDLE_INIT_COMPUTE 0x041 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_BUNDLE_INIT_2D 0x042 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_BUNDLE_INIT_3D 0x043 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_BUNDLE_INIT_MEM2MEM 0x044 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_SIZE 0x054 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_LO 0x055 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_LO 0x056 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_CALCULATE 0x057 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_HI 0x058 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_HI 0x059 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_INJECT_STACK_CANARY_ERROR 0x070 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SHUTDOWN_UCODE 0x012 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_CONTEXT_ADDRESS 0x013 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_CONTEXT_ADDRESS_HI 0x01e /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_PRIV_OFFSET 0x014 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_GFXP_CONTEXT_ADDRESS 0x01c /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_GFXP_CONTEXT_ADDRESS_HI 0x01f /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_GFXP_RC_OFFSET 0x01d /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_ZCULL_CONTEXT_ADDRESS 0x017 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_ZCULL_CONTEXT_ADDRESS_HI 0x022 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_ZCULL_PRIV_OFFSET 0x018 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_ZCULL_MODE 0x019 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_CBC_CLEAR_ACTIVE 0x01b /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_FMODEL_TESTS 0x020 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x021 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SET_GFID 0x024 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_PM_CONTEXT_ADDRESS 0x026 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_PM_CONTEXT_ADDRESS_HI 0x023 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_PM_PRIV_OFFSET 0x027 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SEND_PM_MODE 0x028 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_TEST_MODE 0x029 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_CONTROL_ZBC_TABLES_SAVE 0x061 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SAVE_SM_PERF_COUNTERS_START 0x062 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SAVE_SM_PERF_COUNTERS_END 0x063 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_RESTORE_SM_PERF_COUNTERS 0x064 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SMPC_GLOBAL_MODE_START 0x069 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_SMPC_GLOBAL_MODE_STOP 0x06a /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_RESTORE_HWPM_CONTROL_REGS 0x065 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_PERFORM_PRE_SAVE_TASKS 0x06b /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_ADR_PERFORM_PRE_RESTORE_TASKS 0x06c /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A 0x0041a508 /* -W-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_PRIV 31:31 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR 11:0 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_NOP 0x000 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_WFI_SAVE 0x001 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_WFI_RESTORE 0x002 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_BIND_POINTER 0x003 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_BIND_POINTER_ONLY 0x060 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_HALT_PIPELINE 0x004 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_HALT_PIPELINE_NEW 0x007 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_UNHALT_PIPELINE 0x005 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_CONTEXT_RESET 0x006 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_IMAGE_SIZE 0x010 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_PREPARE_FOR_INITIALIZATION 0x011 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_WFI_SAVE_ONLY 0x008 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_WFI_GOLDEN_SAVE 0x009 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_WFI_SAVE_RESTORE 0x00a /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_WFI 0x00b /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_NOCHSW_MODE 0x00c /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_ALLOW_SWDX_DIRECT_CTXSW_SKIP 0x00d /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_DISABLE_RAMCHAIN_SCRUB 0x00e /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_DISABLE_SWDX_DIRECT_CTXSW_SCRUB 0x00f /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_RESTORE_GOLDEN 0x015 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_ZCULL_IMAGE_SIZE 0x016 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_PM_IMAGE_SIZE 0x025 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_PREEMPTION_IMAGE_SIZE 0x01a /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_INIT_MME_SHADOW_RAM 0x02a /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_INIT_BUNDLE_DECODERS 0x02b /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_LO 0x02c /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_HI 0x02d /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SET_SMC_LTS_MASK_INDEX 0x02e /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_ASSIGN_SMC_LTS_MASK 0x02f /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x030 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SET_REGLIST_BIND_INSTANCE 0x031 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x032 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SAVE_REGLIST 0x033 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_RESTORE_REGLIST 0x034 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_UCODE_RECONFIG 0x035 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_CHECK_GPCCS_INIT_COMPLETE 0x036 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_STOP_CTXSW 0x038 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_START_CTXSW 0x039 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_CONFIGURE_INTERRUPT_COMPLETION_OPTION 0x03a /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_DISABLE_ACCESS_COUNTER 0x03c /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_SIZE 0x054 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_LO 0x055 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_LO 0x056 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_CALCULATE 0x057 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_HI 0x058 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_HI 0x059 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_READ_PHYS_MEM 0x067 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_ENABLE_PHYS_MEM_READS 0x068 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SHUTDOWN_UCODE 0x012 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_CONTEXT_ADDRESS 0x013 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_CONTEXT_ADDRESS_HI 0x01e /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_PRIV_OFFSET 0x014 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_GFXP_CONTEXT_ADDRESS 0x01c /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_GFXP_CONTEXT_ADDRESS_HI 0x01f /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_GFXP_RC_OFFSET 0x01d /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_ZCULL_CONTEXT_ADDRESS 0x017 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_ZCULL_CONTEXT_ADDRESS_HI 0x022 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_ZCULL_PRIV_OFFSET 0x018 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_ZCULL_MODE 0x019 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_CBC_CLEAR_ACTIVE 0x01b /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_FMODEL_TESTS 0x020 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SET_WATCHDOG_TIMEOUT 0x021 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SET_GFID 0x024 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_PM_CONTEXT_ADDRESS 0x026 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_PM_CONTEXT_ADDRESS_HI 0x023 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_PM_PRIV_OFFSET 0x027 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SEND_PM_MODE 0x028 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_TEST_MODE 0x029 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_PCIE_TRAINING 0x050 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_CONTROL_ZBC_TABLES_SAVE 0x061 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SAVE_SM_PERF_COUNTERS_START 0x062 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_SAVE_SM_PERF_COUNTERS_END 0x063 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_RESTORE_SM_PERF_COUNTERS 0x064 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_RESTORE_HWPM_CONTROL_REGS 0x065 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_PERFORM_PRE_SAVE_TASKS 0x06b /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_PERFORM_PRE_RESTORE_TASKS 0x06c /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_METHOD_PUSH_A_ADR_INJECT_STACK_CANARY_ERROR 0x070 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_DATA 0x0041a8b8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_DATA_FIELD 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG 0x0041a8bc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_NONE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_ENGINE_RESET 0x01 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CONTEXT_RESET 0x02 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_INSTANCE_BIND 0x03 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_SAVE_ENGINE_REGS 0x06 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_RESTORE_ENGINE_REGS 0x07 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GOLDEN_SAVE 0x08 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_SAVE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_SAVE 0x10 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_SAVE 0x11 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_SAVE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_SAVE_ONLY 0x0a /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_SAVE_ONLY 0x05 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_SAVE_ONLY 0x12 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_SAVE_ONLY 0x13 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_RESTORE 0x0f /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_RESTORE 0x14 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_RESTORE 0x15 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_RESTORE 0x0b /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GOLDEN_RESTORE 0x0c /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_PATCH_BUFFER_END 0x0d /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_END 0x04 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FORCE_NONIDLE 0x0041a424 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FORCE_NONIDLE_OVERRIDE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FORCE_NONIDLE_OVERRIDE_ACTIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FORCE_NONIDLE_OVERRIDE_INACTIVE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_IDLESTATE 0x0041a420 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_IDLESTATE_FALCON 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_IDLESTATE_FORCED 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_IDLESTATE_RC_LANES 2:2 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_IDLESTATE_PRIV_SEQUENCER 3:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_IDLESTATE_GPCCS 15:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_GPC_0 0x0041ac04 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_GPC_0_HWW 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_GPC_0_CTXSW_HALT 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_GPC_0_STOP_SM 2:2 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1 0x0041a400 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_CONSTANT_0 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_LOCAL_PRIV_ERROR 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_RC_LANES 2:2 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_RC_LANES_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_RC_LANES_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_CONTEXT_RESET 3:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_CONTEXT_RESET_ACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_CONTEXT_RESET_DISABLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL 4:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL_BUSY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL_IDLE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_SEQUENCER 5:5 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_SEQUENCER_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_SEQUENCER_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_READ 6:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_READ_DONE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_READ_NOT_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_WRACK 7:7 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_WRACK_DONE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_WRACK_NOT_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_COMP0 8:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_COMP0_DONE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_COMP0_NOT_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_COMP1 9:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_COMP1_DONE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_COMP1_NOT_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_DFD_TRIGGER 10:10 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_DFD_TRIGGER_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_DFD_TRIGGER_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_WATCHDOG_TRIGGER 11:11 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_WATCHDOG_TRIGGER_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_WATCHDOG_TRIGGER_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_ARB_BUSY 12:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_ARB_NACK 13:13 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_ARB_HALTED 14:14 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_ARB_FLUSH_WHEN_BUSY 15:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_CTXSW_CHECKSUM_MISMATCH 16:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL 28:28 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL_VIOLATION 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_ERROR 29:29 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP 30:30 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_WRITE_DROPPED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_UCODE_TRAP 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_UCODE_TRAP_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_STATUS_1_PRIV_UCODE_TRAP_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG 0x0041a404 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SEL0_BIT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SEL0_BIT_V0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SEL0_STATUS_REG 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_1 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SEL1_BIT 12:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SEL1_BIT_V0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SEL1_STATUS_REG 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_1 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_COMBINATION 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_COMBINATION_OR 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_COMBINATION_AND 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SENSE 18:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SENSE_RISING_EDGE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SENSE_FALLING_EDGE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SENSE_LEVEL_1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_CFG_SENSE_LEVEL_0 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_WATCHDOG 0x0041a430 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_WATCHDOG_COUNT 29:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_WATCHDOG_COUNT_V 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_WATCHDOG_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_WATCHDOG_ENABLE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_WATCHDOG_ENABLE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK 0x0041a434 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_2_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_3_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_3_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_4 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_4_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_4_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_5_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_5_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_6_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_6_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_7_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_INT_ACK_7_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL 0x0041a614 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_GPC_HALT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_GPC_HALT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_GPC_HALT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_HALT_SEQUENCER 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_HALT_SEQUENCER_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_HALT_SEQUENCER_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_ZCULL_RT_RESET 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_ZCULL_RT_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_ZCULL_RT_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ENGINE_RESET_CTL 0x0041a610 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ENGINE_RESET_CTL_GPC_ENGINE_RESET 0:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ENGINE_RESET_CTL_GPC_ENGINE_RESET_ENABLED 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ENGINE_RESET_CTL_GPC_ENGINE_RESET_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_CTL_SIGS 0x0041a88c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_CTL_SIGS_CTXSW_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_CTL_SIGS_CTXSW_FREEZE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_CTL_SIGS_CTXSW_FREEZE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x0041a800+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX__SIZE_1 18 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_NONE 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_PASS 0x00000001 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_FAIL 0x00000002 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_BIND_POINTER_PASS 0x00000010 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_BIND_POINTER_FAIL 0x00000021 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_MAGIC 0x12345678 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_WAIT_FOR_MODS 0x0000000f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_STOP_WAIT_FOR_MODS 0x0000000e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SYNC_POINT_1 0x00000005 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SYNC_POINT_2 0x00000006 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SYNC_POINT_3 0x00000007 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_INIT_FAILED 0x00000008 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_INVALID_METHOD 0x00000009 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_METHOD_QUEUE_OVERFLOW 0x00000010 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_INVALID_FIRMWARE_METHOD_PARAMETER 0x00000011 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SIDEBAND_METHOD_QUEUE_OVERFLOW 0x00000012 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_FIRMWARE_METHOD_QUEUE_OVERFLOW 0x00000013 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_BECS_RC_NON_ZERO 0x00000014 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_BAD_CTXSW_IMAGE 0x00000015 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SECURE_FAIL_FECS 0x00000016 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SECURE_FAIL_GPCCS 0x00000017 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SECURE_FAIL_FECS_AND_GPCCS 0x00000018 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_GFXP_WITH_VPR_CONTEXT 0x00000019 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_PRI_SEQ_ERROR 0x00000020 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_CTXSW_CHECKSUM_MISMATCH 0x00000021 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_FALCON_CSB_ERROR 0x00000022 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_PATCH_BUFFER_ACCESS_VIOLATION 0x00000023 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_FALCON_STACK_CANARY_CHECK_FAILED 0x00000024 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SCRUB_STEP_CHECK_1_FAILED 0x00000025 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SCRUB_STEP_CHECK_2_FAILED 0x00000026 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_INDEX_OOB 0x00000027 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_POINTER_OVERFLOW 0x00000028 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_OFFSET_OVERFLOW 0x00000029 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_FULL 0x00000030 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_INVALID_ARBITER_COMMANDS 0x00000031 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_NUM_GPC_MISMATCH 0x00000032 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_NUM_TPC_MISMATCH 0x00000033 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_GFXP_IN_SMC_MODE 0x00000034 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_RESTORE_SMC_IN_LEGACY 0x00000035 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_RESTORE_LEGACY_IN_SMC 0x00000036 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SMC_LTS_MASK_INDEX_OUT_OF_BOUNDS 0x00000037 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SYS_RAMCHAIN_IMAGE_SIZE_MISMATCH 0x00000038 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_GPC_RAMCHAIN_IMAGE_SIZE_MISMATCH 0x00000039 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SYS_PRI_IMAGE_SIZE_MISMATCH 0x00000040 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_GPC_PRI_IMAGE_SIZE_MISMATCH 0x00000041 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_MAX_LTS_PER_LTC 0x00000042 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_NUM_PPC_MISMATCH 0x00000043 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_TRIVIAL_ACK_WITHOUT_NOCHSW 0x00000044 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_SECOND_RESTORE_WITH_NOCHSW 0x00000045 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_INVALID_PRIV_ACCESS_MAP_CONFIG 0x00000046 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_LTC_COUNT_OVERFLOW 0x00000047 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_REV_ID_CHECK_FAILED 0x00000048 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_CHIP_ID_CHECK_FAILED 0x00000049 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_ILLEGAL_FALCON_LEVEL 0x00000050 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_PRIV_SEC_NOT_ENABLED 0x00000051 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_FIRMWARE_MTHD_PRIV_ACCESS_VIOLATION 0x00000002 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_FIRMWARE_MTHD_VERIF_VIOLATION 0x00000003 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_OOB 0x00000001 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_NOT_IN_WHITELIST 0x00000002 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_ALLOW_NONE 0x00000003 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_KILL 0x00000004 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_OOB 0x00000005 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_NOT_IN_WHITELIST 0x00000006 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_SET(i) (0x0041a848+(i)*4) /* -W-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_SET__SIZE_1 6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_SET_VALUE 31:0 /* -W-VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR(i) (0x0041a860+(i)*4) /* -W-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR__SIZE_1 6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR_VALUE 31:0 /* -W-VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX(i) (0x0041a8c0+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX__SIZE_1 6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_VALUE 31:0 /* -W-VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK 0x0041a878 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_LEVEL3_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_LOCAL_FALCON_ENABLED 0x80040 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1(i) (0x0041a8d8+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1__PRIV_LEVEL_MASK 0x0041a878 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_VALUE 31:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK 0x0041a87c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_LEVEL3_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2(i) (0x0041a8e4+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2__PRIV_LEVEL_MASK 0x0041a87c /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_VALUE 31:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK 0x0041a8fc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3(i) (0x0041a8f0+(i)*4) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3__PRIV_LEVEL_MASK 0x0041a8fc /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_VALUE 31:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK 0x0041a428 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_SOURCE_FALCON_FECS_GPCCS_ENABLED 0x80174 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_FS_CONFIG 0x0041a40c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_FS_CONFIG__PRIV_LEVEL_MASK 0x0041a428 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_FS_CONFIG_EN 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_FS_CONFIG_EN_NONE 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_ACTIVE_CONFIG 0x0041a410 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_ACTIVE_CONFIG__PRIV_LEVEL_MASK 0x0041a428 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_ACTIVE_CONFIG_EN 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_ACTIVE_CONFIG_EN_NONE 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_FINISHED 0x0041a414 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_FINISHED__PRIV_LEVEL_MASK 0x0041a428 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_FINISHED_BITS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_FINISHED_BITS_RESET 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE(i) (0x0041a418+(i)*4) /* -W-4A */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE__PRIV_LEVEL_MASK 0x0041a428 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT0 0:0 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT0_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT0_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT1 1:1 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT1_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT1_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT2 2:2 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT2_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT2_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT3 3:3 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT3_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT3_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT4 4:4 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT4_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT4_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT5 5:5 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT5_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT5_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT6 6:6 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT6_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT6_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT7 7:7 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT7_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT7_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT8 8:8 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT8_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT8_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT9 9:9 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT9_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT9_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT10 10:10 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT10_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT10_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT11 11:11 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT11_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT11_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT12 12:12 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT12_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT12_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT13 13:13 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT13_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT13_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT14 14:14 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT14_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT14_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT15 15:15 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT15_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT15_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT16 16:16 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT16_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT16_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT17 17:17 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT17_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT17_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT18 18:18 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT18_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT18_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT19 19:19 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT19_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT19_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT20 20:20 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT20_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT20_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT21 21:21 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT21_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT21_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT22 22:22 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT22_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT22_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT23 23:23 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT23_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT23_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT24 24:24 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT24_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT24_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT25 25:25 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT25_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT25_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT26 26:26 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT26_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT26_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT27 27:27 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT27_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT27_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT28 28:28 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT28_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT28_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT29 29:29 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT29_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT29_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT30 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT30_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT30_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT31 31:31 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT31_SET 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_COMP_SET_DONE_BIT31_I 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FS 0x0041a604 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FS_NUM_AVAILABLE_GPCS 4:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FS_NUM_AVAILABLE_FBPS 20:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FS_NUM_AVAILABLE_LTCS 28:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FS_GPC 0x0041a608 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FS_GPC_NUM_AVAILABLE_ROPS 25:21 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_INFO 0x0041a618 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_INFO_GLOBAL_GPC_ID 4:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_INFO_SMC_LOCAL_GPC_ID 12:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_INFO_UGPU_ID 13:13 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_SMC_CONFIGURATION 0x0041a61c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_SMC_CONFIGURATION_MODE 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_SMC_CONFIGURATION_MODE_LEGACY_MODE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_SMC_CONFIGURATION_MODE_SMC_MODE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_SMC_CONFIGURATION_SMC_ENGINE_ID 20:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CFG_FALCON 0x0041a620 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CFG_FALCON_IMEM_SZ 7:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CFG_FALCON_IMEM_SZ_4K 0x10 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CFG_FALCON_IMEM_SZ_6K 0x18 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CFG_FALCON_IMEM_SZ_8K 0x20 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CFG_FALCON_IMEM_SZ_12K 0x30 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CFG_FALCON_DMEM_SZ 15:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CFG_FALCON_DMEM_SZ_2K 0x08 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CFG_FALCON_DMEM_SZ_4K 0x10 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CFG_FALCON_DMEM_SZ_8K 0x20 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS 0x0041acfc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC0_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC0_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC1_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC1_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC2_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC2_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC3_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC3_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC4 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC4_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC4_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC5_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC5_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC6_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC6_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC7_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_TPCCS_STATUS_TPC7_BUSY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANES 0x0041a880 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANES_NUM_CHAINS 5:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN 0x0041a884 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE0_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE0_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE1_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE1_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE2_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE2_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE3_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE3_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE4 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE4_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE4_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE5_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE5_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE6_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE6_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE7_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE7_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE8 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE8_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE8_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE9 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE9_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE9_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE10 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE10_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE10_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE11 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE11_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE11_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE12 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE12_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE12_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE13 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE13_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE13_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE14 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE14_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE14_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE15 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE15_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE15_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE16 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE16_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE16_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE17 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE17_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RUN_LANE17_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS 0x0041a888 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE0 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE0_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE0_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE1 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE1_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE1_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE2 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE2_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE2_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE3 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE3_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE3_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE4 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE4_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE4_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE5 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE5_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE5_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE6 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE6_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE6_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE7 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE7_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE7_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE8 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE8_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE8_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE9 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE9_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE9_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE10 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE10_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE10_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE11 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE11_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE11_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE12 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE12_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE12_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE13 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE13_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE13_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE14 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE14_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE14_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE15 15:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE15_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE15_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE16 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE16_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE16_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE17 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE17_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_STATUS_LANE17_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SCRUB 0x0041a640 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SCRUB_STATUS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SCRUB_STATUS_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SCRUB_STATUS_CLEAN 0xffffffff /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_SIMULATION_OPTIONS 0x0041a644 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_SIMULATION_OPTIONS_MODEL 1:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_SIMULATION_OPTIONS_MODEL_GATES 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_SIMULATION_OPTIONS_MODEL_RTL 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_SIMULATION_OPTIONS_MODEL_FMODEL 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS 0x0041a678 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_RESET 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_RESET_TASK 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_STATUS_RESET_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT 0x0041a67c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT 0x0041a680 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_ADDRESS 0x0041a684 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_ADDRESS_INDEX 22:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_ADDRESS_ROW_ADDRESS 19:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_ADDRESS_SOURCE_RAM 22:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_ADDRESS_SOURCE_RAM_FALCON_IMEM 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_ADDRESS_SOURCE_RAM_FALCON_DMEM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK 0x0041a688 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CONTROL 0x0041a68c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CONTROL__PRIV_LEVEL_MASK 0x0041a688 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR 0:0 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR 1:1 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_INFO 0x0041a690 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_INFO_ADDRESS 25:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_INFO_ADDRESS_V 0x0000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE 30:29 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE_INVALID 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE_READ 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE_WRITE_ACK 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE_WRITE_NO_ACK 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_INFO_SOURCE 31:31 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_INFO_SOURCE_PRI_SEQ 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_INFO_SOURCE_FALCON_CSB 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_CODE 0x0041a694 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_CODE_VALUE 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_CODE_VALUE_V 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_SUBID_INFO 0x0041a6a0 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_SUBID_INFO_TRANSACTION_SUBID 7:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_SUBID_INFO_TRANSACTION_SUBID_V 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_SUBID_INFO_RETURN_SUBID 15:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PRI_ERROR_SUBID_INFO_RETURN_SUBID_V 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK 0x0041a950 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_IFF_GPCCS_FECS_GSP_SEC2_FUSE1 0x8007c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CONTROL 0x0041a904 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CONTROL__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CONTROL_COMPRESSION 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CONTROL_COMPRESSION_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CONTROL_COMPRESSION_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CONTROL_BLOAT_BUDGET 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CONTROL_BLOAT_BUDGET_0 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CONTROL_COMPRESSION_SETTINGS 27:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CONTROL_COMPRESSION_SETTINGS__0 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SAVE_OFFSET 0x0041a908 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SAVE_OFFSET__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SAVE_OFFSET_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SAVE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RESTORE_OFFSET 0x0041a90c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RESTORE_OFFSET__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RESTORE_OFFSET_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RESTORE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CURRENT_OFFSET 0x0041a92c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CURRENT_OFFSET_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CURRENT_OFFSET_V_0 0x00000000 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CURRENT_SUBOFFSET 0x0041a930 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CURRENT_SUBOFFSET_V 5:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CURRENT_SUBOFFSET_V_0 0x00 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SIZE 0x0041a910 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SIZE__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SIZE_V 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SIZE_V_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_PREFETCH_OFFSET 0x0041a914 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_PREFETCH_OFFSET__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_PREFETCH_OFFSET_V 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_PREFETCH_OFFSET_V_10 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SAVED_WORDS 0x0041a934 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SAVED_WORDS__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SAVED_WORDS_V 23:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SAVED_WORDS_V_0 0x000000 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RESTORE_WORDS 0x0041a938 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RESTORE_WORDS__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RESTORE_WORDS_V 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_RESTORE_WORDS_V_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_DATA 0x0041a918 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_DATA__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_DATA_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_DATA_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_LOC 0x0041a91c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_LOC__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_LOC_RAMID 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_LOC_RAMID_V 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_LOC_OFFSET 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_LOC_OFFSET_V 0x000f /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_CFG 0x0041a920 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_CFG__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_CFG_DELAY 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_CFG_DELAY_V 0x41 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_CFG_CREDITS 21:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_CFG_CREDITS_V 0x3f /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_CFG_AUTOSEEK 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_CFG_AUTOSEEK_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_CFG_AUTOSEEK_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_RCCLASS 0x0041a93c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_RCCLASS__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_RCCLASS_V 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_RCCLASS_V_3 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_RCCLASS_V_WFI 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_RCCLASS_V_GFXP 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS 0x0041a924 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD 4:0 /* RW-VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_IDLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SEEK 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_DISCOVER_LENGTH 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SAVE 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RESTORE 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_LOAD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_READ_POP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_WRITE_PUSH 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_ENABLE 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_DISABLE 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_ENABLE 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_DISABLE 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_ENABLE 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_DISABLE 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_OVERRIDE 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_FLUSH 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SUSPEND 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_CURRENT 9:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_CURRENT_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_STATUS_CURRENT_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC 0x0041a928 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_IDLE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_SEEK 0x01 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_DISCOVER_LENGTH 0x02 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_SAVE 0x03 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_RESTORE 0x04 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_LOAD 0x05 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_READ_POP 0x06 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_WRITE_PUSH 0x07 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_RAMID_ENABLE 0x08 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_RAMID_DISABLE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_ENABLE 0x0a /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_DISABLE 0x0b /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_CHAIN_ENABLE 0x0c /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_CHAIN_DISABLE 0x0d /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_OVERRIDE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_FLUSH 0x0f /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_SUSPEND 0x10 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CMD_EXEC_CMD_SCRUB 0x11 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_COMPUTED_CHECKSUM 0x0041a944 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_COMPUTED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SAVED_CHECKSUM 0x0041a948 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SAVED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CHECKSUM 0x0041a94c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CHECKSUM__PRIV_LEVEL_MASK 0x0041a950 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CHECKSUM_CTRL_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CHECKSUM_CTRL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CHECKSUM_STATUS_MATCH 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_RC_LANE_CHECKSUM_STATUS_MISMATCH 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK 0x0041a760 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pri_sequencer_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_pri_sequencer_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_JTAG_IFF_SEC2_ENABLED_FUSE1 0x80144 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_SAVE_OFFSET 0x0041a700 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_SAVE_OFFSET__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_SAVE_OFFSET_V 31:0 /* RW-VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_SAVE_OFFSET_V_0 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_RESTORE_OFFSET 0x0041a704 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_RESTORE_OFFSET__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_RESTORE_OFFSET_V 31:0 /* RW-VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_RESTORE_OFFSET_V_0 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_SAVE_COUNT 0x0041a748 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_SAVE_COUNT_V 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_SAVE_COUNT_V_0 0x0000 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_RESTORE_COUNT 0x0041a74c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_RESTORE_COUNT__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_RESTORE_COUNT_V 15:0 /* RW-VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_RESTORE_COUNT_V_0 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_CURRENT_OFFSET 0x0041a708 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_CURRENT_OFFSET_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_CURRENT_SUBOFFSET 0x0041a70c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_CURRENT_SUBOFFSET_V 5:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_REGISTER_BASE_ADDR 0x0041a710 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_REGISTER_BASE_ADDR__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_REGISTER_BASE_ADDR_V 25:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_REGISTER_BASE_ADDR_V_0 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_REGISTER_BASE_ADDR 0x0041a724 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_REGISTER_BASE_ADDR__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_REGISTER_BASE_ADDR_V 25:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_REGISTER_BASE_ADDR_V_0 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_ST_CONSTANT 0x0041a744 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_ST_CONSTANT__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_ST_CONSTANT_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_ST_CONSTANT_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE 0x0041a714 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_FIFO_FREE_ENTRIES 4:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_FIFO_FREE_ENTRIES_IV 0x10 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_FIFO_TOTAL_ENTRIES 12:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_FIFO_TOTAL_ENTRIES_IV 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_DIRECTION 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_DIRECTION_SAVE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_DIRECTION_RESTORE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_START 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_START_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_START_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_FINISH 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_FINISH_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_FINISH_T 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_NO_ADDR_INC 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_NO_ADDR_INC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_NO_ADDR_INC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_PRIV_LEVEL 29:28 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_PRIV_LEVEL_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_LOWER_PRIV_LEVEL 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_LOWER_PRIV_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_MODE_LOWER_PRIV_LEVEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PREFETCH_CTL 0x0041a740 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PREFETCH_CTL__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PREFETCH_CTL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PREFETCH_CTL_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PREFETCH_CTL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PREFETCH_CTL_OFFSET 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_PREFETCH_CTL_OFFSET_10 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_INDEX_INCREMENT 0x0041a718 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_INDEX_INCREMENT__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_INDEX_INCREMENT_V 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_INDEX_INCREMENT_V_0 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_INDEX_MASK 0x0041a71c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_INDEX_MASK__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_INDEX_MASK_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_INDEX_MASK_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH 0x0041a720 /* -W-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_USE_BASE_ADDR 0:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_USE_INDEXER 1:1 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_ADDR 25:2 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_REGISTER_COUNT 30:26 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_SPECIAL 31:31 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_SPECIAL_DATA 25:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_SPECIAL_COUNT 11:0 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD 30:26 /* -WXVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_NOP 0x00 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_WAIT 0x01 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_STORE_CONSTANT 0x02 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_SKIP_DATA 0x03 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_SET_REG_COUNT 0x04 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ 0x0041a728 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_USE_BASE_ADDR_NOT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_ADDR 25:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_ADDR_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_LOWER_PRIV_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_LOWER_PRIV_LEVEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_TRANS_STATUS 28:27 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_TRANS_STATUS_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_TRANS_STATUS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_TRANS_STATUS_DONE 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_TRANS_TYPE 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_TRANS_TYPE_READ 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_TRANS_TYPE_UNDEF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_TRANS_TYPE_WRITE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_TRANS_TYPE_WRITE_ACK 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_CMD 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_CMD_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_CMD_GO 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A 0x0041a734 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_USE_BASE_ADDR_NOT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_ADDR 25:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_ADDR_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_TRANS_STATUS 28:27 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_TRANS_STATUS_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_TRANS_STATUS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_TRANS_STATUS_DONE 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE_READ 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE_UNDEF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE_WRITE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE_WRITE_ACK 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_CMD 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_CMD_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_A_CMD_GO 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B 0x0041a738 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_USE_BASE_ADDR_NOT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_ADDR 25:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_ADDR_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_TRANS_STATUS 28:27 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_TRANS_STATUS_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_TRANS_STATUS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_TRANS_STATUS_DONE 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE_READ 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE_UNDEF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE_WRITE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE_WRITE_ACK 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_CMD 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_CMD_NONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_B_CMD_GO 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_READ_DATA 0x0041a72c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_READ_DATA_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_READ_DATA_A 0x0041a754 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_READ_DATA_A_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_READ_DATA_B 0x0041a758 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_READ_DATA_B_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_WRITE_DATA 0x0041a730 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_WRITE_DATA__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_WRITE_DATA_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_WRITE_DATA_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_WRITE_DATA_A 0x0041a73c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_WRITE_DATA_A__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_WRITE_DATA_A_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_WRITE_DATA_A_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_WRITE_DATA_B 0x0041a750 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_WRITE_DATA_B__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_WRITE_DATA_B_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_WRITE_DATA_B_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_STATUS 0x0041a764 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_STATUS_PRIV_LEVEL 1:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_STATUS_PRIV_LEVEL_A 5:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PV_PRIV_REQ_STATUS_PRIV_LEVEL_B 9:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_COMPUTED_CHECKSUM 0x0041a774 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_COMPUTED_CHECKSUM__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_COMPUTED_CHECKSUM_RESULTS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_SAVED_CHECKSUM 0x0041a778 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_SAVED_CHECKSUM__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_SAVED_CHECKSUM_RESULTS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_CHECKSUM 0x0041a77c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_CHECKSUM__PRIV_LEVEL_MASK 0x0041a760 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_CHECKSUM_CTRL_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_CHECKSUM_CTRL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_CHECKSUM_STATUS_MATCH 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PVS_CHECKSUM_STATUS_MISMATCH 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_LANE_CTL 0x0041aa00 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES_V 0x8 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_LANE_CTL_WRR_WEIGHT 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_LANE_CTL_WRR_WEIGHT_V 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_BASE_ADDR 0x0041aa04 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_BASE_ADDR_F 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_BASE_ADDR_F_V 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_HI_BASE_ADDR 0x0041aa38 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_HI_BASE_ADDR_F 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_HI_BASE_ADDR_F_V 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_ENGINE_CTL 0x0041aa3c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_ENGINE_CTL_ENGINE_ID 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_ENGINE_CTL_ENGINE_ID_VEID0 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_ENGINE_CTL_ENGINE_ID_BAR2_FN0 0xc0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_ENGINE_CTL_VEID 21:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_ENGINE_CTL_VEID_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_ENGINE_CTL_GFID 29:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_ENGINE_CTL_GFID_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_PREFETCH_CTL 0x0041aa08 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_PREFETCH_CTL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_PREFETCH_CTL_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_PREFETCH_CTL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_PREFETCH_CTL_OFFSET 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_PREFETCH_CTL_OFFSET_V 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK 0x0041aa28 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD 0x0041aa10 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD__PRIV_LEVEL_MASK 0x0041aa28 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_IDLE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_FB_OP_FLUSH 0x05 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_FB_OP_SOFT_FLUSH 0x06 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_FB_OP_BIND_INST_BLK_PTR 0x07 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_FB_OP_MMU_TLB_INVALIDATE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_PREFETCH 0x0a /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_FB_OP_PHYSICAL_L2_CACHE_MGMT 0x0b /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_CACHE_MGMT 0x0c /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_FB_OP_L2_PEER_INVALIDATE 0x0d /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_FB_OP_L2_SYSMEM_INVALIDATE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_CLEAN_COMPTAGS 0x0f /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_FLUSH_DIRTY 0x10 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_CMD_MEMBAR 0x01 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_SUB_OP 8:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_SUB_OP_INVALIDATE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_SUB_OP_CLEAN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_SUB_OP_DEMOTE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_ACK 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_ACK_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_ACK_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_ACK_TLB 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_ACK_MEM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_ACK_NONE_REQUIRED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_ACK_GLOBALLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_ACK_INTRANODE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_HALT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_HALT_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_HALT_REQUEST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_UNHALT 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_UNHALT_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CTX_CMD_UNHALT_REQUEST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_L2_EVICTION_CTL 0x0041aa14 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_L2_EVICTION_CTL_WR 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_L2_EVICTION_CTL_WR_FIRST 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_L2_EVICTION_CTL_WR_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_L2_EVICTION_CTL_WR_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_L2_EVICTION_CTL_RD 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_L2_EVICTION_CTL_RD_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_L2_EVICTION_CTL_RD_NORMAL 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_L2_EVICTION_CTL_RD_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_PRIV 0x0041aa18 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_PRIV_OVERRIDE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_PRIV_OVERRIDE_PRIV 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_PRIV_OVERRIDE_NONPRIV 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS 0x0041aa1c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_CLEAR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_CLEAR_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_CLEAR_CLEAR 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_ACK 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_ACK_OK 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_ACK_NACK 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_SUBID 15:2 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_OUTSTANDING_TRANSACTIONS 23:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_BUFFER_NOT_EMPTY 24:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_FLUSH_WHEN_BUSY 28:28 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_FLUSH_WHEN_BUSY_DEFAULT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_FLUSH_WHEN_BUSY_ERROR 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_HALTED 30:30 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_STATUS_BUSY 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CMD_OVERRIDE 0x0041aa20 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CMD_OVERRIDE_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CMD_OVERRIDE_CMD_VIRTUAL 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_VID_MEM 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_NONCOHERENT 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_COHERENT 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CMD_OVERRIDE_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CMD_OVERRIDE_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_CMD_OVERRIDE_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR 0x0041aa2c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR__PRIV_LEVEL_MASK 0x0041aa28 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_RC_ID 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_RC_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_RC_SECURE_LEVEL 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_RC_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PVS_ID 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PVS_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PVS_SECURE_LEVEL 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_PVS_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_CMD_ID 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_CMD_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_CMD_SECURE_LEVEL 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_CMD_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_BLOCKED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_ALLOWED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK 0x0041aa30 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG 0x0041aa34 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG__PRIV_LEVEL_MASK 0x0041aa30 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T0 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T1 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T2 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T3 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T4 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T5 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T6 27:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T7 31:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_ARB_FALCON_REGIONCFG_T7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON 0x0041a8a0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_FB_CMD 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_FB_CMD2 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_FB_CMD3 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_FB_DATA 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_MISC_0 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_MISC_1 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_0 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_1 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_2 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_3 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_4 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_5 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_6 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_7 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_8 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_9 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_10 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_11 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_12 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_13 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_14 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_15 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_17 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_18 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_RC_0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_RC_1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_RC_2 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_RC_3 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_RC_4 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_RC_5 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_RC_6 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_RC_7 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_RC_8 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_RC_9 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_RC_10 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_0 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_1 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_2 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_3 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_4 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_5 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_6 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_7 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_9 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_10 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PROBE_0 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PROBE_1 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_ARB_0 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_ARB_1 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_ERR 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_MISC_2 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_MISC_3 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_MISC_4 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_MISC_5 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_MISC_6 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_19 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_20 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_21 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_22 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_23 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_24 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_25 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_26 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_27 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_28 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_29 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_30 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_31 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_32 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_33 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_34 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_35 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_PRI_36 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATIC_PATTERN_55_8_GROUP 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATIC_PATTERN_AA_8_GROUP 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_11 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_12 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_13 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_14 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_STATUS_15 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_CTXSW_0 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_SEL_ECC_ERR 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_CTRL_ENABLE 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_CTRL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM 0x0041a8a8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_PROBE 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_PROBE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT0 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT1 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT2 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT3 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT4 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT5 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT6 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT7 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_SET 23:16 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_SET_INIT 0x00 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_SET_BIT0 0x01 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_SET_BIT1 0x02 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_SET_BIT2 0x04 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_SET_BIT3 0x08 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_SET_BIT4 0x10 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_SET_BIT5 0x20 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_SET_BIT6 0x40 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_SET_BIT7 0x80 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_CLEAR 31:24 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_CLEAR_INIT 0x00 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_CLEAR_BIT0 0x01 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_CLEAR_BIT1 0x02 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_CLEAR_BIT2 0x04 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_CLEAR_BIT3 0x08 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_CLEAR_BIT4 0x10 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_CLEAR_BIT5 0x20 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_CLEAR_BIT6 0x40 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM_CLEAR_BIT7 0x80 /* -W--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_MODE 0x0041a8a4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_MODE_PROBE 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_MODE_PROBE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x0041ac80 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_SETUP 2:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_SETUP_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_SETUP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_SETUP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_SETUP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_SETUP_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_SETUP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_SETUP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_SETUP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_CRSTR 5:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_CRSTR_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_CRSTR_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_CRSTR_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_CRSTR_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_CRSTR_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_CRSTR_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_CRSTR_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_CRSTR_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_ZCULL 8:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_ZCULL_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_ZCULL_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_ZCULL_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_ZCULL_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_ZCULL_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_ZCULL_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_ZCULL_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_ZCULL_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_WIDCLIP 11:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_WIDCLIP_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_WIDCLIP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_WIDCLIP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_WIDCLIP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_WIDCLIP_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_WIDCLIP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_WIDCLIP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_WIDCLIP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_FRSTR 14:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_FRSTR_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_FRSTR_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_FRSTR_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_FRSTR_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_FRSTR_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_FRSTR_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_FRSTR_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_FRSTR_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_TC 17:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_TC_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_TC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_TC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_TC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_TC_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_TC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_TC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_TC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_RASTERARB 20:18 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_RASTERARB_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_RASTERARB_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_RASTERARB_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_RASTERARB_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_RASTERARB_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_RASTERARB_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_RASTERARB_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_RASTERARB_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_PROP 23:21 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_PROP_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_PROP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_PROP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_PROP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_PROP_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_PROP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_PROP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_PROP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_GPCCS 26:24 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_GPCCS_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_GPCCS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_GPCCS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_GPCCS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_GPCCS_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_GPCCS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_GPCCS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0_GPCCS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x0041ac84 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMPD 2:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMPD_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMPD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMPD_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMPD_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMPD_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMPD_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMPD_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMPD_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMSD 5:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMSD_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMSD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMSD_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMSD_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMSD_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMSD_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMSD_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMSD_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMREPORT 8:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMREPORT_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMREPORT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMREPORT_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMREPORT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMREPORT_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMREPORT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMREPORT_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPMREPORT_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_SWDX 11:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_SWDX_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_SWDX_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_SWDX_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_SWDX_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_SWDX_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_SWDX_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_SWDX_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_SWDX_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_WDXPS 14:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_WDXPS_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_WDXPS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_WDXPS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_WDXPS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_WDXPS_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_WDXPS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_WDXPS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_WDXPS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GCC 17:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GCC_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GCC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GCC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GCC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GCC_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GCC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GCC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GCC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPCMMU0 20:18 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPCMMU0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPCMMU0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPCMMU0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPCMMU0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPCMMU0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPCMMU0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPCMMU0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GPCMMU0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GNIC 23:21 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GNIC_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GNIC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GNIC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GNIC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GNIC_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GNIC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GNIC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1_GNIC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x0041ac88 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES0 2:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES1 5:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES2 8:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES2_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES2_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES2_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES2_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES2_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES2_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES2_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_PES2_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR0 11:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR1 14:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR2 17:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR2_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR2_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR2_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR2_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR2_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR2_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR2_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_CBMGR2_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX0 20:18 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX1 23:21 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX2 26:24 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX2_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX2_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX2_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX2_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX2_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX2_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX2_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2_WWDX2_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x0041ac8c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC0 2:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC1 5:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC2 8:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC2_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC2_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC2_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC2_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC2_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC2_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC2_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC2_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC3 11:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC3_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC3_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC3_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC3_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC3_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC3_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC3_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC3_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC4 14:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC4_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC4_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC4_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC4_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC4_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC4_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC4_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC4_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC5 17:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC5_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC5_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC5_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC5_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC5_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC5_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC5_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3_TPC5_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4 0x0041ac9c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP0 2:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP1 5:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_CROP1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP0 8:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP1 11:9 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_ZROP1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH0 14:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH0_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH0_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH0_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH1 17:15 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH1_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH1_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY4_RRH1_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION 0x0041ac90 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_PROP 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_PROP_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_PROP_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_ZCULL 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_ZCULL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_ZCULL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_GCC 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_GCC_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_GCC_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_SETUP 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_SETUP_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_SETUP_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_PES0 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_PES0_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_PES0_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_PES1 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_PES1_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_PES1_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_PES2 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_PES2_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_PES2_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_GPCMMU0 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_GPCMMU0_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_GPCMMU0_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_GPCCS 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_GPCCS_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_GPCCS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_TPC 23:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_TPC_NOT_PENDING 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_TPC_0_NOT_PENDING 0x00 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_TPC_0_PENDING 0x01 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_CROP0 26:26 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_CROP0_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_CROP0_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_ZROP0 27:27 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_ZROP0_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_ZROP0_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_RRH0 28:28 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_RRH0_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_RRH0_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_CROP1 29:29 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_CROP1_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_CROP1_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_ZROP1 30:30 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_ZROP1_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_ZROP1_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_RRH1 31:31 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_RRH1_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_RRH1_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x0041ac94 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_PROP 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_PROP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_PROP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_ZCULL 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_ZCULL_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_ZCULL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_GCC 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_GCC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_GCC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_SETUP 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_SETUP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_SETUP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_PES0 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_PES0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_PES0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_PES1 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_PES1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_PES1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_PES2 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_PES2_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_PES2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_GPCMMU0 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_GPCMMU0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_GPCMMU0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_GPCCS 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_GPCCS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_GPCCS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC_DISABLED 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC_0_DISABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC_0_ENABLED 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_CROP0 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_CROP0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_CROP0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_ZROP0 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_ZROP0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_ZROP0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_RRH0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_RRH0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_RRH0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_CROP1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_CROP1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_CROP1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_ZROP1 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_ZROP1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_ZROP1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_RRH1 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_RRH1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_RRH1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_HWW_ESR 0x0041ac98 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_HWW_ESR_ECC_CORRECTED 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_HWW_ESR_ECC_CORRECTED_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_HWW_ESR_ECC_CORRECTED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_HWW_ESR_ECC_UNCORRECTED 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_HWW_ESR_ECC_UNCORRECTED_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_HWW_ESR_ECC_UNCORRECTED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_DEBUG 0x0041a698 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_DEBUG_STATUS_FILTER 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_DEBUG_STATUS_FILTER_INIT 0x16 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_DEBUG_STATUS_FILTER_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_DEBUG_STATUS_FILTER_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_STOP_SM 0x0041a69c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_STOP_SM_BIT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_STOP_SM_BIT_CLR 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_STOP_SM_BIT_SET 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG 0x0041a890 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_IDLE_CG_DLY_CNT__PROD 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG1 0x0041a894 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG1_SLCG 15:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG1_SLCG_DISABLED 0x7fff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG 0x0041a8b0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_IDLE_CG_DLY_CNT__PROD 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG1 0x0041a8b4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX 0x004188c0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_ADDRESS 15:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT 20:16 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_ZNEAR0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_ZNEAR1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_ZNEAR2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_ZNEAR3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_ZFAR0 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_ZFAR1 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_ZFAR2 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_ZFAR3 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_ZFAR4 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_ZFAR5 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_ZFAR6 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_ZFAR7 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_STENCIL0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_STENCIL1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_STENCIL2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_STENCIL3 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_STENCIL4 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_STENCIL5 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_STENCIL6 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_SELECT_STENCIL7 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_WRITE 31:31 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_WRITE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_INDEX_WRITE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_DATA 0x004188c4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_DATA_VALUE 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL 0x004188c8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRPA 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRPB 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP_AGG2_OCCLUDERS 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP_AGG2_PARTIAL_FLUSH 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP_ZSLVR 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_GRP_4X2_COUNT 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_STATIC_PATTERN_15_6_GROUP 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_STATIC_PATTERN_2A_6_GROUP 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_PERF_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0 0x004188cc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT1 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT1_COARSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT1_ZCULLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT1_SCULLED 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT1_ZACCEPT 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT1_ZREJECT 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT1_DBCULLED 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT1_FCULLED 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT1_CULLED 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT1_ZFAIL_NO_CULL 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT2 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT2_ZCULL_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT2_SCULL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT2_DBCULL_ENABLE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT2_ZACCEPT_ENABLE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT2_ZSAMPLED_OUTSIDE_PRIM 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT2_8X8_INSIDE 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT2_REGION_VALID 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT3 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT3_PIPE0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT3_PIPE1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT3_PIPE2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT3_PIPE3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0_PM_SELECT3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1 0x004188d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_RESULT_NF_PASS 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_RESULT_NF_PASS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_RESULT_NF_PASS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_RESULT_DB_PASS 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_RESULT_DB_PASS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_RESULT_DB_PASS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISCARD_THRESH_SEVEN_EIGHTS 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISCARD_THRESH_SEVEN_EIGHTS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISCARD_THRESH_SEVEN_EIGHTS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_RESULT_ZFAIL 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_RESULT_ZFAIL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_RESULT_ZFAIL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_RESULT_ZPASS 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_RESULT_ZPASS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_RESULT_ZPASS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_NO_CULL 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_NO_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_NO_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_Z_CULL 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_Z_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_Z_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_S_CULL 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_S_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_S_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_DB_CULL 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_DB_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_DB_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_NF_CULL 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_NF_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_NF_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_ZNEAR_CACHE 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_ZNEAR_CACHE_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_ZNEAR_CACHE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_ZNEAR_MERGE 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_ZNEAR_MERGE_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_ZNEAR_MERGE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISCARD_THRESH_ONE_QUARTER 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISCARD_THRESH_ONE_QUARTER_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISCARD_THRESH_ONE_QUARTER_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISCARD_THRESH_THREE_QUARTER 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISCARD_THRESH_THREE_QUARTER_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISCARD_THRESH_THREE_QUARTER_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_READ_CACHE 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_READ_CACHE_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_READ_CACHE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_FORCE_Z_PER_PRIM 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_FORCE_Z_PER_PRIM_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_FORCE_Z_PER_PRIM_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_STICKY_SCULL 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_STICKY_SCULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_STICKY_SCULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_STENCIL_SUBSETS 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_STENCIL_SUBSETS_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_STENCIL_SUBSETS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_OCCLUSION_QUERY_ACCEL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_OCCLUSION_QUERY_ACCEL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_OCCLUSION_QUERY_ACCEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_CULL_TO_NEAR_SIDE 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_CULL_TO_NEAR_SIDE_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_CULL_TO_NEAR_SIDE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_PER_PRIM_CLAMP 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_PER_PRIM_CLAMP_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_PER_PRIM_CLAMP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_ALWAYS_SYNCED 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_ALWAYS_SYNCED_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_ALWAYS_SYNCED_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_ZPASS_COUNT_AT_256 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_ZPASS_COUNT_AT_256_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_ZPASS_COUNT_AT_256_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_NF_CULL_IF_Z_CULL 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_NF_CULL_IF_Z_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_NF_CULL_IF_Z_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_NO_PACKET_KILL 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_NO_PACKET_KILL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_NO_PACKET_KILL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_NON_BLOCKING_BLOCK 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_NON_BLOCKING_BLOCK_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_NON_BLOCKING_BLOCK_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_Z_PER_SLIVER 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_Z_PER_SLIVER_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_Z_PER_SLIVER_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_REVERSED_ZFUNC_CULL 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_REVERSED_ZFUNC_CULL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_REVERSED_ZFUNC_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_OCCL_OVERLAP 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_OCCL_OVERLAP_0 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_DISABLE_OCCL_OVERLAP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_INVALIDATE_UPON_WRONG_DIR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_INVALIDATE_UPON_WRONG_DIR_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_1_INVALIDATE_UPON_WRONG_DIR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2 0x004188d4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_ZNEAR_NON_MONO 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_ZNEAR_NON_MONO_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_ZNEAR_NON_MONO_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_SAVE_RESTORE_WITH_NO_ALLOCATION_PERMISSION 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_SAVE_RESTORE_WITH_NO_ALLOCATION_PERMISSION_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_SAVE_RESTORE_WITH_NO_ALLOCATION_PERMISSION_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_FORCE_Z_PER_TILE_SHADER_Z 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_FORCE_Z_PER_TILE_SHADER_Z_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_GEN_ROP_STATE_BUNDLE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_GEN_ROP_STATE_BUNDLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_GEN_SYNC_BUNDLE 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_GEN_SYNC_BUNDLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_ZFAIL_NEARER 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_ZFAIL_NEARER_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_CONSERVATIVE_Z_CLAMP 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_DISABLE_CONSERVATIVE_Z_CLAMP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_MORE_CONSERVATIVE_Z_PER_SLIVER 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_MORE_CONSERVATIVE_Z_PER_SLIVER_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_LANA_CLOCKGATE_CONTROL 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_LANA_CLOCKGATE_CONTROL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_LANA_CLOCKGATE_CONTROL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_LANA_CLOCKGATE_CONTROL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_UPDATE_WRITE_WITHOUT_READ 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_UPDATE_WRITE_WITHOUT_READ_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_UPDATE_WRITE_WITHOUT_READ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_UPDATE_WRITE_WITHOUT_READ_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_17 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_17_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_18 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_18_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_19 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_19_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_20 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_20_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_21 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_21_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_22 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_22_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_23 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_23_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_24 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_24_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_25 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_25_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_26 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_26_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_27 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_27_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_28 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_28_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_29 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_29_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_30 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_30_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_31 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_2_SPARE_31_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX1 0x004188d8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX1_PRI_ZCULL_PROC_CUR_STATE 2:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX1_PRI_ZCULL_PROC_CUR_STATE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX1_PRI_ZCULL_BETWEEN_PRIMITIVES 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX1_PRI_ZCULL_BETWEEN_PRIMITIVES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX1_PRI_ZCULL_NON_BLOCKING_STATE 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX1_PRI_ZCULL_NON_BLOCKING_STATE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX1_PRI_ZCULL_STENCIL_WRITTEN 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX1_PRI_ZCULL_STENCIL_WRITTEN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX1_PRI_ZCULL_PROC_SYNC_COUNT 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX1_PRI_ZCULL_PROC_SYNC_COUNT_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX5 0x004188e0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX5_PRI_ZCULL_UPDATE_SYNC_COUNT 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX5_PRI_ZCULL_UPDATE_SYNC_COUNT_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX5_PRI_ZCULL_SYNC_SINCE_LAST_TILE 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX5_PRI_ZCULL_SYNC_SINCE_LAST_TILE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX6 0x004188e8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX6_PRI_ZCULL_ZPASS_PIXEL_COUNT 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX6_PRI_ZCULL_ZPASS_PIXEL_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX7 0x004188ec /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX7_PRI_ZCULL_TOTAL_8X8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX7_PRI_ZCULL_TOTAL_8X8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX8 0x004188f0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX8_PRI_ZCULL_ZFAIL_4X2 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX8_PRI_ZCULL_ZFAIL_4X2_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX9 0x004188f4 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX9_PRI_ZCULL_ZPASS_8X8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX9_PRI_ZCULL_ZPASS_8X8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX10 0x004188f8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX10_PRI_ZCULL_STNCL_4X4 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX10_PRI_ZCULL_STNCL_4X4_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG 0x004188fc /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_ZPASS_CULL_AFTER_FULLY_COVERED 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_ZPASS_CULL_AFTER_FULLY_COVERED_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_ZPASS_CULL_AFTER_PARTIALLY_COVERED 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_ZPASS_CULL_AFTER_PARTIALLY_COVERED_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_ZFAIL_REPORT_NOT_EQUAL_TOTAL_COARSE_TILES 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_ZFAIL_REPORT_NOT_EQUAL_TOTAL_COARSE_TILES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_ZF32_AS_Z16 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_ZF32_AS_Z16_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_PROC_TO_UPDATE_OCCLUDERS_ENABLE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_PROC_TO_UPDATE_OCCLUDERS_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_TWO_Z_1XAA_UPDATES_DISABLE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_TWO_Z_1XAA_UPDATES_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_BLKACTIVITY_DISABLE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_GFXP_DISABLE 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_GFXP_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_SPARE_12 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_SPARE_12_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_SPARE_13 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_SPARE_13_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_SPARE_14 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_SPARE_14_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_SPARE_15 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_SPARE_15_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_OCCL_OVERLAP_THRESHOLD 20:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_OCCL_OVERLAP_THRESHOLD_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_IGNORE_INSUFF_BANKS_RAMFORMAT 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_IGNORE_INSUFF_BANKS_RAMFORMAT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_USE_Z_OUTSIDE_PRIM 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_USE_Z_OUTSIDE_PRIM_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_Z_OUTSIDE_PRIM_OFFSET 29:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CTX_DEBUG_Z_OUTSIDE_PRIM_OFFSET_INIT 0x8 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR 0x00418900 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_SAVE_RESTORE_ADDR_OOB 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_SAVE_RESTORE_ADDR_OOB_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_SAVE_RESTORE_ADDR_OOB_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_RESET_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_INFO_0 0x00418904 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_INFO_0_ADDRESS_LOW 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_INFO_1 0x00418908 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_INFO_1_ADDRESS_HIGH 7:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_INFO_1_LIMIT_ADDRESS_HIGH 15:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_INFO_2 0x0041890c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HWW_ESR_INFO_2_LIMIT_ADDRESS_LOW 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_FS 0x00418910 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_FS_NUM_SMS 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_FS_NUM_SMS_INIT 0x001 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_FS_NUM_ACTIVE_BANKS_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_FS_NUM_BANKS 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_RAM_ADDR 0x00418914 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_RAM_ADDR_ROW_OFFSET_INIT 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_NUM_RCP 0x00418918 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_NUM_RCP_CONSERVATIVE_INIT 0x800000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_REGION_PERMISSION 0x0041891c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_REGION_PERMISSION_ALLOCATION_MASK 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_REGION_PERMISSION_ALLOCATION_MASK_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_REGION_PERMISSION_MASK 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_REGION_PERMISSION_MASK_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE 0x00418920 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS 31:16 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X16X2_4X4 0x0001 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_4X4 0x0001 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_16X16_4X4 0x0002 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_4X4 0x0002 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X16_4X2 0x0004 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_4X2 0x0004 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_2X4 0x0008 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X16_2X4 0x0008 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X8_4X4 0x0010 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_8X8_4X2 0x0020 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_8X8_2X4 0x0040 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X16_4X8 0x0080 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_4X8_2X2 0x0100 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_16X8_4X2 0x0200 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_16X8_2X4 0x0400 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_8X8_2X2 0x0800 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_4X8_1X1 0x1000 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_SPARE0 0x2000 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_SPARE1 0x4000 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_SPARE2 0x8000 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_OFFSET 0x00418924 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_OFFSET_AMOUNT 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_OFFSET_AMOUNT_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_THRESHOLD_1 0x00418928 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_THRESHOLD_1_MIN_ZCENTER 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_THRESHOLD_1_MIN_ZCENTER_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_THRESHOLD_1_MAX_ZCENTER 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_THRESHOLD_1_MAX_ZCENTER_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_THRESHOLD_1_MAX_CLIPPED_SLOPE 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_THRESHOLD_1_MAX_CLIPPED_SLOPE_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_THRESHOLD_0 0x0041892c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_THRESHOLD_0_MIN_SLOPE 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_THRESHOLD_0_MIN_SLOPE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_THRESHOLD_0_MAX_SLOPE 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_Z_GAMUT_THRESHOLD_0_MAX_SLOPE_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL 0x00418930 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL_SAVE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL_SAVE_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL_SAVE_RUN 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL_RESTORE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL_RESTORE_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL_RESTORE_RUN 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL_SCRUB 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL_SCRUB_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL_SCRUB_RUN 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL_SCRUBBED 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL_SCRUBBED_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_CTRL_SCRUBBED_TRUE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_ADDR 0x00418934 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_ADDR_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_ADDR_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_SIZE 0x00418938 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DIRECT_CTXSW_SIZE_VALUE 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HEAVY_BUNDLE_ADDITIONS 0x0041893c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HEAVY_BUNDLE_ADDITIONS_ADDRESS_0 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HEAVY_BUNDLE_ADDITIONS_ADDRESS_0_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HEAVY_BUNDLE_ADDITIONS_ADDRESS_1 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_HEAVY_BUNDLE_ADDITIONS_ADDRESS_1_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_LIMIT0 0x00418940 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_LIMIT0_CRSTR2ZCULL_VALUE 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_LIMIT0_CRSTR2ZCULL_VALUE_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_LIMIT0_WIDREQ2ZCULL_VALUE 19:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_LIMIT0_WIDREQ2ZCULL_VALUE_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC 0x00418944 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_FLUSH_PENDING_WRITES_BUNDLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_FLUSH_PENDING_WRITES_BUNDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_FLUSH_PENDING_WRITES_BUNDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_REPORT_SEMAPHORE_D_BUNDLE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_REPORT_SEMAPHORE_D_BUNDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_REPORT_SEMAPHORE_D_BUNDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_BACK_END_COPY_E_BUNDLE 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_BACK_END_COPY_E_BUNDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_BACK_END_COPY_E_BUNDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_PM_TRIGGER_END_BUNDLE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_PM_TRIGGER_END_BUNDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_PM_TRIGGER_END_BUNDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BUNDLE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BUNDLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BUNDLE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SYNC_ON_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BUNDLE__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG 0x00418970 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG1 0x00418974 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP(i) (0x00418980+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP__SIZE_1 32 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_0 2:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_0_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_1 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_1_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_2 10:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_2_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_3 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_3_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_4 18:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_4_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_5 22:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_5_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_6 26:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_6_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_7 30:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_7_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION(i) (0x00418a00+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_FAR_Z 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_FAR_Z_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT 15:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_LOW_RES_Z 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_Z_16X16_4X2 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_LOW_RES_Z_2X4 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_Z_16X16_2X4 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_HIGH_RES_Z 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_Z_16X16X2_4X4 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_LOW_RES_ZS 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_ZS_16X16_4X4 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_Z_16X8_4X4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_Z_8X8_4X2 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_Z_8X8_2X4 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_Z_16X16_4X8 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_Z_4X8_2X2 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_ZS_16X8_4X2 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_ZS_16X8_2X4 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_ZS_8X8_2X2 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_Z_4X8_1X1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_Z_NONE 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCREGION_RAMFORMAT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSIZE(i) (0x00418a04+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSIZE__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSIZE_HEIGHT 12:1 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSIZE_HEIGHT_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSIZE_HEIGHT__MULTIPLE 0x020 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x040 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSIZE_HEIGHT__MAX 0x4000 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSIZE_WIDTH 28:16 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSIZE_WIDTH_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSIZE_WIDTH__MULTIPLE 0x0010 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 0x0010 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSIZE_WIDTH__MAX 0x4000 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCOFFSET(i) (0x00418a08+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCOFFSET__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCOFFSET_Y 11:0 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCOFFSET_Y_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCOFFSET_Y__MULTIPLE 0x010 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCOFFSET_X 27:16 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCOFFSET_X_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCOFFSET_X__MULTIPLE 0x010 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRT_ARRAY_INDEX(i) (0x00418a0c+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRT_ARRAY_INDEX__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRT_ARRAY_INDEX_OFFSET 10:0 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRT_ARRAY_INDEX_OFFSET_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRT_ARRAY_INDEX_SIZE 27:16 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRT_ARRAY_INDEX_SIZE_INIT 0x001 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTART(i) (0x00418a10+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTART__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTART_ADDR 15:0 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTART_ADDR_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTART_ADDR__MULTIPLE 0x0001 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTART_NORMALIZED_SIZE_PER_LAYER 31:16 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTART_NORMALIZED_SIZE_PER_LAYER_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_SIZE(i) (0x00418a14+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_SIZE__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_SIZE_TOTAL 15:0 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_SIZE_TOTAL_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_SIZE_PER_LAYER 31:16 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCRAM_SIZE_PER_LAYER_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS(i) (0x00418a18+(i)*32) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_VALID 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_VALID_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_VALID_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_ZDIR 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_ZDIR_LESS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_ZDIR_GREATER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_ZDIR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_ZFORMAT 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_ZFORMAT_MSB 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_ZFORMAT_FP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_ZFORMAT_ZTRICK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_ZFORMAT_ZF32_1 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_ZFORMAT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_FORCE_MATCH 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_FORCE_MATCH_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_FORCE_MATCH_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_FORCE_MATCH_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SUBREGION_MODE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SUBREGION_MODE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SUBREGION_MODE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SUBREGION_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SFUNC 14:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SFUNC_NEVER 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SFUNC_LESS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SFUNC_EQUAL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SFUNC_LEQUAL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SFUNC_GREATER 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SFUNC_NOTEQUAL 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SFUNC_GEQUAL 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SFUNC_ALWAYS 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SFUNC_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SREF 23:16 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SREF_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SMASK 31:24 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_ZCULL_ZCSTATUS_SMASK_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG 0x00418000 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ZBC_EN 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ZBC_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ZBC_EN_ENABLED 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ZBC_EN_Z_ONLY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ZBC_EN_C_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ZBC_EN_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_EARLYZ_NOUPDATE 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_EARLYZ_NOUPDATE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_EARLYZ_NOUPDATE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_EARLYZ_NOUPDATE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_EARLYZ_IGNORE_PXCNT 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_EARLYZ_IGNORE_PXCNT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_EARLYZ_IGNORE_PXCNT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_EARLYZ_IGNORE_PXCNT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_EARLYZ 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_EARLYZ_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_EARLYZ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_EARLYZ_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_RUN_DS_NOW 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_RUN_DS_NOW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_RUN_DS_NOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ZONLY 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ZONLY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ZONLY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ZONLY_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_STENCIL_KEEP 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_STENCIL_KEEP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_STENCIL_KEEP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_STENCIL_KEEP_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_DS_ROP_FORCE_BC_ON 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_DS_ROP_FORCE_BC_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_DS_ROP_FORCE_BC_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_DS_ROP_FORCE_BC_ON_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_DS_PROP_FORCE_BC_ON 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_DS_PROP_FORCE_BC_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_DS_PROP_FORCE_BC_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_DS_PROP_FORCE_BC_ON_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_DS_RSTR_FORCE_BC_ON 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_DS_RSTR_FORCE_BC_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_DS_RSTR_FORCE_BC_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_DS_RSTR_FORCE_BC_ON_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_RTL_KNOBS 17:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_RTL_KNOBS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_RTL_KNOBS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_BYPASS_PROP 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_BYPASS_PROP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_BYPASS_PROP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_BYPASS_PROP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_BYPASS_ROP 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_BYPASS_ROP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_BYPASS_ROP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_BYPASS_ROP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_BYPASS_RSTR 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_BYPASS_RSTR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_BYPASS_RSTR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_BYPASS_RSTR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_COLOR 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_COLOR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_COLOR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_COLOR_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_DEPTH 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_DEPTH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_DEPTH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_DEPTH_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_STENCIL 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_STENCIL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_STENCIL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_STENCIL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ROP_ALWAYS_DIRTY 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ROP_ALWAYS_DIRTY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ROP_ALWAYS_DIRTY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_ROP_ALWAYS_DIRTY_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_SP_SWIZZLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_SP_SWIZZLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_SP_SWIZZLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_DEBUG_SP_SWIZZLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG 0x00418004 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG_USE_DS_CT_SEL_DL_SRC_BLND 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG_USE_DS_CT_SEL_DL_SRC_BLND_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG_USE_CT_SEL_PITCH_ACTIVE 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG_USE_CT_SEL_PITCH_ACTIVE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG_DS_PROPAGATE_BDL_ENABLE 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG_DS_PROPAGATE_BDL_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG_X_CHANNEL_ONLY_MATCH_0 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG_X_CHANNEL_ONLY_MATCH_0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG_X_CHANNEL_ONLY_MATCH_0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG_X_CHANNEL_ONLY_MATCH_0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG_EXTRA_PROPAGATION_CYC 31:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG_EXTRA_PROPAGATION_CYC_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG2 0x00418008 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG2_DS_PROPAGATE_BDL_ADDR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG2_DS_PROPAGATE_BDL_ADDR_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG2_STENCIL_ZBC_EN 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG2_STENCIL_ZBC_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG2_STENCIL_ZBC_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG2_STENCIL_ZBC_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG2_SPARE 31:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ROP_DEBUG2_SPARE_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_R(i) (0x00418010+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_R__SIZE_1 15 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_R_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_R_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_G(i) (0x0041804c+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_G__SIZE_1 15 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_G_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_G_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_B(i) (0x00418088+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_B__SIZE_1 15 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_B_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_B_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_A(i) (0x004180c4+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_A__SIZE_1 15 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_A_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_COLOR_A_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT 0x00418100 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03 20:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04 27:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT 0x00418104 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07 20:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08 27:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT 0x00418108 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11 20:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12 27:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT 0x0041810c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15 20:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_INVALID 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_ZERO 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_UNORM_ONE 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RF32_GF32_BF32_AF32 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_R16_G16_B16_A16 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RN16_GN16_BN16_AN16 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RS16_GS16_BS16_AS16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RU16_GU16_BU16_AU16 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RF16_GF16_BF16_AF16 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A8R8G8B8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A8RL8GL8BL8 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A2B10G10R10 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_AU2BU10GU10RU10 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A8B8G8R8 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A8BL8GL8RL8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_AN8BN8GN8RN8 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_AS8BS8GS8RS8 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_AU8BU8GU8RU8 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A2R10G10B10 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_BF10GF11RF11 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z(i) (0x00418110+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z__SIZE_1 15 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT 0x0041814c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_01 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_01_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_01_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_01_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_02 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_02_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_02_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_02_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_03 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_03_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_03_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_03_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_04 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_04_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_04_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_04_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT 0x00418150 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_05 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_05_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_05_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_05_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_06 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_06_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_06_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_06_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_07 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_07_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_07_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_07_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_08 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_08_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_08_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_08_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT 0x00418154 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_09 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_09_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_09_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_09_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_10 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_10_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_10_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_10_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_11 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_11_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_11_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_11_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_12 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_12_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_12_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_12_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT 0x00418158 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_13 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_13_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_13_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_13_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_14 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_14_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_14_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_14_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_15 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_15_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_15_FP32 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_15_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S(i) (0x0041815c+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S__SIZE_1 15 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_VAL 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_VAL__INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT 0x00418198 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_01 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_01_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_01_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_01_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_02 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_02_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_02_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_02_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_03 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_03_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_03_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_03_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_04 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_04_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_04_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_04_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT 0x0041819c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_05 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_05_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_05_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_05_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_06 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_06_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_06_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_06_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_07 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_07_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_07_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_07_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_08 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_08_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_08_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_08_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT 0x004181a0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_09 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_09_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_09_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_09_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_10 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_10_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_10_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_10_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_11 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_11_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_11_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_11_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_12 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_12_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_12_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_12_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT 0x004181a4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_13 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_13_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_13_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_13_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_14 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_14_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_14_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_14_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_15 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_15_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_15_U8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_15_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG 0x00418e00 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_TILED_CACHING 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_TILED_CACHING_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_TILED_CACHING_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_TC_LAZY_VALIDATION 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_TC_LAZY_VALIDATION_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_TC_LAZY_VALIDATION_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_SETUP_OUTPUT_LIMITER 7:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_SETUP_OUTPUT_LIMITER_DISABLE 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BTWT_FIFO_REDUCE_DIV32 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BTWT_FIFO_REDUCE_DIV32_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BTWT_FIFO_REDUCE_DIV32_FULLSIZE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY_ZERO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY_MULTI 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY_ONE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BIN_SEMAD_REPORT_NONE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BIN_SEMAD_REPORT_NONE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BIN_SEMAD_REPORT_NONE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_PM_MODE_E_BUNDLE_ADDR 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_PM_MODE_E_BUNDLE_ADDR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_PM_MODE_E_BUNDLE_ADDR_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_TREAT_NON_BINNABLE_AS_IMMEDIATE 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_TREAT_NON_BINNABLE_AS_IMMEDIATE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_TREAT_NON_BINNABLE_AS_IMMEDIATE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_SPILL_POINT_PATH 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_SPILL_POINT_PATH_AUTOMATIC 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_SPILL_POINT_PATH_SPILL_BUFFER 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BUNDLE_FILTER 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BUNDLE_FILTER_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BUNDLE_FILTER_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_MULTIPLE_INTERVALS_PER_BIN 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_MULTIPLE_INTERVALS_PER_BIN_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_MULTIPLE_INTERVALS_PER_BIN_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_INSERT_DEBUG_TOKENS 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_INSERT_DEBUG_TOKENS_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_INSERT_DEBUG_TOKENS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT 29:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0010 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0020 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0040 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0080 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0100 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0180 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0200 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0300 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0400 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0600 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0800 0xb /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0A00 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0C00 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X0E00 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0X1000 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BIN_SCC_FEEDBACK_DATA_SYNC 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BIN_SCC_FEEDBACK_DATA_SYNC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_BIN_SCC_FEEDBACK_DATA_SYNC_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_RESERVED 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG_RESERVED_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DEBUG 0x00418e04 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DEBUG_RECEIVED_BAD_BUNDLE_DATA 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DEBUG_RESOLVED_TC_ENABLE 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DEBUG_UNEXPECTED_L0_PACKET 2:2 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DEBUG_OCCUPIED_SPILL_BUFFER_ENTRIES 26:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM 0x00418e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_USERDATA_BUNDLE_FLUSH_GROUP 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_STATIC_PATTERN_2AA_10_GROUP 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_STATIC_PATTERN_155_10_GROUP 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_SELECT_MAX 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE 0x00418e24 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE 0x00418e28 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0x030 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_VALID 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_VALID_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_TIMEOUT 0x00418e34 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_TIMEOUT_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_TIMEOUT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_COUNT 0x00418e38 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_COUNT_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_COUNT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO 0x00418e3c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_BUNDLE_ADDR 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON 30:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_CBE_MEMORY 0x0001 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_CBE_SLOT 0x0002 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_PAGEPOOL 0x0003 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_CBTBL 0x0004 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_BIN_MEMORY 0x0005 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_LEVEL0 0x0006 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_LEVEL1 0x0007 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_STATE_COUNT 0x0008 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_TC_FLUSH_METHOD 0x0009 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_RTV_LIMIT_HIT 0x000a /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_NON_BINNABLE_STATE 0x000b /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_TIMEOUT 0x000c /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_INTERVAL_BOUNDARY 0x000d /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_NON_BINNABLE_LINES 0x000e /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_TIMESLICE_BUNDLE 0x000f /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_REASON_Z_MODE_TRANSITION 0x0010 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_FLUSH_INFO_VALID 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL(i) (0x00418e40+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_0 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_0_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_0_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE 2:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_0_TYPE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_0_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_0_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_1 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_1_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_1_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE 6:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_1_TYPE 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_1_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_1_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_2 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_2_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_2_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE 10:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_2_TYPE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_2_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_2_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_3 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_3_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_3_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE 14:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_3_TYPE 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_3_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_3_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_4 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_4_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_4_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE 18:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_4_TYPE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_4_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_4_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_5 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_5_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_5_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE 22:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_5_TYPE 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_5_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_5_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_6 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_6_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_6_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE 26:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_6_TYPE 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_6_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_6_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_7 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_7_EMPTY 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_7_USED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE 30:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE_NOT_TILED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE_TILED_REPLAY_FIRST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE_TILED_REPLAY_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE_TILED_REPLAY_ALL 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_7_TYPE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_7_TYPE_LIGHT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_CTRL_SLOT_7_TYPE_HEAVY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL(i) (0x00418e50+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_0 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_0_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_0_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_0_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_1 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_1_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_1_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_1_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_2 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_2_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_2_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_2_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_3 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_3_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_3_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_3_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_4 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_4_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_4_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_4_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_5 11:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_5_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_5_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_5_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_6 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_6_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_6_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_6_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_7 15:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_7_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_7_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_7_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_8 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_8_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_8_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_8_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_9 19:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_9_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_9_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_9_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_10 21:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_10_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_10_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_10_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_11 23:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_11_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_11_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_11_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_12 25:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_12_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_12_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_12_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_13 27:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_13_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_13_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_13_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_14 29:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_14_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_14_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_14_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_15 31:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_15_CACHE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_15_NOCACHE_NO_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_15_NOCACHE_FLUSH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_ADDR(i) (0x00418e58+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_ADDR__SIZE_1 16 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_ADDR_SLOT_0 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_ADDR_SLOT_0_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_ADDR_SLOT_1 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BUNDLE_ADDR_SLOT_1_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT 0x00418e9c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_READ 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_READ_EVICT_FIRST 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_READ_EVICT_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_READ_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_WRITE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_WRITE_EVICT_FIRST 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_WRITE_EVICT_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_WRITE_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_WRITE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_WRITE_EVICT_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_WRITE_EVICT_NORMAL 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_WRITE_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_READ 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_READ_EVICT_FIRST 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_READ_EVICT_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_READ_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_STATE_READ 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_STATE_READ_EVICT_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_STATE_READ_EVICT_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LINE_CLASS_STATE_READ_EVICT_LAST 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_SPILL_BUFFER_CACHE_MGMT_MODE 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_SPILL_BUFFER_CACHE_MGMT_MODE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_SPILL_BUFFER_CACHE_MGMT_MODE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_DIRECT_CTXSW_WRITE_BURST_MODE 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_DIRECT_CTXSW_WRITE_BURST_MODE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_DIRECT_CTXSW_WRITE_BURST_MODE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_TC_TIMEOUT_ENABLE_MODE 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_TC_TIMEOUT_ENABLE_MODE_A 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_TC_TIMEOUT_ENABLE_MODE_B 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_TC_TIMEOUT_DISABLE_MODE 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_TC_TIMEOUT_DISABLE_MODE_A 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_TC_TIMEOUT_DISABLE_MODE_B 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_SPILL_WRITE_BURST_MODE 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_SPILL_WRITE_BURST_MODE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_SPILL_WRITE_BURST_MODE_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION 22:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION_NONE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION_HALF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION_QUARTER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION_EIGHTH 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION 24:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION_NONE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION_HALF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION_QUARTER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION_EIGHTH 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION_NONE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION_HALF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION_QUARTER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION_EIGHTH 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE(i) (0x00418ea0+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE__SIZE_1 21 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_V 21:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_V_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_V_DEFAULT 0x000480 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG2 0x004181cc /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG2_ASYNC_TC_OVERRIDE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG2_ASYNC_TC_OVERRIDE_NONE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONFIG2_ASYNC_TC_OVERRIDE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK 0x004181d0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_0 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_1 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_2 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_3 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_4 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_5 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_6 27:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_7 31:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_PES_MASK_GPC_7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_ADDR 0x004181d8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_ADDR_39_8_BYTE_GRANULARITY 0x00000100 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_ADDR_39_8_ALIGN_BITS 0x00000008 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_SIZE 0x004181dc /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_SIZE_256B 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_SIZE_256B_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_SIZE_256B_DEFAULT 0x0578 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_SIZE_256B_BYTE_GRANULARITY 0x0100 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_LWM 0x004181e0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_LWM_SIZE_256B 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_RM_SPILL_BUFFER_LWM_SIZE_256B_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_BETA_CB_CTRL 0x004181e4 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_BETA_CB_CTRL_CBES_RESERVE 11:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_BETA_CB_CTRL_CBES_RESERVE_NON_GFXP 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_BETA_CB_CTRL_CBES_RESERVE_GFXP 0x100 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL 0x004181e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_SAVE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_SAVE_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_SAVE_RUN_WFI 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_SAVE_RUN_GFXP 0x2 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_RESTORE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_RESTORE_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_RESTORE_RUN_WFI 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_RESTORE_RUN_GFXP 0x2 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_RESTORE_RUN_SCRUB 0x3 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_STATUS_SAVED 9:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_STATUS_SAVED_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_STATUS_SAVED_WFI 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_STATUS_SAVED_GFXP 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED 11:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED_WFI 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED_GFXP 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED_SCRUB 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_BINNER_RAM_STATUS 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_BINNER_RAM_STATUS_EMPTY 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_CTRL_BINNER_RAM_STATUS_NONEMPTY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_ADDR 0x004181ec /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_ADDR_39_8 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_ADDR_39_8_BYTE_GRANULARITY 0x00000100 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_ADDR_39_8_ALIGN_BITS 0x00000008 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_SIZE_WFI 0x004181f0 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_SIZE_WFI_VALUE 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_SIZE_GFXP 0x004181f4 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_DIRECT_CTXSW_SIZE_GFXP_VALUE 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONST_LIMITS_TS_ON 0x004181f8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONST_LIMITS_TS_ON_PPOOL 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONST_LIMITS_TS_ON_PPOOL_INIT 0x1c2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONST_LIMITS_TS_ON_CBTBL 25:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONST_LIMITS_TS_ON_CBTBL_INIT 0x1c2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONST_LIMITS_TS_OFF 0x004181fc /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONST_LIMITS_TS_OFF_PPOOL 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONST_LIMITS_TS_OFF_PPOOL_INIT 0x1f2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONST_LIMITS_TS_OFF_CBTBL 25:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CONST_LIMITS_TS_OFF_CBTBL_INIT 0x1f2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RTV_LIMITS 0x004181c8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_RTV_LIMITS_TS_OFF 13:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_RTV_LIMITS_TS_OFF_INIT 0x000d /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_RTV_LIMITS_TS_ON 29:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_RTV_LIMITS_TS_ON_INIT 0x000c /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG 0x00418e0c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG1 0x00418e10 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SWDX_CG1_SLCG__PROD 0x7fffffff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x00418880 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE_128KB 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE_64KB 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN_FULL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN_HALF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN_QUARTER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN_NO_PTE_COMP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE_ON 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE_OFF 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_PDE_CACHE_MODE 8:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_PDE_CACHE_MODE_ON 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_PDE_CACHE_MODE_EVICT_SMPG_PARTIALS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_PDE_CACHE_MODE_EVICT_ALL_PARTIALS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_PDE_CACHE_MODE_OFF 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_L2_SEND_MODE 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_L2_SEND_MODE_ONE_PTE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_L2_SEND_MODE_WHOLE_CL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_WORK_CREATION_DISABLE 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_WORK_CREATION_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_WORK_CREATION_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_ATOMIC_CAPABILITY_MODE 25:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_STRONG_BIT_ATOMIC_CYA 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL 0x00419480 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_VM_PG_SIZE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_VM_PG_SIZE_128KB 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_VM_PG_SIZE_64KB 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_COMP_FAULT 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_COMP_FAULT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_COMP_FAULT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_MISS_GRAN 4:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_MISS_GRAN_FULL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_MISS_GRAN_HALF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_MISS_GRAN_QUARTER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_MISS_GRAN_NO_PTE_COMP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_CACHE_MODE 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_CACHE_MODE_ON 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_CACHE_MODE_OFF 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_PDE_CACHE_MODE 8:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_PDE_CACHE_MODE_ON 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_PDE_CACHE_MODE_EVICT_SMPG_PARTIALS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_PDE_CACHE_MODE_EVICT_ALL_PARTIALS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_PDE_CACHE_MODE_OFF 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_L2_SEND_MODE 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_L2_SEND_MODE_ONE_PTE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_L2_SEND_MODE_WHOLE_CL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_WORK_CREATION_DISABLE 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_WORK_CREATION_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_WORK_CREATION_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_USE_PDB_BIG_PAGE_SIZE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_USE_PDB_BIG_PAGE_SIZE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_ATOMIC_CAPABILITY_MODE 25:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_ATOMIC_CAPABILITY_MODE_L2 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_ATOMIC_CAPABILITY_MODE_RMW 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_ATOMIC_CAPABILITY_MODE_POWER 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_STRONG_BIT_ATOMIC_CYA 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_STRONG_BIT_ATOMIC_CYA_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_STRONG_BIT_ATOMIC_CYA_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM 0x00418884 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_00 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_01 0x001 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_02 0x002 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_03 0x003 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_04 0x004 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_05 0x005 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_06 0x006 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_07 0x007 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_08 0x008 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_09 0x009 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_0A 0x00a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_0B 0x00b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_0C 0x00c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_0D 0x00d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_0E 0x00e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_0F 0x00f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_10 0x010 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_11 0x011 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_12 0x012 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_13 0x013 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_14 0x014 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_15 0x015 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_16 0x016 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_17 0x017 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_18 0x018 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_19 0x019 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1A 0x01a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1B 0x01b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1C 0x01c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1D 0x01d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1E 0x01e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1F 0x01f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_20 0x020 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_21 0x021 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_22 0x022 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_23 0x023 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_24 0x024 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_25 0x025 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_26 0x026 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_27 0x027 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_28 0x028 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_29 0x029 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_2A 0x02a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_2B 0x02b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_2C 0x02c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_2D 0x02d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_2E 0x02e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_2F 0x02f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_30 0x030 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_31 0x031 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_32 0x032 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_33 0x033 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_34 0x034 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_35 0x035 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_36 0x036 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_37 0x037 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_38 0x038 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_39 0x039 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_3A 0x03a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_3B 0x03b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_3C 0x03c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_3D 0x03d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_3E 0x03e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_3F 0x03f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_40 0x040 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_41 0x041 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_42 0x042 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_43 0x043 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_44 0x044 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_45 0x045 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_46 0x046 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_47 0x047 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_48 0x048 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_49 0x049 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_4A 0x04a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_4B 0x04b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_4C 0x04c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_4D 0x04d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_4E 0x04e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_4F 0x04f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_50 0x050 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_51 0x051 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_52 0x052 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_53 0x053 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_54 0x054 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_55 0x055 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_56 0x056 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_57 0x057 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_58 0x058 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_59 0x059 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_5A 0x05a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_5B 0x05b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_5C 0x05c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_5D 0x05d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_5E 0x05e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_5F 0x05f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_60 0x060 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_61 0x061 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_62 0x062 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_63 0x063 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_64 0x064 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_65 0x065 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_66 0x066 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_67 0x067 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_68 0x068 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_69 0x069 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_6A 0x06a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_6B 0x06b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_6C 0x06c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_6D 0x06d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_6E 0x06e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_6F 0x06f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_70 0x070 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_71 0x071 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_72 0x072 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_73 0x073 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_74 0x074 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_75 0x075 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_76 0x076 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_77 0x077 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_78 0x078 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_79 0x079 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_7A 0x07a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_7B 0x07b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_7C 0x07c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_7D 0x07d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_7E 0x07e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_7F 0x07f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_80 0x080 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_81 0x081 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_82 0x082 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_83 0x083 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_84 0x084 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_85 0x085 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_86 0x086 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_87 0x087 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_88 0x088 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_89 0x089 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_8A 0x08a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_8B 0x08b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_8C 0x08c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_8D 0x08d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_8E 0x08e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_8F 0x08f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_90 0x090 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_91 0x091 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_92 0x092 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_93 0x093 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_94 0x094 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_95 0x095 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_96 0x096 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_97 0x097 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_98 0x098 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_99 0x099 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_9A 0x09a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_9B 0x09b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_9C 0x09c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_9D 0x09d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_9E 0x09e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_9F 0x09f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_A0 0x0a0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_A1 0x0a1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_A2 0x0a2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_A3 0x0a3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_A4 0x0a4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_A5 0x0a5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_A6 0x0a6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_A7 0x0a7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_A8 0x0a8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_A9 0x0a9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_AA 0x0aa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_AB 0x0ab /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_AC 0x0ac /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_AD 0x0ad /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_AE 0x0ae /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_AF 0x0af /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_B0 0x0b0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_B1 0x0b1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_B2 0x0b2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_B3 0x0b3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_B4 0x0b4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_B5 0x0b5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_B6 0x0b6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_B7 0x0b7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_B8 0x0b8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_B9 0x0b9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_BA 0x0ba /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_BB 0x0bb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_BC 0x0bc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_BD 0x0bd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_BE 0x0be /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_BF 0x0bf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_C0 0x0c0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_C1 0x0c1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_C2 0x0c2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_C3 0x0c3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_C4 0x0c4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_C5 0x0c5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_C6 0x0c6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_C7 0x0c7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_C8 0x0c8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_C9 0x0c9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_CA 0x0ca /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_CB 0x0cb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_CC 0x0cc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_CD 0x0cd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_CE 0x0ce /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_CF 0x0cf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_D0 0x0d0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_D1 0x0d1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_D2 0x0d2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_D3 0x0d3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_D4 0x0d4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_D5 0x0d5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_D6 0x0d6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_D7 0x0d7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_D8 0x0d8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_D9 0x0d9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_DA 0x0da /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_DB 0x0db /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_DC 0x0dc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_DD 0x0dd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_DE 0x0de /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_DF 0x0df /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_E0 0x0e0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_E1 0x0e1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_E2 0x0e2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_E3 0x0e3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_E4 0x0e4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_E5 0x0e5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_E6 0x0e6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_E7 0x0e7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_E8 0x0e8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_E9 0x0e9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_EA 0x0ea /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_EB 0x0eb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_EC 0x0ec /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_ED 0x0ed /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_EE 0x0ee /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_EF 0x0ef /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_F0 0x0f0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_F1 0x0f1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_F2 0x0f2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_F3 0x0f3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_F4 0x0f4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_F5 0x0f5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_F6 0x0f6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_F7 0x0f7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_F8 0x0f8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_F9 0x0f9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_FA 0x0fa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_FB 0x0fb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_FC 0x0fc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_FD 0x0fd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x0fe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x0ff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_100 0x100 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_101 0x101 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_102 0x102 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_103 0x103 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_104 0x104 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_105 0x105 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_106 0x106 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_107 0x107 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_108 0x108 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_109 0x109 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_10A 0x10a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_10B 0x10b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_10C 0x10c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_10D 0x10d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_10E 0x10e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_10F 0x10f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_110 0x110 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_111 0x111 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_112 0x112 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_113 0x113 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_114 0x114 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_115 0x115 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_116 0x116 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_117 0x117 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_118 0x118 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_119 0x119 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_11A 0x11a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_11B 0x11b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_11C 0x11c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_11D 0x11d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_11E 0x11e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_11F 0x11f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_120 0x120 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_121 0x121 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_122 0x122 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_123 0x123 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_124 0x124 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_125 0x125 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_126 0x126 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_127 0x127 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_128 0x128 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_129 0x129 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_12A 0x12a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_12B 0x12b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_12C 0x12c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_12D 0x12d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_12E 0x12e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_12F 0x12f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_130 0x130 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_131 0x131 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_132 0x132 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_133 0x133 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_134 0x134 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_135 0x135 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_136 0x136 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_137 0x137 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_138 0x138 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_139 0x139 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_13A 0x13a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_13B 0x13b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_13C 0x13c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_13D 0x13d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_13E 0x13e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_13F 0x13f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_140 0x140 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_141 0x141 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_142 0x142 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_143 0x143 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_144 0x144 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_145 0x145 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_146 0x146 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_147 0x147 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_148 0x148 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_149 0x149 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_14A 0x14a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_14B 0x14b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_14C 0x14c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_14D 0x14d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_14E 0x14e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_14F 0x14f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_150 0x150 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_151 0x151 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_152 0x152 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_153 0x153 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_154 0x154 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_155 0x155 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_156 0x156 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_157 0x157 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_158 0x158 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_159 0x159 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_15A 0x15a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_15B 0x15b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_15C 0x15c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_15D 0x15d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_15E 0x15e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_15F 0x15f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_160 0x160 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_161 0x161 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_162 0x162 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_163 0x163 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_164 0x164 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_165 0x165 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_166 0x166 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_167 0x167 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_168 0x168 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_169 0x169 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_16A 0x16a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_16B 0x16b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_16C 0x16c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_16D 0x16d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_16E 0x16e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_16F 0x16f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_170 0x170 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_171 0x171 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_172 0x172 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_173 0x173 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_174 0x174 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_175 0x175 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_176 0x176 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_177 0x177 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_178 0x178 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_179 0x179 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_17A 0x17a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_17B 0x17b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_17C 0x17c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_17D 0x17d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_17E 0x17e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_17F 0x17f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_180 0x180 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_181 0x181 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_182 0x182 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_183 0x183 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_184 0x184 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_185 0x185 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_186 0x186 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_187 0x187 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_188 0x188 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_189 0x189 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_18A 0x18a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_18B 0x18b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_18C 0x18c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_18D 0x18d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_18E 0x18e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_18F 0x18f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_190 0x190 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_191 0x191 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_192 0x192 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_193 0x193 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_194 0x194 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_195 0x195 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_196 0x196 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_197 0x197 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_198 0x198 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_199 0x199 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_19A 0x19a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_19B 0x19b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_19C 0x19c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_19D 0x19d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_19E 0x19e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_19F 0x19f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1A0 0x1a0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1A1 0x1a1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1A2 0x1a2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1A3 0x1a3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1A4 0x1a4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1A5 0x1a5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1A6 0x1a6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1A7 0x1a7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1A8 0x1a8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1A9 0x1a9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1AA 0x1aa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1AB 0x1ab /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1AC 0x1ac /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1AD 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1AE 0x1ae /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1AF 0x1af /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1B0 0x1b0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1B1 0x1b1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1B2 0x1b2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1B3 0x1b3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1B4 0x1b4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1B5 0x1b5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1B6 0x1b6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1B7 0x1b7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1B8 0x1b8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1B9 0x1b9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1BA 0x1ba /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1BB 0x1bb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1BC 0x1bc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1BD 0x1bd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1BE 0x1be /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1BF 0x1bf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1C0 0x1c0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1C1 0x1c1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1C2 0x1c2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1C3 0x1c3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1C4 0x1c4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1C5 0x1c5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1C6 0x1c6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1C7 0x1c7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1C8 0x1c8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1C9 0x1c9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1CA 0x1ca /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1CB 0x1cb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1CC 0x1cc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1CD 0x1cd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1CE 0x1ce /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1CF 0x1cf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1D0 0x1d0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1D1 0x1d1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1D2 0x1d2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1D3 0x1d3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1D4 0x1d4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1D5 0x1d5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1D6 0x1d6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1D7 0x1d7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1D8 0x1d8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1D9 0x1d9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1DA 0x1da /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1DB 0x1db /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1DC 0x1dc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1DD 0x1dd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1DE 0x1de /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1DF 0x1df /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1E0 0x1e0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1E1 0x1e1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1E2 0x1e2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1E3 0x1e3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1E4 0x1e4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1E5 0x1e5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1E6 0x1e6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1E7 0x1e7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1E8 0x1e8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1E9 0x1e9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1EA 0x1ea /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1EB 0x1eb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1EC 0x1ec /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1ED 0x1ed /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1EE 0x1ee /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1EF 0x1ef /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1F0 0x1f0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1F1 0x1f1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1F2 0x1f2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1F3 0x1f3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1F4 0x1f4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1F5 0x1f5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1F6 0x1f6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1F7 0x1f7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1F8 0x1f8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1F9 0x1f9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1FA 0x1fa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1FB 0x1fb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1FC 0x1fc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1FD 0x1fd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1FE 0x1fe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_GRP_1FF 0x1ff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1 24:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_00 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_01 0x001 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_02 0x002 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_03 0x003 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_04 0x004 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_05 0x005 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_06 0x006 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_07 0x007 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_08 0x008 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_09 0x009 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_0A 0x00a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_0B 0x00b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_0C 0x00c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_0D 0x00d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_0E 0x00e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_0F 0x00f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_10 0x010 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_11 0x011 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_12 0x012 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_13 0x013 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_14 0x014 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_15 0x015 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_16 0x016 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_17 0x017 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_18 0x018 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_19 0x019 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1A 0x01a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1B 0x01b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1C 0x01c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1D 0x01d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1E 0x01e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1F 0x01f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_20 0x020 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_21 0x021 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_22 0x022 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_23 0x023 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_24 0x024 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_25 0x025 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_26 0x026 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_27 0x027 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_28 0x028 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_29 0x029 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_2A 0x02a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_2B 0x02b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_2C 0x02c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_2D 0x02d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_2E 0x02e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_2F 0x02f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_30 0x030 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_31 0x031 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_32 0x032 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_33 0x033 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_34 0x034 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_35 0x035 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_36 0x036 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_37 0x037 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_38 0x038 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_39 0x039 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_3A 0x03a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_3B 0x03b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_3C 0x03c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_3D 0x03d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_3E 0x03e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_3F 0x03f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_40 0x040 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_41 0x041 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_42 0x042 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_43 0x043 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_44 0x044 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_45 0x045 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_46 0x046 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_47 0x047 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_48 0x048 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_49 0x049 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_4A 0x04a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_4B 0x04b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_4C 0x04c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_4D 0x04d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_4E 0x04e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_4F 0x04f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_50 0x050 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_51 0x051 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_52 0x052 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_53 0x053 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_54 0x054 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_55 0x055 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_56 0x056 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_57 0x057 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_58 0x058 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_59 0x059 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_5A 0x05a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_5B 0x05b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_5C 0x05c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_5D 0x05d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_5E 0x05e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_5F 0x05f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_60 0x060 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_61 0x061 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_62 0x062 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_63 0x063 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_64 0x064 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_65 0x065 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_66 0x066 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_67 0x067 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_68 0x068 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_69 0x069 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_6A 0x06a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_6B 0x06b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_6C 0x06c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_6D 0x06d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_6E 0x06e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_6F 0x06f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_70 0x070 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_71 0x071 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_72 0x072 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_73 0x073 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_74 0x074 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_75 0x075 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_76 0x076 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_77 0x077 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_78 0x078 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_79 0x079 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_7A 0x07a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_7B 0x07b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_7C 0x07c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_7D 0x07d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_7E 0x07e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_7F 0x07f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_80 0x080 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_81 0x081 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_82 0x082 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_83 0x083 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_84 0x084 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_85 0x085 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_86 0x086 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_87 0x087 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_88 0x088 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_89 0x089 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_8A 0x08a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_8B 0x08b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_8C 0x08c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_8D 0x08d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_8E 0x08e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_8F 0x08f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_90 0x090 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_91 0x091 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_92 0x092 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_93 0x093 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_94 0x094 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_95 0x095 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_96 0x096 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_97 0x097 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_98 0x098 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_99 0x099 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_9A 0x09a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_9B 0x09b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_9C 0x09c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_9D 0x09d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_9E 0x09e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_9F 0x09f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_A0 0x0a0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_A1 0x0a1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_A2 0x0a2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_A3 0x0a3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_A4 0x0a4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_A5 0x0a5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_A6 0x0a6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_A7 0x0a7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_A8 0x0a8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_A9 0x0a9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_AA 0x0aa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_AB 0x0ab /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_AC 0x0ac /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_AD 0x0ad /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_AE 0x0ae /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_AF 0x0af /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_B0 0x0b0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_B1 0x0b1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_B2 0x0b2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_B3 0x0b3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_B4 0x0b4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_B5 0x0b5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_B6 0x0b6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_B7 0x0b7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_B8 0x0b8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_B9 0x0b9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_BA 0x0ba /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_BB 0x0bb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_BC 0x0bc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_BD 0x0bd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_BE 0x0be /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_BF 0x0bf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_C0 0x0c0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_C1 0x0c1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_C2 0x0c2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_C3 0x0c3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_C4 0x0c4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_C5 0x0c5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_C6 0x0c6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_C7 0x0c7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_C8 0x0c8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_C9 0x0c9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_CA 0x0ca /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_CB 0x0cb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_CC 0x0cc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_CD 0x0cd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_CE 0x0ce /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_CF 0x0cf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_D0 0x0d0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_D1 0x0d1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_D2 0x0d2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_D3 0x0d3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_D4 0x0d4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_D5 0x0d5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_D6 0x0d6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_D7 0x0d7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_D8 0x0d8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_D9 0x0d9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_DA 0x0da /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_DB 0x0db /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_DC 0x0dc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_DD 0x0dd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_DE 0x0de /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_DF 0x0df /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_E0 0x0e0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_E1 0x0e1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_E2 0x0e2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_E3 0x0e3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_E4 0x0e4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_E5 0x0e5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_E6 0x0e6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_E7 0x0e7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_E8 0x0e8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_E9 0x0e9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_EA 0x0ea /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_EB 0x0eb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_EC 0x0ec /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_ED 0x0ed /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_EE 0x0ee /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_EF 0x0ef /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_F0 0x0f0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_F1 0x0f1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_F2 0x0f2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_F3 0x0f3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_F4 0x0f4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_F5 0x0f5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_F6 0x0f6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_F7 0x0f7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_F8 0x0f8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_F9 0x0f9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_FA 0x0fa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_FB 0x0fb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_FC 0x0fc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_FD 0x0fd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP 0x0fe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP 0x0ff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_100 0x100 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_101 0x101 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_102 0x102 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_103 0x103 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_104 0x104 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_105 0x105 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_106 0x106 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_107 0x107 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_108 0x108 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_109 0x109 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_10A 0x10a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_10B 0x10b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_10C 0x10c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_10D 0x10d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_10E 0x10e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_10F 0x10f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_110 0x110 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_111 0x111 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_112 0x112 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_113 0x113 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_114 0x114 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_115 0x115 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_116 0x116 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_117 0x117 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_118 0x118 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_119 0x119 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_11A 0x11a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_11B 0x11b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_11C 0x11c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_11D 0x11d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_11E 0x11e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_11F 0x11f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_120 0x120 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_121 0x121 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_122 0x122 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_123 0x123 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_124 0x124 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_125 0x125 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_126 0x126 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_127 0x127 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_128 0x128 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_129 0x129 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_12A 0x12a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_12B 0x12b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_12C 0x12c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_12D 0x12d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_12E 0x12e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_12F 0x12f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_130 0x130 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_131 0x131 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_132 0x132 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_133 0x133 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_134 0x134 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_135 0x135 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_136 0x136 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_137 0x137 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_138 0x138 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_139 0x139 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_13A 0x13a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_13B 0x13b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_13C 0x13c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_13D 0x13d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_13E 0x13e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_13F 0x13f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_140 0x140 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_141 0x141 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_142 0x142 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_143 0x143 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_144 0x144 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_145 0x145 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_146 0x146 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_147 0x147 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_148 0x148 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_149 0x149 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_14A 0x14a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_14B 0x14b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_14C 0x14c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_14D 0x14d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_14E 0x14e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_14F 0x14f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_150 0x150 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_151 0x151 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_152 0x152 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_153 0x153 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_154 0x154 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_155 0x155 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_156 0x156 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_157 0x157 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_158 0x158 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_159 0x159 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_15A 0x15a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_15B 0x15b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_15C 0x15c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_15D 0x15d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_15E 0x15e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_15F 0x15f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_160 0x160 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_161 0x161 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_162 0x162 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_163 0x163 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_164 0x164 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_165 0x165 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_166 0x166 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_167 0x167 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_168 0x168 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_169 0x169 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_16A 0x16a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_16B 0x16b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_16C 0x16c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_16D 0x16d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_16E 0x16e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_16F 0x16f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_170 0x170 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_171 0x171 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_172 0x172 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_173 0x173 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_174 0x174 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_175 0x175 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_176 0x176 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_177 0x177 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_178 0x178 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_179 0x179 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_17A 0x17a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_17B 0x17b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_17C 0x17c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_17D 0x17d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_17E 0x17e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_17F 0x17f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_180 0x180 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_181 0x181 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_182 0x182 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_183 0x183 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_184 0x184 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_185 0x185 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_186 0x186 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_187 0x187 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_188 0x188 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_189 0x189 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_18A 0x18a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_18B 0x18b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_18C 0x18c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_18D 0x18d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_18E 0x18e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_18F 0x18f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_190 0x190 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_191 0x191 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_192 0x192 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_193 0x193 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_194 0x194 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_195 0x195 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_196 0x196 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_197 0x197 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_198 0x198 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_199 0x199 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_19A 0x19a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_19B 0x19b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_19C 0x19c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_19D 0x19d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_19E 0x19e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_19F 0x19f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1A0 0x1a0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1A1 0x1a1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1A2 0x1a2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1A3 0x1a3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1A4 0x1a4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1A5 0x1a5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1A6 0x1a6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1A7 0x1a7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1A8 0x1a8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1A9 0x1a9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1AA 0x1aa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1AB 0x1ab /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1AC 0x1ac /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1AD 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1AE 0x1ae /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1AF 0x1af /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1B0 0x1b0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1B1 0x1b1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1B2 0x1b2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1B3 0x1b3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1B4 0x1b4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1B5 0x1b5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1B6 0x1b6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1B7 0x1b7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1B8 0x1b8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1B9 0x1b9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1BA 0x1ba /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1BB 0x1bb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1BC 0x1bc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1BD 0x1bd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1BE 0x1be /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1BF 0x1bf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1C0 0x1c0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1C1 0x1c1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1C2 0x1c2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1C3 0x1c3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1C4 0x1c4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1C5 0x1c5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1C6 0x1c6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1C7 0x1c7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1C8 0x1c8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1C9 0x1c9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1CA 0x1ca /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1CB 0x1cb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1CC 0x1cc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1CD 0x1cd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1CE 0x1ce /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1CF 0x1cf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1D0 0x1d0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1D1 0x1d1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1D2 0x1d2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1D3 0x1d3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1D4 0x1d4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1D5 0x1d5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1D6 0x1d6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1D7 0x1d7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1D8 0x1d8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1D9 0x1d9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1DA 0x1da /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1DB 0x1db /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1DC 0x1dc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1DD 0x1dd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1DE 0x1de /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1DF 0x1df /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1E0 0x1e0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1E1 0x1e1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1E2 0x1e2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1E3 0x1e3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1E4 0x1e4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1E5 0x1e5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1E6 0x1e6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1E7 0x1e7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1E8 0x1e8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1E9 0x1e9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1EA 0x1ea /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1EB 0x1eb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1EC 0x1ec /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1ED 0x1ed /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1EE 0x1ee /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1EF 0x1ef /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1F0 0x1f0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1F1 0x1f1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1F2 0x1f2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1F3 0x1f3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1F4 0x1f4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1F5 0x1f5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1F6 0x1f6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1F7 0x1f7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1F8 0x1f8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1F9 0x1f9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1FA 0x1fa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1FB 0x1fb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1FC 0x1fc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1FD 0x1fd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1FE 0x1fe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_SELECT_MUX1_GRP_1FF 0x1ff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ALT_INPUT 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ALT_INPUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ALT_INPUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ALT_INPUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_BLK_ACT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_BLK_ACT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_BLK_ACT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_BLK_ACT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM 0x00419484 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_00 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_01 0x001 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_02 0x002 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_03 0x003 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_04 0x004 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_05 0x005 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_06 0x006 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_07 0x007 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_08 0x008 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_09 0x009 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_0A 0x00a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_0B 0x00b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_0C 0x00c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_0D 0x00d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_0E 0x00e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_0F 0x00f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_10 0x010 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_11 0x011 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_12 0x012 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_13 0x013 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_14 0x014 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_15 0x015 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_16 0x016 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_17 0x017 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_18 0x018 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_19 0x019 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1A 0x01a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1B 0x01b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1C 0x01c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1D 0x01d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1E 0x01e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1F 0x01f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_20 0x020 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_21 0x021 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_22 0x022 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_23 0x023 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_24 0x024 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_25 0x025 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_26 0x026 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_27 0x027 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_28 0x028 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_29 0x029 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_2A 0x02a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_2B 0x02b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_2C 0x02c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_2D 0x02d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_2E 0x02e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_2F 0x02f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_30 0x030 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_31 0x031 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_32 0x032 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_33 0x033 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_34 0x034 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_35 0x035 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_36 0x036 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_37 0x037 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_38 0x038 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_39 0x039 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_3A 0x03a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_3B 0x03b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_3C 0x03c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_3D 0x03d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_3E 0x03e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_3F 0x03f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_40 0x040 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_41 0x041 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_42 0x042 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_43 0x043 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_44 0x044 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_45 0x045 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_46 0x046 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_47 0x047 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_48 0x048 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_49 0x049 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_4A 0x04a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_4B 0x04b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_4C 0x04c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_4D 0x04d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_4E 0x04e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_4F 0x04f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_50 0x050 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_51 0x051 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_52 0x052 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_53 0x053 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_54 0x054 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_55 0x055 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_56 0x056 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_57 0x057 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_58 0x058 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_59 0x059 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_5A 0x05a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_5B 0x05b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_5C 0x05c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_5D 0x05d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_5E 0x05e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_5F 0x05f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_60 0x060 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_61 0x061 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_62 0x062 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_63 0x063 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_64 0x064 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_65 0x065 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_66 0x066 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_67 0x067 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_68 0x068 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_69 0x069 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_6A 0x06a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_6B 0x06b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_6C 0x06c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_6D 0x06d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_6E 0x06e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_6F 0x06f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_70 0x070 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_71 0x071 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_72 0x072 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_73 0x073 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_74 0x074 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_75 0x075 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_76 0x076 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_77 0x077 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_78 0x078 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_79 0x079 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_7A 0x07a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_7B 0x07b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_7C 0x07c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_7D 0x07d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_7E 0x07e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_7F 0x07f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_80 0x080 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_81 0x081 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_82 0x082 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_83 0x083 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_84 0x084 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_85 0x085 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_86 0x086 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_87 0x087 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_88 0x088 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_89 0x089 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_8A 0x08a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_8B 0x08b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_8C 0x08c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_8D 0x08d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_8E 0x08e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_8F 0x08f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_90 0x090 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_91 0x091 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_92 0x092 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_93 0x093 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_94 0x094 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_95 0x095 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_96 0x096 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_97 0x097 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_98 0x098 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_99 0x099 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_9A 0x09a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_9B 0x09b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_9C 0x09c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_9D 0x09d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_9E 0x09e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_9F 0x09f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_A0 0x0a0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_A1 0x0a1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_A2 0x0a2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_A3 0x0a3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_A4 0x0a4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_A5 0x0a5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_A6 0x0a6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_A7 0x0a7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_A8 0x0a8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_A9 0x0a9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_AA 0x0aa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_AB 0x0ab /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_AC 0x0ac /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_AD 0x0ad /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_AE 0x0ae /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_AF 0x0af /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_B0 0x0b0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_B1 0x0b1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_B2 0x0b2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_B3 0x0b3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_B4 0x0b4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_B5 0x0b5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_B6 0x0b6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_B7 0x0b7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_B8 0x0b8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_B9 0x0b9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_BA 0x0ba /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_BB 0x0bb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_BC 0x0bc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_BD 0x0bd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_BE 0x0be /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_BF 0x0bf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_C0 0x0c0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_C1 0x0c1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_C2 0x0c2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_C3 0x0c3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_C4 0x0c4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_C5 0x0c5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_C6 0x0c6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_C7 0x0c7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_C8 0x0c8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_C9 0x0c9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_CA 0x0ca /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_CB 0x0cb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_CC 0x0cc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_CD 0x0cd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_CE 0x0ce /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_CF 0x0cf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_D0 0x0d0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_D1 0x0d1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_D2 0x0d2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_D3 0x0d3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_D4 0x0d4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_D5 0x0d5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_D6 0x0d6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_D7 0x0d7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_D8 0x0d8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_D9 0x0d9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_DA 0x0da /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_DB 0x0db /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_DC 0x0dc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_DD 0x0dd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_DE 0x0de /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_DF 0x0df /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_E0 0x0e0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_E1 0x0e1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_E2 0x0e2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_E3 0x0e3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_E4 0x0e4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_E5 0x0e5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_E6 0x0e6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_E7 0x0e7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_E8 0x0e8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_E9 0x0e9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_EA 0x0ea /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_EB 0x0eb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_EC 0x0ec /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_ED 0x0ed /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_EE 0x0ee /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_EF 0x0ef /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_F0 0x0f0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_F1 0x0f1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_F2 0x0f2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_F3 0x0f3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_F4 0x0f4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_F5 0x0f5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_F6 0x0f6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_F7 0x0f7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_F8 0x0f8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_F9 0x0f9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_FA 0x0fa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_FB 0x0fb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_FC 0x0fc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_FD 0x0fd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x0fe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x0ff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_100 0x100 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_101 0x101 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_102 0x102 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_103 0x103 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_104 0x104 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_105 0x105 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_106 0x106 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_107 0x107 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_108 0x108 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_109 0x109 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_10A 0x10a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_10B 0x10b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_10C 0x10c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_10D 0x10d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_10E 0x10e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_10F 0x10f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_110 0x110 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_111 0x111 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_112 0x112 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_113 0x113 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_114 0x114 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_115 0x115 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_116 0x116 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_117 0x117 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_118 0x118 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_119 0x119 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_11A 0x11a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_11B 0x11b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_11C 0x11c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_11D 0x11d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_11E 0x11e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_11F 0x11f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_120 0x120 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_121 0x121 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_122 0x122 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_123 0x123 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_124 0x124 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_125 0x125 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_126 0x126 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_127 0x127 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_128 0x128 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_129 0x129 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_12A 0x12a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_12B 0x12b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_12C 0x12c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_12D 0x12d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_12E 0x12e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_12F 0x12f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_130 0x130 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_131 0x131 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_132 0x132 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_133 0x133 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_134 0x134 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_135 0x135 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_136 0x136 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_137 0x137 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_138 0x138 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_139 0x139 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_13A 0x13a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_13B 0x13b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_13C 0x13c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_13D 0x13d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_13E 0x13e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_13F 0x13f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_140 0x140 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_141 0x141 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_142 0x142 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_143 0x143 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_144 0x144 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_145 0x145 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_146 0x146 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_147 0x147 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_148 0x148 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_149 0x149 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_14A 0x14a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_14B 0x14b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_14C 0x14c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_14D 0x14d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_14E 0x14e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_14F 0x14f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_150 0x150 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_151 0x151 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_152 0x152 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_153 0x153 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_154 0x154 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_155 0x155 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_156 0x156 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_157 0x157 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_158 0x158 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_159 0x159 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_15A 0x15a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_15B 0x15b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_15C 0x15c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_15D 0x15d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_15E 0x15e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_15F 0x15f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_160 0x160 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_161 0x161 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_162 0x162 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_163 0x163 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_164 0x164 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_165 0x165 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_166 0x166 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_167 0x167 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_168 0x168 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_169 0x169 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_16A 0x16a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_16B 0x16b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_16C 0x16c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_16D 0x16d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_16E 0x16e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_16F 0x16f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_170 0x170 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_171 0x171 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_172 0x172 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_173 0x173 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_174 0x174 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_175 0x175 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_176 0x176 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_177 0x177 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_178 0x178 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_179 0x179 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_17A 0x17a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_17B 0x17b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_17C 0x17c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_17D 0x17d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_17E 0x17e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_17F 0x17f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_180 0x180 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_181 0x181 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_182 0x182 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_183 0x183 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_184 0x184 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_185 0x185 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_186 0x186 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_187 0x187 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_188 0x188 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_189 0x189 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_18A 0x18a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_18B 0x18b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_18C 0x18c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_18D 0x18d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_18E 0x18e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_18F 0x18f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_190 0x190 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_191 0x191 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_192 0x192 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_193 0x193 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_194 0x194 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_195 0x195 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_196 0x196 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_197 0x197 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_198 0x198 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_199 0x199 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_19A 0x19a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_19B 0x19b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_19C 0x19c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_19D 0x19d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_19E 0x19e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_19F 0x19f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1A0 0x1a0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1A1 0x1a1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1A2 0x1a2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1A3 0x1a3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1A4 0x1a4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1A5 0x1a5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1A6 0x1a6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1A7 0x1a7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1A8 0x1a8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1A9 0x1a9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1AA 0x1aa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1AB 0x1ab /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1AC 0x1ac /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1AD 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1AE 0x1ae /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1AF 0x1af /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1B0 0x1b0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1B1 0x1b1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1B2 0x1b2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1B3 0x1b3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1B4 0x1b4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1B5 0x1b5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1B6 0x1b6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1B7 0x1b7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1B8 0x1b8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1B9 0x1b9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1BA 0x1ba /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1BB 0x1bb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1BC 0x1bc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1BD 0x1bd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1BE 0x1be /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1BF 0x1bf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1C0 0x1c0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1C1 0x1c1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1C2 0x1c2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1C3 0x1c3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1C4 0x1c4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1C5 0x1c5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1C6 0x1c6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1C7 0x1c7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1C8 0x1c8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1C9 0x1c9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1CA 0x1ca /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1CB 0x1cb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1CC 0x1cc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1CD 0x1cd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1CE 0x1ce /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1CF 0x1cf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1D0 0x1d0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1D1 0x1d1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1D2 0x1d2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1D3 0x1d3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1D4 0x1d4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1D5 0x1d5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1D6 0x1d6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1D7 0x1d7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1D8 0x1d8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1D9 0x1d9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1DA 0x1da /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1DB 0x1db /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1DC 0x1dc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1DD 0x1dd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1DE 0x1de /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1DF 0x1df /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1E0 0x1e0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1E1 0x1e1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1E2 0x1e2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1E3 0x1e3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1E4 0x1e4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1E5 0x1e5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1E6 0x1e6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1E7 0x1e7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1E8 0x1e8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1E9 0x1e9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1EA 0x1ea /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1EB 0x1eb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1EC 0x1ec /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1ED 0x1ed /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1EE 0x1ee /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1EF 0x1ef /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1F0 0x1f0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1F1 0x1f1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1F2 0x1f2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1F3 0x1f3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1F4 0x1f4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1F5 0x1f5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1F6 0x1f6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1F7 0x1f7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1F8 0x1f8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1F9 0x1f9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1FA 0x1fa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1FB 0x1fb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1FC 0x1fc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1FD 0x1fd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1FE 0x1fe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_GRP_1FF 0x1ff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1 24:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_00 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_01 0x001 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_02 0x002 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_03 0x003 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_04 0x004 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_05 0x005 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_06 0x006 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_07 0x007 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_08 0x008 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_09 0x009 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_0A 0x00a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_0B 0x00b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_0C 0x00c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_0D 0x00d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_0E 0x00e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_0F 0x00f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_10 0x010 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_11 0x011 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_12 0x012 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_13 0x013 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_14 0x014 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_15 0x015 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_16 0x016 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_17 0x017 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_18 0x018 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_19 0x019 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1A 0x01a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1B 0x01b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1C 0x01c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1D 0x01d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1E 0x01e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1F 0x01f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_20 0x020 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_21 0x021 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_22 0x022 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_23 0x023 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_24 0x024 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_25 0x025 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_26 0x026 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_27 0x027 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_28 0x028 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_29 0x029 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_2A 0x02a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_2B 0x02b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_2C 0x02c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_2D 0x02d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_2E 0x02e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_2F 0x02f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_30 0x030 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_31 0x031 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_32 0x032 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_33 0x033 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_34 0x034 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_35 0x035 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_36 0x036 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_37 0x037 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_38 0x038 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_39 0x039 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_3A 0x03a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_3B 0x03b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_3C 0x03c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_3D 0x03d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_3E 0x03e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_3F 0x03f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_40 0x040 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_41 0x041 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_42 0x042 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_43 0x043 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_44 0x044 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_45 0x045 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_46 0x046 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_47 0x047 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_48 0x048 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_49 0x049 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_4A 0x04a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_4B 0x04b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_4C 0x04c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_4D 0x04d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_4E 0x04e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_4F 0x04f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_50 0x050 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_51 0x051 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_52 0x052 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_53 0x053 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_54 0x054 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_55 0x055 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_56 0x056 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_57 0x057 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_58 0x058 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_59 0x059 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_5A 0x05a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_5B 0x05b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_5C 0x05c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_5D 0x05d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_5E 0x05e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_5F 0x05f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_60 0x060 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_61 0x061 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_62 0x062 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_63 0x063 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_64 0x064 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_65 0x065 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_66 0x066 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_67 0x067 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_68 0x068 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_69 0x069 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_6A 0x06a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_6B 0x06b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_6C 0x06c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_6D 0x06d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_6E 0x06e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_6F 0x06f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_70 0x070 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_71 0x071 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_72 0x072 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_73 0x073 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_74 0x074 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_75 0x075 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_76 0x076 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_77 0x077 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_78 0x078 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_79 0x079 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_7A 0x07a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_7B 0x07b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_7C 0x07c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_7D 0x07d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_7E 0x07e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_7F 0x07f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_80 0x080 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_81 0x081 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_82 0x082 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_83 0x083 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_84 0x084 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_85 0x085 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_86 0x086 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_87 0x087 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_88 0x088 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_89 0x089 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_8A 0x08a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_8B 0x08b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_8C 0x08c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_8D 0x08d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_8E 0x08e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_8F 0x08f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_90 0x090 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_91 0x091 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_92 0x092 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_93 0x093 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_94 0x094 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_95 0x095 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_96 0x096 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_97 0x097 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_98 0x098 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_99 0x099 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_9A 0x09a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_9B 0x09b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_9C 0x09c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_9D 0x09d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_9E 0x09e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_9F 0x09f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_A0 0x0a0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_A1 0x0a1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_A2 0x0a2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_A3 0x0a3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_A4 0x0a4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_A5 0x0a5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_A6 0x0a6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_A7 0x0a7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_A8 0x0a8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_A9 0x0a9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_AA 0x0aa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_AB 0x0ab /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_AC 0x0ac /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_AD 0x0ad /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_AE 0x0ae /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_AF 0x0af /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_B0 0x0b0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_B1 0x0b1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_B2 0x0b2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_B3 0x0b3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_B4 0x0b4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_B5 0x0b5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_B6 0x0b6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_B7 0x0b7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_B8 0x0b8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_B9 0x0b9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_BA 0x0ba /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_BB 0x0bb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_BC 0x0bc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_BD 0x0bd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_BE 0x0be /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_BF 0x0bf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_C0 0x0c0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_C1 0x0c1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_C2 0x0c2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_C3 0x0c3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_C4 0x0c4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_C5 0x0c5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_C6 0x0c6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_C7 0x0c7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_C8 0x0c8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_C9 0x0c9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_CA 0x0ca /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_CB 0x0cb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_CC 0x0cc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_CD 0x0cd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_CE 0x0ce /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_CF 0x0cf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_D0 0x0d0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_D1 0x0d1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_D2 0x0d2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_D3 0x0d3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_D4 0x0d4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_D5 0x0d5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_D6 0x0d6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_D7 0x0d7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_D8 0x0d8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_D9 0x0d9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_DA 0x0da /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_DB 0x0db /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_DC 0x0dc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_DD 0x0dd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_DE 0x0de /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_DF 0x0df /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_E0 0x0e0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_E1 0x0e1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_E2 0x0e2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_E3 0x0e3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_E4 0x0e4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_E5 0x0e5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_E6 0x0e6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_E7 0x0e7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_E8 0x0e8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_E9 0x0e9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_EA 0x0ea /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_EB 0x0eb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_EC 0x0ec /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_ED 0x0ed /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_EE 0x0ee /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_EF 0x0ef /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_F0 0x0f0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_F1 0x0f1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_F2 0x0f2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_F3 0x0f3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_F4 0x0f4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_F5 0x0f5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_F6 0x0f6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_F7 0x0f7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_F8 0x0f8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_F9 0x0f9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_FA 0x0fa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_FB 0x0fb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_FC 0x0fc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_FD 0x0fd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP 0x0fe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP 0x0ff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_100 0x100 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_101 0x101 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_102 0x102 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_103 0x103 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_104 0x104 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_105 0x105 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_106 0x106 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_107 0x107 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_108 0x108 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_109 0x109 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_10A 0x10a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_10B 0x10b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_10C 0x10c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_10D 0x10d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_10E 0x10e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_10F 0x10f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_110 0x110 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_111 0x111 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_112 0x112 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_113 0x113 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_114 0x114 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_115 0x115 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_116 0x116 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_117 0x117 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_118 0x118 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_119 0x119 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_11A 0x11a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_11B 0x11b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_11C 0x11c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_11D 0x11d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_11E 0x11e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_11F 0x11f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_120 0x120 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_121 0x121 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_122 0x122 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_123 0x123 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_124 0x124 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_125 0x125 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_126 0x126 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_127 0x127 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_128 0x128 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_129 0x129 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_12A 0x12a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_12B 0x12b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_12C 0x12c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_12D 0x12d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_12E 0x12e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_12F 0x12f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_130 0x130 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_131 0x131 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_132 0x132 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_133 0x133 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_134 0x134 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_135 0x135 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_136 0x136 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_137 0x137 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_138 0x138 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_139 0x139 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_13A 0x13a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_13B 0x13b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_13C 0x13c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_13D 0x13d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_13E 0x13e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_13F 0x13f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_140 0x140 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_141 0x141 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_142 0x142 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_143 0x143 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_144 0x144 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_145 0x145 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_146 0x146 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_147 0x147 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_148 0x148 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_149 0x149 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_14A 0x14a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_14B 0x14b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_14C 0x14c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_14D 0x14d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_14E 0x14e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_14F 0x14f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_150 0x150 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_151 0x151 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_152 0x152 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_153 0x153 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_154 0x154 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_155 0x155 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_156 0x156 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_157 0x157 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_158 0x158 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_159 0x159 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_15A 0x15a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_15B 0x15b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_15C 0x15c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_15D 0x15d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_15E 0x15e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_15F 0x15f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_160 0x160 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_161 0x161 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_162 0x162 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_163 0x163 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_164 0x164 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_165 0x165 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_166 0x166 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_167 0x167 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_168 0x168 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_169 0x169 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_16A 0x16a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_16B 0x16b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_16C 0x16c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_16D 0x16d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_16E 0x16e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_16F 0x16f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_170 0x170 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_171 0x171 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_172 0x172 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_173 0x173 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_174 0x174 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_175 0x175 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_176 0x176 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_177 0x177 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_178 0x178 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_179 0x179 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_17A 0x17a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_17B 0x17b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_17C 0x17c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_17D 0x17d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_17E 0x17e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_17F 0x17f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_180 0x180 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_181 0x181 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_182 0x182 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_183 0x183 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_184 0x184 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_185 0x185 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_186 0x186 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_187 0x187 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_188 0x188 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_189 0x189 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_18A 0x18a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_18B 0x18b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_18C 0x18c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_18D 0x18d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_18E 0x18e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_18F 0x18f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_190 0x190 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_191 0x191 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_192 0x192 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_193 0x193 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_194 0x194 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_195 0x195 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_196 0x196 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_197 0x197 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_198 0x198 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_199 0x199 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_19A 0x19a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_19B 0x19b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_19C 0x19c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_19D 0x19d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_19E 0x19e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_19F 0x19f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1A0 0x1a0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1A1 0x1a1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1A2 0x1a2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1A3 0x1a3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1A4 0x1a4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1A5 0x1a5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1A6 0x1a6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1A7 0x1a7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1A8 0x1a8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1A9 0x1a9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1AA 0x1aa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1AB 0x1ab /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1AC 0x1ac /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1AD 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1AE 0x1ae /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1AF 0x1af /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1B0 0x1b0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1B1 0x1b1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1B2 0x1b2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1B3 0x1b3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1B4 0x1b4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1B5 0x1b5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1B6 0x1b6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1B7 0x1b7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1B8 0x1b8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1B9 0x1b9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1BA 0x1ba /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1BB 0x1bb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1BC 0x1bc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1BD 0x1bd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1BE 0x1be /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1BF 0x1bf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1C0 0x1c0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1C1 0x1c1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1C2 0x1c2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1C3 0x1c3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1C4 0x1c4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1C5 0x1c5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1C6 0x1c6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1C7 0x1c7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1C8 0x1c8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1C9 0x1c9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1CA 0x1ca /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1CB 0x1cb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1CC 0x1cc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1CD 0x1cd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1CE 0x1ce /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1CF 0x1cf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1D0 0x1d0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1D1 0x1d1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1D2 0x1d2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1D3 0x1d3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1D4 0x1d4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1D5 0x1d5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1D6 0x1d6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1D7 0x1d7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1D8 0x1d8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1D9 0x1d9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1DA 0x1da /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1DB 0x1db /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1DC 0x1dc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1DD 0x1dd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1DE 0x1de /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1DF 0x1df /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1E0 0x1e0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1E1 0x1e1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1E2 0x1e2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1E3 0x1e3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1E4 0x1e4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1E5 0x1e5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1E6 0x1e6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1E7 0x1e7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1E8 0x1e8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1E9 0x1e9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1EA 0x1ea /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1EB 0x1eb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1EC 0x1ec /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1ED 0x1ed /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1EE 0x1ee /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1EF 0x1ef /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1F0 0x1f0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1F1 0x1f1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1F2 0x1f2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1F3 0x1f3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1F4 0x1f4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1F5 0x1f5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1F6 0x1f6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1F7 0x1f7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1F8 0x1f8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1F9 0x1f9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1FA 0x1fa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1FB 0x1fb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1FC 0x1fc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1FD 0x1fd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1FE 0x1fe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_SELECT_MUX1_GRP_1FF 0x1ff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ALT_INPUT 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ALT_INPUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ALT_INPUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ALT_INPUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_BLK_ACT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_BLK_ACT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_BLK_ACT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_BLK_ACT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ADDR_LOW 0x00418888 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ADDR_LOW_ALIGNMENT 0x00000008 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ADDR_LOW_BITS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ADDR_LOW_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ADDR_LOW 0x00419488 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ADDR_LOW_ALIGNMENT 0x00000008 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ADDR_LOW_BITS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ADDR_LOW_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ADDR_HIGH 0x0041888c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ADDR_HIGH_ALIGNMENT 0x00000008 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ADDR_HIGH_BITS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_ADDR_HIGH_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ADDR_HIGH 0x0041948c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ADDR_HIGH_ALIGNMENT 0x00000008 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ADDR_HIGH_BITS 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_ADDR_HIGH_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK 0x00418300 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0005c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK 0x00419400 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0005c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK 0x00418358 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0005c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK 0x00419458 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0005c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK 0x0041832c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x8 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK 0x0041942c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x8 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK 0x00418308 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK 0x00419408 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK 0x00418328 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0004c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK 0x00419428 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0004c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CONTROL 0x00418310 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK 0x00418328 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CONTROL 0x00419410 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK 0x00418328 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS 0x00418314 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS 0x00419414 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT 0x00418318 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT 0x00419418 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT 0x0041831c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT 0x0041941c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_ADDRESS 0x00418320 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_ADDRESS 0x00419420 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_GPCMMU_GLOBAL_ESR 0x00418324 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_MMU_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_MMU_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_MMU_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_MMU_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_MMU_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_MMU_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_MMU0_GPCMMU_GLOBAL_ESR 0x00419424 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_MMU0_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL 0x004188a4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_SIZE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_RB_SIZE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_SIZE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_RB_SIZE 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_PROP_SIZE 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_PROP_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_PROP_RB_SIZE 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_PROP_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_SIZE 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_FA_SIZE 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_FA_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_RB_SIZE 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_SET_INDEX_BIG_PG 19:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_SET_INDEX_BIG_PG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_SET_INDEX_SMALL_PG 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_SET_INDEX_SMALL_PG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_FAST_PATH_DISABLE 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_PRF_FAULT_ENABLE 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_PRF_FAULT_ENABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_PRF_FAULT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_FAST_PATH_DISABLE 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_PRF_FAULT_ENABLE 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_PRF_FAULT_ENABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_PRF_FAULT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_PROP_FAST_PATH_DISABLE 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_PROP_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_PROP_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_FAST_PATH_DISABLE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_L1_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_DB_SIZE 29:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_RGG_DB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_DB_SIZE 31:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_CTRL_LTP_DB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL 0x004194a4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_SIZE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_RB_SIZE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_SIZE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_RB_SIZE 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_PROP_SIZE 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_PROP_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_PROP_RB_SIZE 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_PROP_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_SIZE 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_FA_SIZE 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_FA_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_RB_SIZE 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_SET_INDEX_BIG_PG 19:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_SET_INDEX_BIG_PG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_SET_INDEX_SMALL_PG 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_SET_INDEX_SMALL_PG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_FAST_PATH_DISABLE 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_PRF_FAULT_ENABLE 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_PRF_FAULT_ENABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_PRF_FAULT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_FAST_PATH_DISABLE 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_PRF_FAULT_ENABLE 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_PRF_FAULT_ENABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_PRF_FAULT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_PROP_FAST_PATH_DISABLE 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_PROP_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_PROP_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_FAST_PATH_DISABLE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_L1_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_DB_SIZE 29:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_RGG_DB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_DB_SIZE 31:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_CTRL_LTP_DB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_MISC 0x0041837c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_MISC_ROP_SIZE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_MISC_ROP_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_MISC_ROP_RB_SIZE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_MISC_ROP_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_MISC_ROP_DB_SIZE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_MISC_ROP_DB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_MISC 0x0041947c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_MISC_ROP_SIZE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_MISC_ROP_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_MISC_ROP_RB_SIZE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_MISC_ROP_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_MISC_ROP_DB_SIZE 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_MISC_ROP_DB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD 0x004188a8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_RGG_UTLB_CL_VC_B 2:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_RGG_UTLB_CL_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_RGG_UTLB_CL_VC_NB 5:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_RGG_UTLB_CL_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_RGG_UTLB_RB_VC_B 8:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_RGG_UTLB_RB_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_RGG_UTLB_RB_VC_NB 11:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_RGG_UTLB_RB_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_LTP_UTLB_CL_VC_B 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_LTP_UTLB_CL_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_LTP_UTLB_CL_VC_NB 17:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_LTP_UTLB_CL_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_LTP_UTLB_RB_VC_B 20:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_LTP_UTLB_RB_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_LTP_UTLB_RB_VC_NB 23:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_LTP_UTLB_RB_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_LTP_UTLB_DB_VC_B 26:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_LTP_UTLB_DB_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_LTP_UTLB_DB_VC_NB 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_LTP_UTLB_DB_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_MEMBAR_RQ_TRACKING 31:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_MEMBAR_RQ_TRACKING_RW 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_MEMBAR_RQ_TRACKING_WRT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_MEMBAR_RQ_TRACKING_SYSMEM 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_RSRVD_MEMBAR_RQ_TRACKING_NONE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD 0x004194a8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_RGG_UTLB_CL_VC_B 2:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_RGG_UTLB_CL_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_RGG_UTLB_CL_VC_NB 5:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_RGG_UTLB_CL_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_RGG_UTLB_RB_VC_B 8:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_RGG_UTLB_RB_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_RGG_UTLB_RB_VC_NB 11:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_RGG_UTLB_RB_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_LTP_UTLB_CL_VC_B 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_LTP_UTLB_CL_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_LTP_UTLB_CL_VC_NB 17:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_LTP_UTLB_CL_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_LTP_UTLB_RB_VC_B 20:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_LTP_UTLB_RB_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_LTP_UTLB_RB_VC_NB 23:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_LTP_UTLB_RB_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_LTP_UTLB_DB_VC_B 26:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_LTP_UTLB_DB_VC_B_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_LTP_UTLB_DB_VC_NB 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_LTP_UTLB_DB_VC_NB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_MEMBAR_RQ_TRACKING 31:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_MEMBAR_RQ_TRACKING_RW 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_MEMBAR_RQ_TRACKING_WRT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_MEMBAR_RQ_TRACKING_SYSMEM 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_RSRVD_MEMBAR_RQ_TRACKING_NONE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS 0x004188ac /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_V 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_V_INIT 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_COUNT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_COUNT_INIT 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_HALF_LTC 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_HALF_LTC_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_HALF_LTC_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_HALF_LTC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i) ((i)+16):((i)+16) /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_SLICES_PER_LTC 30:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS_SLICES_PER_LTC_INIT 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS 0x004194ac /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_V 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_V_INIT 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_COUNT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_COUNT_INIT 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_HALF_LTC 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_HALF_LTC_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_HALF_LTC_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_HALF_LTC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i) ((i)+16):((i)+16) /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_SLICES_PER_LTC 30:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_NUM_ACTIVE_LTCS_SLICES_PER_LTC_INIT 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x004188b0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_WR_KIND 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_WR_KIND_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_RD_KIND 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_RD_KIND_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_PAGE_SIZE 18:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_PAGE_SIZE_4KB 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_PAGE_SIZE_64KB 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_PAGE_SIZE_128KB 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_PAGE_SIZE_1MB 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL 0x004194b0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL_WR_KIND 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL_WR_KIND_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL_RD_KIND 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL_RD_KIND_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL_DEBUG 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL_DEBUG_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL_DEBUG_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL_PAGE_SIZE 18:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL_PAGE_SIZE_4KB 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL_PAGE_SIZE_64KB 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL_PAGE_SIZE_128KB 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_CTRL_PAGE_SIZE_1MB 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x004188b4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR_APERTURE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR_APERTURE_VID_MEM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR_APERTURE_PEER_MEM 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR_APERTURE_SYS_MEM_C 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR_VOL 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR_VOL_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR_VOL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR_ADDR 31:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR_ADDR_INIT 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR_ADDR_ALIGNMENT 0x000000c /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_WR 0x004194b4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_WR_APERTURE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_WR_APERTURE_VID_MEM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_WR_APERTURE_PEER_MEM 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_WR_APERTURE_SYS_MEM_C 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_WR_APERTURE_SYS_MEM_NC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_WR_VOL 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_WR_VOL_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_WR_VOL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_WR_ADDR 31:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_WR_ADDR_INIT 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_WR_ADDR_ALIGNMENT 0x000000c /* */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x004188b8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD_APERTURE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD_APERTURE_VID_MEM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD_APERTURE_PEER_MEM 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD_APERTURE_SYS_MEM_C 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD_VOL 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD_VOL_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD_VOL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD_ADDR 31:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD_ADDR_INIT 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD_ADDR_ALIGNMENT 0x000000c /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_RD 0x004194b8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_RD_APERTURE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_RD_APERTURE_VID_MEM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_RD_APERTURE_PEER_MEM 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_RD_APERTURE_SYS_MEM_C 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_RD_APERTURE_SYS_MEM_NC 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_RD_VOL 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_RD_VOL_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_RD_VOL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_RD_ADDR 31:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_RD_ADDR_INIT 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_DEBUG_RD_ADDR_ALIGNMENT 0x000000c /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UPPER_ADDR_LOW 0x00418334 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UPPER_ADDR_LOW_BITS 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UPPER_ADDR_LOW_BITS_INIT 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UPPER_ADDR_LOW 0x00419434 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UPPER_ADDR_LOW_BITS 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UPPER_ADDR_LOW_BITS_INIT 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UPPER_ADDR_HIGH 0x00418338 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UPPER_ADDR_HIGH_BITS 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UPPER_ADDR_HIGH_BITS_INIT 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UPPER_ADDR_HIGH 0x00419438 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UPPER_ADDR_HIGH_BITS 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UPPER_ADDR_HIGH_BITS_INIT 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE 0x00418304 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE__PRIV_LEVEL_MASK 0x00418300 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_PROTECTED_MODE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_PROTECTED_MODE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_PROTECTED_MODE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_PROTECTED_MODE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_UPDATE_MODE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_UPDATE_MODE_FALSE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_UPDATE_MODE_TRUE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_UPDATE_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_SECURE_LOCK 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_SECURE_LOCK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_SECURE_LOCK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_VPR_LOCK_MISC 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_VPR_LOCK_MISC_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_VPR_LOCK_MISC_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_VPR_LOCK_HWPM 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_VPR_LOCK_HWPM_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_VPR_LOCK_HWPM_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_VPR_LOCK_SMPC 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_VPR_LOCK_SMPC_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_WPR_WRITE_VPR_LOCK_SMPC_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE 0x00419404 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE__PRIV_LEVEL_MASK 0x00418300 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_PROTECTED_MODE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_PROTECTED_MODE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_PROTECTED_MODE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_PROTECTED_MODE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_UPDATE_MODE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_UPDATE_MODE_FALSE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_UPDATE_MODE_TRUE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_UPDATE_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_SECURE_LOCK 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_SECURE_LOCK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_SECURE_LOCK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_VPR_LOCK_MISC 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_VPR_LOCK_MISC_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_VPR_LOCK_MISC_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_VPR_LOCK_HWPM 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_VPR_LOCK_HWPM_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_VPR_LOCK_HWPM_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_VPR_LOCK_SMPC 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_VPR_LOCK_SMPC_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_WPR_WRITE_VPR_LOCK_SMPC_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE 0x0041835c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE__PRIV_LEVEL_MASK 0x00418358 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PROTECTED_MODE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PROTECTED_MODE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PROTECTED_MODE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VPR_STATE_PROTECTED_MODE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE 0x0041945c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE__PRIV_LEVEL_MASK 0x00418358 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PROTECTED_MODE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PROTECTED_MODE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PROTECTED_MODE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VPR_STATE_PROTECTED_MODE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI 0x00418330 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI__PRIV_LEVEL_MASK 0x0041832c /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_BYPASS_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_BYPASS_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_BYPASS_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_BYPASS_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_DC_EN 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_DC_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_DC_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_DC_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_AC_EN 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_AC_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_AC_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CTRL_DBI_AC_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI 0x00419430 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI__PRIV_LEVEL_MASK 0x0041832c /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_BYPASS_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_BYPASS_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_BYPASS_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_BYPASS_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_DC_EN 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_DC_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_DC_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_DC_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_AC_EN 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_AC_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_AC_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CTRL_DBI_AC_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_BOTTOM 0x00418340 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_BOTTOM_PER_SLICE 19:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_BOTTOM_PER_SLICE_INIT 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_MEM_PARTITION_BOTTOM 0x00419440 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_MEM_PARTITION_BOTTOM_PER_SLICE 19:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_MEM_PARTITION_BOTTOM_PER_SLICE_INIT 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_MIDDLE 0x00418344 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_MIDDLE_PER_SLICE 19:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_INIT 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE 0x01000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE_LG2 0x0000c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_MEM_PARTITION_MIDDLE 0x00419444 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_MEM_PARTITION_MIDDLE_PER_SLICE 19:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_MEM_PARTITION_MIDDLE_PER_SLICE_INIT 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE 0x01000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE_LG2 0x0000c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_BOUNDARY_CFG0 0x00418348 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL 10:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT 0x603 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_MEM_PARTITION_BOUNDARY_CFG0 0x00419448 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_MEM_PARTITION_BOUNDARY_CFG0_VAL 10:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT 0x603 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG 0x0041834c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER(i) ((i)*4+1):((i)*4) /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_INVALID 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB0 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB1 0x2 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_BOTH_HSHUBS 0x3 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_PCIE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER0 1:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER1 5:4 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER2 9:8 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER3 13:12 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER4 17:16 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER5 21:20 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER6 25:24 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER7 29:28 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU_PEER_HSHUB_CONNECTION_CFG_PEER7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG 0x0041944c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER(i) ((i)*4+1):((i)*4) /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_INVALID 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB0 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB1 0x2 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_BOTH_HSHUBS 0x3 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_PCIE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER0 1:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER1 5:4 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER2 9:8 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER3 13:12 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER4 17:16 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER5 21:20 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER6 25:24 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER7 29:28 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_SYSMEM_HSHUB_CONNECTION_CFG 0x00418350 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS 1:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB0 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_BOTH_HSHUBS 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_PCIE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_SYSMEM_HSHUB_CONNECTION_CFG 0x00419450 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS 1:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INVALID 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB0 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_BOTH_HSHUBS 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_PCIE 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_GPCMMU_HYPERVISOR_CTL0 0x00418354 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_GPCMMU_HYPERVISOR_CTL0 0x00419454 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT 0x0041833c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_SIZE 3:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_SIZE_INIT 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_GRANULARITY 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_GRANULARITY_INIT 0x5 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_MODE 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_MODE_ACCESS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_MODE_DIRTY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT 0x0041943c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_SIZE 3:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_SIZE_INIT 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_GRANULARITY 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_GRANULARITY_INIT 0x5 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_DISABLE_MODE 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_MODE 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_MODE_ACCESS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_MODE_DIRTY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO 0x00418360 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL 31:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_LO 0x00419460 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL 31:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI 0x00418364 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_HI 0x00419464 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x00418890 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TX_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TX_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TX_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TX_1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TX_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TX_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_PE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_PE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_PE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPCCS 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPCCS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPCCS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_RAST 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_RAST_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_RAST_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_GCC 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_GCC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_GCC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_GPCCS 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_GPCCS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_GPCCS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_PROP 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_PROP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_PROP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_ROP_0 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_ROP_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_ROP_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_ROP_1 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_ROP_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_ROP_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_0 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_1 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_2 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_2_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_3 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_3_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_3_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_4 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_4_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_4_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_5 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_5_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_5_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_6 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_6_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_6_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_7 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_7_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK_TPC_7_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK 0x00419490 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TX_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TX_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TX_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TX_1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TX_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TX_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_PE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_PE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_PE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPCCS 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPCCS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPCCS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_RAST 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_RAST_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_RAST_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_GCC 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_GCC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_GCC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_GPCCS 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_GPCCS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_GPCCS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_PROP 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_PROP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_PROP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_ROP_0 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_ROP_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_ROP_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_ROP_1 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_ROP_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_ROP_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_0 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_0_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_0_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_1 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_1_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_1_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_2 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_2_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_2_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_3 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_3_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_3_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_4 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_4_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_4_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_5 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_5_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_5_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_6 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_6_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_6_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_7 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_7_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_UNIT_MASK_TPC_7_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x00418894 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_RD 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_RD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_RD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_WR 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_WR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_WR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_GATOM 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_GRED 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_GRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_CACHE_MGMT 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_CACHE_MGMT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_CACHE_MGMT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PREFETCH 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PREFETCH_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PREFETCH_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PF1_PREFETCH 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PF1_PREFETCH_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PF1_PREFETCH_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_MEMBAR 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_MEMBAR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_MEMBAR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PHYS_RD 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PHYS_RD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PHYS_RD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PHYS_WR 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PHYS_WR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PHYS_WR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PHYS_GRED 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PHYS_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PHYS_GRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PHYS_GATOM 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PHYS_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PHYS_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PACK_RD 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PACK_RD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PACK_RD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_CONCAT_WR 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_CONCAT_WR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_CONCAT_WR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_CONCAT_GRED 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_CONCAT_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_CONCAT_GRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_CONCAT_GATOM 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_CONCAT_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_CONCAT_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_ALL_CLIENTS 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_ALL_CLIENTS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_ALL_CLIENTS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_ALL_REQUESTS 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_ALL_REQUESTS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_ALL_REQUESTS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_VIDMEM 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_VIDMEM_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_VIDMEM_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PEER 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PEER_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_PEER_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_SYSMEM_C 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_SYSMEM_C_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_SYSMEM_C_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_SYSMEM_NC 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_SYSMEM_NC_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_SYSMEM_NC_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_TYPE 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_TYPE_VIRTUAL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_TYPE_PHYSICAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_EXCLUSIVE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_EXCLUSIVE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK_EXCLUSIVE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK 0x00419494 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_RD 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_RD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_RD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_WR 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_WR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_WR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_GATOM 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_GRED 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_GRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_CACHE_MGMT 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_CACHE_MGMT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_CACHE_MGMT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PREFETCH 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PREFETCH_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PREFETCH_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PF1_PREFETCH 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PF1_PREFETCH_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PF1_PREFETCH_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_MEMBAR 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_MEMBAR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_MEMBAR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PHYS_RD 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PHYS_RD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PHYS_RD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PHYS_WR 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PHYS_WR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PHYS_WR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PHYS_GRED 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PHYS_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PHYS_GRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PHYS_GATOM 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PHYS_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PHYS_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PACK_RD 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PACK_RD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PACK_RD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_CONCAT_WR 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_CONCAT_WR_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_CONCAT_WR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_CONCAT_GRED 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_CONCAT_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_CONCAT_GRED_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_CONCAT_GATOM 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_CONCAT_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_CONCAT_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_ALL_CLIENTS 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_ALL_CLIENTS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_ALL_CLIENTS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_ALL_REQUESTS 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_ALL_REQUESTS_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_ALL_REQUESTS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_VIDMEM 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_VIDMEM_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_VIDMEM_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PEER 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PEER_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_PEER_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_SYSMEM_C 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_SYSMEM_C_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_SYSMEM_C_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_SYSMEM_NC 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_SYSMEM_NC_ENABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_SYSMEM_NC_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_TYPE 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_TYPE_VIRTUAL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_TYPE_PHYSICAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_EXCLUSIVE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_EXCLUSIVE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PM_REQ_MASK_EXCLUSIVE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG 0x00418898 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG 0x00419498 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_MMU_CG1 0x0041889c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG1 0x0041949c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG 0x004188a0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_IDLE_BLPG_EN 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_DIS_EARLY_WUP 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_DEEP_ELPG_EN 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_IDLE_ELPG_EN 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_DIDT_DELAY 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_DIDT_DELAY_HWINIT 0xa /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_RESET_DURATION 26:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_RESET_DURATION_HWINIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_CLAMP_DELAY 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_CLAMP_DELAY_HWINIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_ZONE_OFF_MASK 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_SOFT_GATING_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG 0x004194a0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_IDLE_BLPG_EN 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_DIS_EARLY_WUP 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_DEEP_ELPG_EN 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_IDLE_ELPG_EN 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_DIDT_DELAY 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_DIDT_DELAY_HWINIT 0xa /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_RESET_DURATION 26:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_RESET_DURATION_HWINIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_CLAMP_DELAY 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_CLAMP_DELAY_HWINIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_ZONE_OFF_MASK 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_SOFT_GATING_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG1 0x004188bc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU_PG1_ZONE_SEQ 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU_PG1_ZONE_MASK 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU_PG1_ZONE_MASK_HWINIT 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG1 0x004194bc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG1_ZONE_SEQ 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG1_ZONE_MASK 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_MMU0_PG1_ZONE_MASK_HWINIT 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP 0x004185ff:0x00418400 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1 0x00418400 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_FRSTR_3D 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_FRSTR_3D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_FRSTR_3D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_FRSTR_3D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_FRSTR_2D 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_FRSTR_2D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_FRSTR_2D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_FRSTR_2D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_CSB_3D 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_CSB_3D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_CSB_3D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_CSB_3D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_CSB_2D 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_CSB_2D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_CSB_2D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_CSB_2D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SBFILTER 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SBFILTER_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SBFILTER_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SBFILTER_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_FORCE_NO_COMPRESSION 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_FORCE_NO_COMPRESSION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_FORCE_NO_COMPRESSION_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_FORCE_NO_COMPRESSION_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_ZCOMPRESS 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_ZCOMPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_ZCOMPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_ZCOMPRESS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_CCOMPRESS 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_CCOMPRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_CCOMPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_CCOMPRESS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_BLENDOPT 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_BLENDOPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_BLENDOPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_BLENDOPT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SKIP_ZROP 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SKIP_ZROP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SKIP_ZROP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SKIP_ZROP_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB 18:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB_Z_PRIORITY 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB_C_PRIORITY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB_ROUND_ROBIN 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_TIR_TRUNCATION_REDUCTION_OPT 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_TIR_TRUNCATION_REDUCTION_OPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_TIR_TRUNCATION_REDUCTION_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_TIR_TRUNCATION_REDUCTION_OPT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER 22:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_TIER_1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_TIER_1_2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_TIER_1_2_3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_COLOR_MODULATION_AVOID_NULL_ITER 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_COLOR_MODULATION_AVOID_NULL_ITER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_COLOR_MODULATION_AVOID_NULL_ITER_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_COLOR_MODULATION_AVOID_NULL_ITER_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_TIR_FORCE_EOCP_AT_FRSTR_END 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_TIR_FORCE_EOCP_AT_FRSTR_END_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_TIR_FORCE_EOCP_AT_FRSTR_END_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_TIR_FORCE_EOCP_AT_FRSTR_END_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_ROP_SLICE 26:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_ROP_SLICE_NONE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_ROP_SLICE_ROP0 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_ROP_SLICE_ROP1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_SWALLOW_ROP_SLICE_BOTH 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_KILL_BUNDLES_TO_FS_RDM 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_KILL_BUNDLES_TO_FS_RDM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_KILL_BUNDLES_TO_FS_RDM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_KILL_BUNDLES_TO_FS_RDM_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_ASSUME_FULL_CPIX_FOR_BIN_COUNT 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_ASSUME_FULL_CPIX_FOR_BIN_COUNT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_ASSUME_FULL_CPIX_FOR_BIN_COUNT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_ASSUME_FULL_CPIX_FOR_BIN_COUNT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_VISIBLE_EARLY_Z 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_VISIBLE_EARLY_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_VISIBLE_EARLY_Z_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_VISIBLE_EARLY_Z_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_RDM_DETERMINISM_MODE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_RDM_DETERMINISM_MODE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_RDM_DETERMINISM_MODE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG1_RDM_DETERMINISM_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2 0x00418404 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_PITCH_2D_CHECK 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_PITCH_2D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_PITCH_2D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_PITCH_2D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_PITCH_3D_CHECK 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_PITCH_3D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_PITCH_3D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_PITCH_3D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_WIDTH_3D_ZT_CHECK 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_WIDTH_3D_ZT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_WIDTH_3D_ZT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_WIDTH_3D_ZT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_HEIGHT_3D_ZT_CHECK 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_HEIGHT_3D_ZT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_HEIGHT_3D_ZT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_HEIGHT_3D_ZT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_WIDTH_3D_CT_CHECK 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_WIDTH_3D_CT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_WIDTH_3D_CT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_WIDTH_3D_CT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_HEIGHT_3D_CT_CHECK 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_HEIGHT_3D_CT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_HEIGHT_3D_CT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_HEIGHT_3D_CT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_2D_CHECK 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_2D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_2D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_2D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_3D_ZT_CHECK 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_3D_ZT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_3D_ZT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_3D_ZT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_3D_CT_CHECK 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_3D_CT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_3D_CT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_3D_CT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_MEMLAYOUT_2D_CHECK 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_MEMLAYOUT_2D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_MEMLAYOUT_2D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_MEMLAYOUT_2D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_MEMLAYOUT_3D_CT_CHECK 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_MEMLAYOUT_3D_CT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_MEMLAYOUT_3D_CT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_MEMLAYOUT_3D_CT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_ZBLEND_2D_CHECK 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_ZBLEND_2D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_ZBLEND_2D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_ZBLEND_2D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_ZBLEND_3D_CHECK 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_ZBLEND_3D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_ZBLEND_3D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_ZBLEND_3D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_SYSMEM_2D_CHECK 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_SYSMEM_2D_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_SYSMEM_2D_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_SYSMEM_2D_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_SYSMEM_3D_ZT_CHECK 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_SYSMEM_3D_ZT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_SYSMEM_3D_ZT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_SYSMEM_3D_ZT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_SYSMEM_3D_CT_CHECK 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_SYSMEM_3D_CT_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_SYSMEM_3D_CT_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_KIND_SYSMEM_3D_CT_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_COMPOK_Z_PLANES_THRESHOLD 18:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_COMPOK_Z_PLANES_THRESHOLD_INIT 0x4 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_COMPOK_Z_PLANES_THRESHOLD_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_COMPOK_Z_PLANES_THRESHOLD_NEVER 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_TIR_SSAA_CHECK 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_TIR_SSAA_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_TIR_SSAA_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_TIR_SSAA_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_TIR_ZBUF_CHECK 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_TIR_ZBUF_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_TIR_ZBUF_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_TIR_ZBUF_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_PSI_SSAA_CONF_PIX_CHECK 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_PSI_SSAA_CONF_PIX_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_PSI_SSAA_CONF_PIX_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG2_PSI_SSAA_CONF_PIX_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3 0x00418408 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_ERROR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_ERROR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_INFO 11:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_INFO_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_INFO_SEEN_PIXOUT_EOST_SHADER_COVG 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_INFO_PIXOUT_UPSTREAM_STALL_AT_EOST 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_INFO_PIXOUT_AND_PROP_COVG_EOST_MATCHING 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_INFO_SHADER_COVG_EOST_MATCHING 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_INFO_MRT_EOST_MATCHING 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_INFO_MRT_OVERFLOW 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_INFO_CONSTANT_COLOR_NO_PIXOUT_RETIRE 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_INFO_PIXOUT_EOST_ON_LAST_RENDER_TARGET 0x8 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_CDP_ASSERTION_INFO_UNEXPECTED_PIXOUT_PACKET 0x9 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_MAX_THREADS_IN_C_BINNING_TILE 21:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_MAX_THREADS_IN_C_BINNING_TILE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_MAX_THREADS_IN_Z_BINNING_TILE 29:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_MAX_THREADS_IN_Z_BINNING_TILE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_TIR_PSS_COLOR_ERROR 30:30 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_TIR_PSS_COLOR_ERROR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG3_TIR_PSS_COLOR_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4 0x0041840c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_INIT 0x008 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_2D 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_2D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_2D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_2D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_3D 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_3D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_3D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_3D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE 22:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_INIT 0x001 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_OVERRIDE 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_OVERRIDE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_OVERRIDE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_NEXT_ROP_FOR_BYPASS 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_NEXT_ROP_FOR_BYPASS_ROP0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG4_NEXT_ROP_FOR_BYPASS_ROP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG5 0x00418410 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG5_CSLF_WR_LIMIT 11:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG5_CSLF_WR_LIMIT_INIT 0xfff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG5_ZTLF_WR_LIMIT 28:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG5_ZTLF_WR_LIMIT_INIT 0x1fff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG6 0x00418414 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG6_CZLF_WR_LIMIT 11:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG6_CZLF_WR_LIMIT_INIT 0xfff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG6_ZPASS_WR_LIMIT 27:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG6_ZPASS_WR_LIMIT_INIT 0xfff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG7 0x00418418 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG7_CDP_COVG_WR_LIMIT 12:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG7_CDP_COVG_WR_LIMIT_INIT 0x1fff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG7_PXB_C_WR_LIMIT 26:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG7_PXB_C_WR_LIMIT_INIT 0x7ff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG8 0x0041841c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG8_CBF_WR_LIMIT 10:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG8_CBF_WR_LIMIT_INIT 0x3ff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG8_ZBF_WR_LIMIT 20:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG8_ZBF_WR_LIMIT_INIT 0x1ff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG8_MAX_CPIX_IN_C_BINNING_TILE 31:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_DEBUG8_MAX_CPIX_IN_C_BINNING_TILE_INIT 0x1c0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR 0x00418420 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_PITCH_2D_VIOL 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_PITCH_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_PITCH_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_PITCH_3D_VIOL 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_PITCH_3D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_PITCH_3D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_WIDTH_3D_ZT_VIOL 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_WIDTH_3D_ZT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_WIDTH_3D_ZT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_HEIGHT_3D_ZT_VIOL 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_HEIGHT_3D_ZT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_HEIGHT_3D_ZT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_WIDTH_3D_CT_VIOL 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_WIDTH_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_WIDTH_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_HEIGHT_3D_CT_VIOL 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_HEIGHT_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_HEIGHT_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_2D_VIOL 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_3D_ZT_VIOL 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_3D_ZT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_3D_ZT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_3D_CT_VIOL 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_MEMLAYOUT_2D_VIOL 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_MEMLAYOUT_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_MEMLAYOUT_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_MEMLAYOUT_3D_CT_VIOL 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_MEMLAYOUT_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_MEMLAYOUT_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_ZBLEND_2D_VIOL 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_ZBLEND_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_ZBLEND_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_ZBLEND_3D_VIOL 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_ZBLEND_3D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_ZBLEND_3D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_SYSMEM_2D_VIOL 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_SYSMEM_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_SYSMEM_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_SYSMEM_3D_ZT_VIOL 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_SYSMEM_3D_ZT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_SYSMEM_3D_ZT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_SYSMEM_3D_CT_VIOL 15:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_SYSMEM_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_KIND_SYSMEM_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_TIR_SSAA_VIOL 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_TIR_SSAA_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_TIR_SSAA_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_PSI_SSAA_CONF_PIX_VIOL 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_PSI_SSAA_CONF_PIX_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_PSI_SSAA_CONF_PIX_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_TIR_ZBUF_VIOL 18:18 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_TIR_ZBUF_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_TIR_ZBUF_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_COORD 0x00418434 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_COORD_X 15:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_COORD_X_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_COORD_Y 31:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_COORD_Y_INIT 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT 0x00418438 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_DST 6:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_DST_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_CT 14:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_CT_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_ZT 19:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_ZT_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_BLEND_3D 20:20 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_BLEND_3D_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_LOGICOP_3D 21:21 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_LOGICOP_3D_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_AA_SAMPLES 27:24 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_AA_SAMPLES_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_OPERATION_2D 30:28 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_FORMAT_OPERATION_2D_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE 0x0041843c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_PTE_KIND 2:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_PTE_KIND_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_MMU_RESP 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_MMU_RESP_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_APERTURE 21:20 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_APERTURE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_DST_C_TO_Z 22:22 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_DST_C_TO_Z_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_C_TO_Z 23:23 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_C_TO_Z_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_COMPTAG_VLD 24:24 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_COMPTAG_VLD_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_PITCH_ACTIVE 25:25 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE_PITCH_ACTIVE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE2 0x00418440 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE2_LAYER 11:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE2_LAYER_INIT 0x000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE2_CT_TARGET 18:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_STATE2_CT_TARGET_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_OFFSET 0x00418444 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_OFFSET_V 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PROP_HWW_ESR_OFFSET_V_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PROP_PS_INVOCATIONS_LO 0x00418450 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_PS_INVOCATIONS_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_PS_INVOCATIONS_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_PS_INVOCATIONS_HI 0x00418454 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_PS_INVOCATIONS_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_PS_INVOCATIONS_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_CNT_LO 0x00418460 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_CNT_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_CNT_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_CNT_HI 0x00418464 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_CNT_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_CNT_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_CNT_LO 0x0041846c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_CNT_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_CNT_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_CNT_HI 0x00418470 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_CNT_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_CNT_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_0 0x00418480 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_0_MMU_REQ_COUNT 9:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_0_ZLAT_NUM_SUBID_ALLOCATED 20:10 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_0_ZLAT_LAST_SUBID_ACCEPTED_BY_ZSB 31:21 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1 0x00418484 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB 20:18 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI 23:21 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO 29:27 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2 0x00418488 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF 20:18 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT 23:21 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF 29:27 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3 0x0041848c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF 23:21 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ 29:27 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4 0x00418490 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6 0x00418498 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB 20:18 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES 23:21 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT 29:27 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL 0x004184a0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_64 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_65 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_66 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_67 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_68 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_69 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_70 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_71 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_72 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_73 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_74 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_75 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_76 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_77 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_78 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_79 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_80 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_81 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_82 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_83 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_84 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_85 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_86 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_87 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_88 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_89 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_90 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_91 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_92 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_93 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_94 0x5e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_95 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_96 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_97 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_98 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_99 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_100 0x64 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_101 0x65 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_102 0x66 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_103 0x67 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_104 0x68 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_105 0x69 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_106 0x6a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_107 0x6b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_108 0x6c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_109 0x6d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_110 0x6e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_111 0x6f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_112 0x70 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_113 0x71 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_114 0x72 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_115 0x73 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_116 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_117 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_118 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_119 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_120 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_121 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_122 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_123 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_124 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_125 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_126 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_127 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_128 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_129 0x81 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_130 0x82 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_131 0x83 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_132 0x84 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_133 0x85 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_134 0x86 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_135 0x87 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_136 0x88 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_137 0x89 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_138 0x8a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_139 0x8b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_140 0x8c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_141 0x8d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_142 0x8e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_143 0x8f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_144 0x90 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_145 0x91 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_146 0x92 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_147 0x93 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_148 0x94 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_149 0x95 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_150 0x96 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_151 0x97 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_152 0x98 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_153 0x99 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_154 0x9a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_155 0x9b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_156 0x9c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_157 0x9d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_158 0x9e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_159 0x9f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_160 0xa0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_161 0xa1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_162 0xa2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_163 0xa3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_164 0xa4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_165 0xa5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_166 0xa6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_167 0xa7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_168 0xa8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_169 0xa9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_170 0xaa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_171 0xab /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_172 0xac /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_173 0xad /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_174 0xae /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_175 0xaf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_176 0xb0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_177 0xb1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_178 0xb2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_179 0xb3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_180 0xb4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_181 0xb5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_182 0xb6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_183 0xb7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_184 0xb8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_185 0xb9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_186 0xba /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_187 0xbb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_188 0xbc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_189 0xbd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_190 0xbe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_191 0xbf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_192 0xc0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_193 0xc1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_194 0xc2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_195 0xc3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_196 0xc4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_197 0xc5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_198 0xc6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_199 0xc7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_200 0xc8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_201 0xc9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_202 0xca /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_203 0xcb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_204 0xcc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_205 0xcd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_206 0xce /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_207 0xcf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_208 0xd0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_209 0xd1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_210 0xd2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_211 0xd3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_212 0xd4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_213 0xd5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_214 0xd6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_215 0xd7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_216 0xd8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_217 0xd9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_218 0xda /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_219 0xdb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_220 0xdc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_221 0xdd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_222 0xde /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_223 0xdf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_224 0xe0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_225 0xe1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_226 0xe2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_227 0xe3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_228 0xe4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_229 0xe5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_230 0xe6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_231 0xe7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_232 0xe8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_233 0xe9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_234 0xea /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_235 0xeb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_236 0xec /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_237 0xed /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_238 0xee /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_239 0xef /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_240 0xf0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_241 0xf1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_242 0xf2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_243 0xf3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_244 0xf4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_245 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_246 0xf6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_247 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_248 0xf8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_249 0xf9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_250 0xfa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_251 0xfb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_252 0xfc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_GRP_253 0xfd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_STATIC_PATTERN_55_8_GROUP 0xfe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_STATIC_PATTERN_AA_8_GROUP 0xff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_64 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_65 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_66 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_67 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_68 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_69 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_70 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_71 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_72 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_73 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_74 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_75 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_76 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_77 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_78 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_79 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_80 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_81 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_82 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_83 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_84 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_85 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_86 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_87 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_88 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_89 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_90 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_91 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_92 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_93 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_94 0x5e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_95 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_96 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_97 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_98 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_99 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_100 0x64 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_101 0x65 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_102 0x66 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_103 0x67 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_104 0x68 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_105 0x69 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_106 0x6a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_107 0x6b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_108 0x6c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_109 0x6d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_110 0x6e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_111 0x6f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_112 0x70 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_113 0x71 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_114 0x72 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_115 0x73 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_116 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_117 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_118 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_119 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_120 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_121 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_122 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_123 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_124 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_125 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_126 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_127 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_128 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_129 0x81 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_130 0x82 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_131 0x83 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_132 0x84 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_133 0x85 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_134 0x86 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_135 0x87 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_136 0x88 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_137 0x89 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_138 0x8a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_139 0x8b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_140 0x8c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_141 0x8d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_142 0x8e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_143 0x8f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_144 0x90 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_145 0x91 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_146 0x92 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_147 0x93 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_148 0x94 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_149 0x95 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_150 0x96 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_151 0x97 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_152 0x98 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_153 0x99 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_154 0x9a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_155 0x9b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_156 0x9c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_157 0x9d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_158 0x9e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_159 0x9f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_160 0xa0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_161 0xa1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_162 0xa2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_163 0xa3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_164 0xa4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_165 0xa5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_166 0xa6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_167 0xa7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_168 0xa8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_169 0xa9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_170 0xaa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_171 0xab /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_172 0xac /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_173 0xad /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_174 0xae /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_175 0xaf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_176 0xb0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_177 0xb1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_178 0xb2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_179 0xb3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_180 0xb4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_181 0xb5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_182 0xb6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_183 0xb7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_184 0xb8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_185 0xb9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_186 0xba /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_187 0xbb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_188 0xbc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_189 0xbd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_190 0xbe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_191 0xbf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_192 0xc0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_193 0xc1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_194 0xc2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_195 0xc3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_196 0xc4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_197 0xc5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_198 0xc6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_199 0xc7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_200 0xc8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_201 0xc9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_202 0xca /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_203 0xcb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_204 0xcc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_205 0xcd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_206 0xce /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_207 0xcf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_208 0xd0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_209 0xd1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_210 0xd2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_211 0xd3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_212 0xd4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_213 0xd5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_214 0xd6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_215 0xd7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_216 0xd8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_217 0xd9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_218 0xda /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_219 0xdb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_220 0xdc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_221 0xdd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_222 0xde /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_223 0xdf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_224 0xe0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_225 0xe1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_226 0xe2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_227 0xe3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_228 0xe4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_229 0xe5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_230 0xe6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_231 0xe7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_232 0xe8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_233 0xe9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_234 0xea /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_235 0xeb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_236 0xec /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_237 0xed /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_238 0xee /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_239 0xef /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_240 0xf0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_241 0xf1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_242 0xf2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_243 0xf3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_244 0xf4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_245 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_246 0xf6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_247 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_248 0xf8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_249 0xf9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_250 0xfa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_251 0xfb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_252 0xfc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_GRP_253 0xfd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_STATIC_PATTERN_55_8_GROUP 0xfe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_STATIC_PATTERN_AA_8_GROUP 0xff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_PERF_SEL2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_XPG2ZLAT_LAT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_XPG2ZLAT_LAT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_XPG2ZLAT_LAT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_XPG2ZLAT_LAT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_ACCUM_LO 0x004184a4 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_ACCUM_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_ACCUM_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_ACCUM_HI 0x004184a8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_ACCUM_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_ACCUM_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_ACCUM_LO 0x004184ac /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_ACCUM_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_ACCUM_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_ACCUM_HI 0x004184b0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_ACCUM_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_ACCUM_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_INTERVAL_ACCUM_LO 0x004184b8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_INTERVAL_ACCUM_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_INTERVAL_ACCUM_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_INTERVAL_ACCUM_HI 0x004184bc /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_INTERVAL_ACCUM_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_ZPASS_INTERVAL_ACCUM_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_INTERVAL_ACCUM_LO 0x004184c0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_INTERVAL_ACCUM_LO_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_INTERVAL_ACCUM_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_INTERVAL_ACCUM_HI 0x004184c4 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_INTERVAL_ACCUM_HI_V 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PROP_EZ_ZPASS_INTERVAL_ACCUM_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG 0x00418500 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PROP_CG1 0x00418504 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PROP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG1_SLCG 24:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PROP_CG1_SLCG_ENABLED 0x000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG1_SLCG_DISABLED 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PROP_CG1_SLCG__PROD 0x000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR 0x0041867f:0x00418600 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG 0x00418600 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_OPTIMIZE_4X4 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_OPTIMIZE_4X4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_OPTIMIZE_4X4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_OPTIMIZE_4X4_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PROC_3EDGE_ALIASED 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PROC_3EDGE_ALIASED_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PROC_3EDGE_ALIASED_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PROC_3EDGE_ALIASED_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PROC_2EDGE_ALIASED 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PROC_2EDGE_ALIASED_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PROC_2EDGE_ALIASED_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PROC_2EDGE_ALIASED_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PROC_4EDGE_4X4 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PROC_4EDGE_4X4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PROC_4EDGE_4X4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PROC_4EDGE_4X4_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_POWER_FIXES 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_POWER_FIXES_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_POWER_FIXES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_POWER_FIXES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_USE_REDUCED_PRECISION_EDGE_DATA 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_USE_REDUCED_PRECISION_EDGE_DATA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_USE_REDUCED_PRECISION_EDGE_DATA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_USE_REDUCED_PRECISION_EDGE_DATA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PLACEHOLDER2 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PLACEHOLDER2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PLACEHOLDER2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PLACEHOLDER2_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PLACEHOLDER3 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PLACEHOLDER3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PLACEHOLDER3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PLACEHOLDER3_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_LANA_CLOCKGATE_CONTROL 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_BLKACTIVITY_DISABLE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_ZERO_LOWER_THREE_ZC_BITS 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_ZERO_LOWER_THREE_ZC_BITS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_ZERO_LOWER_THREE_ZC_BITS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_ZERO_LOWER_THREE_ZC_BITS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PLACEHOLDER8 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PLACEHOLDER8_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PLACEHOLDER8_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_PLACEHOLDER8_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_USE_INNER_COVG_AS_OUTER_COVG 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_DEBUG_USE_INNER_COVG_AS_OUTER_COVG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL 0x00418604 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRP0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRPA 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRPB 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRPC 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_GRPD 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_PERF_SEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG 0x00418608 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG1 0x0041860c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_FRSTR_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP 0x004186ff:0x00418680 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL 0x00418680 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRP0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRPA 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRPB 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRPC 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_GRPD 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_PERF_SEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG 0x00418684 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_PLACEHOLDER0 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_PLACEHOLDER0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_PLACEHOLDER0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_PLACEHOLDER0_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_PLACEHOLDER1 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_PLACEHOLDER1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_PLACEHOLDER1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_PLACEHOLDER1_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_PLACEHOLDER2 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_PLACEHOLDER2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_PLACEHOLDER2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_PLACEHOLDER2_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_GFXP_DISABLE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_GFXP_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_BLKACTIVITY_DISABLE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_FORCE_STIPPLE_FOR_PSAA_RATE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_FORCE_STIPPLE_FOR_PSAA_RATE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_FORCE_STIPPLE_FOR_PSAA_RATE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_FORCE_STIPPLE_FOR_PSAA_RATE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_MODS_VPRS_BYPASS_FOR_PROP_TESTING 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_MODS_VPRS_BYPASS_FOR_PROP_TESTING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_MODS_VPRS_BYPASS_FOR_PROP_TESTING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_MODS_VPRS_BYPASS_FOR_PROP_TESTING_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_DISABLE_FULLY_COVERED_OPTIMIZATION 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_DEBUG_DISABLE_FULLY_COVERED_OPTIMIZATION_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG 0x00418688 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG1 0x0041868c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG1_SLCG 4:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG1_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG1_SLCG_DISABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WIDCLIP_CG1_SLCG__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC 0x004187ff:0x00418700 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_TC_FLUSH 0x00418700 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TC_FLUSH_CRITERION 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_FLUSH_CRITERION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_FLUSH_CRITERION_END_OF_CBE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_FLUSH_CRITERION_TIMEOUT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_TIMEOUT 0x00418704 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TC_TIMEOUT_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_TIMEOUT_VALUE_INIT 0x00000080 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0 0x00418708 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_LIMIT_COALESCE_BUFFER_SIZE 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_LIMIT_COALESCE_BUFFER_SIZE_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_LIMIT_NUM_OF_TILES 14:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_LIMIT_NUM_OF_TILES_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_FORCE_CONFLICT_DETECTION_TO_VPRS 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_FORCE_CONFLICT_DETECTION_TO_VPRS_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_FORCE_CONFLICT_DETECTION_TO_VPRS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_LIMIT_CBES_ACTIVE 26:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_LIMIT_CBES_ACTIVE_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_FLUSH_ON_VPRS_CHANGE 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_FLUSH_ON_VPRS_CHANGE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_FLUSH_ON_VPRS_CHANGE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_PSI_FORCE_FLUSH_ON_CONFLICT 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_PSI_FORCE_FLUSH_ON_CONFLICT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_BLKACTIVITY_DISABLE 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_RTAI_FLUSH 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_RTAI_FLUSH_ON_OVERRIDE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG0_RTAI_FLUSH_ALWAYS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1 0x0041870c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_LIMIT_TILES_INFLIGHT 10:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_LIMIT_TILES_INFLIGHT_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_SPARE11 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_SPARE11_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_SPARE12 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_SPARE12_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_SPARE13 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_SPARE13_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_SPARE14 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_SPARE14_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_SPARE15 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_SPARE15_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_LIMIT_TRANS_INFLIGHT 28:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_LIMIT_TRANS_INFLIGHT_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_LOCAL_TIMEOUT_OVERRIDE 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_LOCAL_TIMEOUT_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_PSI_LIMIT_TILES_MIN_1 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_PSI_LIMIT_TILES_MIN_1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_PSI_DO_NOT_SPLIT_QUADS 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_DEBUG1_PSI_DO_NOT_SPLIT_QUADS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_TILE_SIZE 0x00418710 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TC_TILE_SIZE_MAX 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TC_TILE_SIZE_MAX_16X16 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TC_TILE_SIZE_MAX_16X8 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_TILE_SIZE_MAX_8X8 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL 0x00418714 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRP0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRPA 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRPB 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRPC 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRPD 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRPE 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_GRPF 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_PERF_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_PM_CTRL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TC_CG 0x00418718 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TC_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TC_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TC_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TC_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TC_CG1 0x0041871c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TC_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_CG1_SLCG 9:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TC_CG1_SLCG_ENABLED 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TC_CG1_SLCG_DISABLED 0x1ff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TC_CG1_SLCG__PROD 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB 0x004183ff:0x00418380 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS 0x00418380 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_SETUP 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_SETUP_EVICT_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_SETUP_EVICT_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_SETUP_EVICT_LAST 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_WIDREQ 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_WIDREQ_EVICT_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_WIDREQ_EVICT_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_WIDREQ_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_ZCULL 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_ZCULL_EVICT_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_ZCULL_EVICT_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_ZCULL_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_SWDX 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_SWDX_EVICT_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_SWDX_EVICT_NORMAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_LINE_CLASS_SWDX_EVICT_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL 0x00418384 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRP0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRPA 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRPB 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRPC 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_GRPD 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_PERF_SEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_CG2 0x00418388 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_CG2_SLCG 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_CG2_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_CG2_SLCG_DISABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_RASTERARB_CG2_SLCG__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP 0x0041887f:0x00418800 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG 0x00418800 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_POLY_OFFSET_NAN_IS_ZERO 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_POLY_OFFSET_NAN_IS_ZERO_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_POLY_OFFSET_NAN_IS_ZERO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_POLY_OFFSET_NAN_IS_ZERO_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_POLY_OFFSET_ZERO_X_NAN_IS_ZERO 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_POLY_OFFSET_ZERO_X_NAN_IS_ZERO_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_POLY_OFFSET_ZERO_X_NAN_IS_ZERO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_POLY_OFFSET_ZERO_X_NAN_IS_ZERO_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_DO_NOT_USE_ABS_Z_GAMUT_MAX_FOR_POFFSET 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_DO_NOT_USE_ABS_Z_GAMUT_MAX_FOR_POFFSET_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_DO_NOT_USE_ABS_Z_GAMUT_MAX_FOR_POFFSET_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_DO_NOT_USE_ABS_Z_GAMUT_MAX_FOR_POFFSET_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_Z_GAMUT_THRESHOLD 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_Z_GAMUT_THRESHOLD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_Z_GAMUT_THRESHOLD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_Z_GAMUT_THRESHOLD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LANA_CLOCKGATE_CONTROL 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LANA_CLOCKGATE_CONTROL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LANA_CLOCKGATE_CONTROL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LANA_CLOCKGATE_CONTROL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_BLKACTIVITY_DISABLE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_THRESHOLD 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_THRESHOLD_INIT 0x86 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SETUP_COMPUTES_STIPPLE_PHASE_FOR_LINES 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SETUP_COMPUTES_STIPPLE_PHASE_FOR_LINES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SETUP_COMPUTES_STIPPLE_PHASE_FOR_LINES_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SETUP_COMPUTES_STIPPLE_PHASE_FOR_LINES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SETUP_MS_POINT_BBOX_BLOAT 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SETUP_MS_POINT_BBOX_BLOAT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SETUP_MS_POINT_BBOX_BLOAT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SETUP_MS_POINT_BBOX_BLOAT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_TIGHTEN_ALIASED_TRI_BBOX 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_TIGHTEN_ALIASED_TRI_BBOX_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_TIGHTEN_ALIASED_TRI_BBOX_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_TIGHTEN_ALIASED_TRI_BBOX_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_USE_24_FRACTIONAL_BIT_STIPPLE_PHASE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_USE_24_FRACTIONAL_BIT_STIPPLE_PHASE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_USE_24_FRACTIONAL_BIT_STIPPLE_PHASE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_USE_24_FRACTIONAL_BIT_STIPPLE_PHASE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SPARE0 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SPARE0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SPARE1 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SPARE1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_CONSERVATIVE_RASTER_TIER1_ONLY 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_CONSERVATIVE_RASTER_TIER1_ONLY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_CONSERVATIVE_RASTER_TIER1_ONLY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_CONSERVATIVE_RASTER_TIER1_ONLY_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SPARE6 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SPARE6_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SETUP2PE_EARLY_THROTTLE 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SETUP2PE_EARLY_THROTTLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SETUP2PE_EARLY_THROTTLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SETUP2PE_EARLY_THROTTLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_ALIASED_LINE_BBOX_SHRINK 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_ALIASED_LINE_BBOX_SHRINK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_ALIASED_LINE_BBOX_SHRINK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_ALIASED_LINE_BBOX_SHRINK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_TRI_CORNER_CLIPPING 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_TRI_CORNER_CLIPPING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_TRI_CORNER_CLIPPING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_TRI_CORNER_CLIPPING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_NEAR_FAR_CULLING 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_NEAR_FAR_CULLING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_NEAR_FAR_CULLING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_NEAR_FAR_CULLING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SMOOTH_LINE_BBOX_SHRINK 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SMOOTH_LINE_BBOX_SHRINK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SMOOTH_LINE_BBOX_SHRINK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_SMOOTH_LINE_BBOX_SHRINK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_Z_GAMUT_OFFSET 0x00418830 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_Z_GAMUT_OFFSET_AMOUNT 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_Z_GAMUT_OFFSET_AMOUNT_INIT 0x0000001 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_Z_GAMUT_OFFSET_ZF32_AS_Z16 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_Z_GAMUT_OFFSET_ZF32_AS_Z16_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_Z_GAMUT_OFFSET_ZF32_AS_Z16_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_Z_GAMUT_OFFSET_ZF32_AS_Z16_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2 0x00418808 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_ALIASED_LINE_BBOX_EXPANSION_LEGACY 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_ALIASED_LINE_BBOX_EXPANSION_LEGACY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_ALIASED_LINE_BBOX_EXPANSION_LEGACY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_ALIASED_LINE_BBOX_EXPANSION_LEGACY_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_LATE_Z_FOR_COLOR_CLEARS 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_LATE_Z_FOR_COLOR_CLEARS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_LATE_Z_FOR_COLOR_CLEARS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_LATE_Z_FOR_COLOR_CLEARS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_TIER1_BEHAVIOR_FOR_LINES_AND_POINTS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_TIER1_BEHAVIOR_FOR_LINES_AND_POINTS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_TIER1_BEHAVIOR_FOR_LINES_AND_POINTS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_TIER1_BEHAVIOR_FOR_LINES_AND_POINTS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_TIER4_LINE_BUG_CHANGE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_TIER4_LINE_BUG_CHANGE_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_TIER4_LINE_BUG_CHANGE_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_TIER4_LINE_BUG_CHANGE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_LINE_LENGTH_ZERO_CULL_PATH 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_LINE_LENGTH_ZERO_CULL_PATH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_LINE_LENGTH_ZERO_CULL_PATH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_LINE_LENGTH_ZERO_CULL_PATH_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_FIX_NEGATIVE_ZERO_COMPARE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_FIX_NEGATIVE_ZERO_COMPARE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_FIX_NEGATIVE_ZERO_COMPARE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_FIX_NEGATIVE_ZERO_COMPARE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE6 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE6_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE7 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE7_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE8 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE8_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE9 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE9_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE10 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE10_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE11 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE11_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE12 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE12_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE13 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE13_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE14 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE14_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE15 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG2_SPARE15_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG 0x00418828 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG1 0x0041882c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x00418810 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 0x000000c /* */ #define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LIMIT0 0x00418814 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LIMIT0_SWDX2SETUP_VALUE 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LIMIT0_SWDX2SETUP_VALUE_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LIMIT0_TAG_LATENCY_VALUE 26:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LIMIT0_TAG_LATENCY_VALUE_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LIMIT1 0x00418818 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LIMIT1_RRRAM_VALUE 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LIMIT1_RRRAM_VALUE_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LIMIT1_SETUP2PE_VALUE 24:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LIMIT1_SETUP2PE_VALUE_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LIMIT1_PRIM_PTR_MSB_VALUE 31:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_DEBUG_LIMIT1_PRIM_PTR_MSB_VALUE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL 0x0041881c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRP0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRPA 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRPB 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRPC 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRPD 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRPE 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_GRPF 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY3 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY4 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY5 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_EARLY6 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE0 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE1 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE2 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE3 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE4 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE5 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_PE2SETUP_LATE6 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY0 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY1 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY2 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY3 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY4 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY5 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_EARLY6 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE0 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE1 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE2 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE3 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE4 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE5 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_SETUP2PE_LATE6 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_STATIC_PATTERN_15_5_GROUP 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_STATIC_PATTERN_0A_5_GROUP 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_PERF_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR 0x00418824 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_INTR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_INTR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_INTR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_LDCONST_OOB 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_LDCONST_OOB_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_LDCONST_OOB_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_POOLPAGE_INVALID 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_POOLPAGE_INVALID_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_POOLPAGE_INVALID_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_RESET_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_SETUP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR 0x00418bff:0x00418b00 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG 0x00418b00 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_SEARCH 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_SEARCH_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_SEARCH_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_SEARCH_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_BBOXDISC 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_BBOXDISC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_BBOXDISC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_BBOXDISC_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_BBOX2X2OPT 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_BBOX2X2OPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_BBOX2X2OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_BBOX2X2OPT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_BLKACTIVITY_DISABLE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_BLKACTIVITY_DISABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_BLKACTIVITY_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_LANA_CLOCKGATE_CONTROL 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_GFXP_SYNC_DISABLE 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_GFXP_SYNC_DISABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_INNER_COVG 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_INNER_COVG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_INNER_COVG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_INNER_COVG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_POINTS 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_POINTS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_LINES 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_LINES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_TRIS 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_TRIS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_FULLY_COVERED_OPTIMIZATION 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_FULLY_COVERED_OPTIMIZATION_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_VPRS_CACHE 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_VPRS_CACHE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_SEARCH_UPDATES 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_SEARCH_UPDATES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_INDEPENDENT_ENGINES 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_DISABLE_INDEPENDENT_ENGINES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_SAVED 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_DEBUG_SAVED_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL 0x00418b04 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRP0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRPA 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRPB 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRPC 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_GRPD 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_PERF_SEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP(i) (0x00418b08+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP__SIZE_1 43 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP_TILE0 4:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP_TILE0_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP_TILE1 9:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP_TILE1_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP_TILE2 14:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP_TILE2_INIT 0x02 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP_TILE3 19:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP_TILE3_INIT 0x03 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP_TILE4 24:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP_TILE4_INIT 0x04 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP_TILE5 29:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP_TILE5_INIT 0x05 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x00418bb8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET_INIT 0x03 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG 0x00418bbc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG1 0x00418bc0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_HEAVY_BUNDLE_ADDITIONS 0x00418bf0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_CRSTR_HEAVY_BUNDLE_ADDITIONS_ADDRESS_0 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_HEAVY_BUNDLE_ADDITIONS_ADDRESS_0_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_CRSTR_HEAVY_BUNDLE_ADDITIONS_ADDRESS_1 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_CRSTR_HEAVY_BUNDLE_ADDITIONS_ADDRESS_1_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD 0x00418c7f:0x00418c00 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS 0x00418c00 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_MODE_ALPHA 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_MODE_ALPHA_UNPARTITIONED 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_MODE_ALPHA_MIXED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_MODE_BETA 4:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_MODE_BETA_UNPARTITIONED 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_MODE_BETA_MIXED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_ALPHA_FSM 10:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_ALPHA_FSM_WTB 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_ALPHA_FSM_SB 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_ALPHA_FSM_WFP 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_ALPHA_FSM_WFC 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_ALPHA_FSM_SWTB 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_ALPHA_PRIMID_EN 12:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_BETA_FSM 18:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_BETA_FSM_READY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_BETA_FSM_SENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_BETA_FSM_COMPLEX 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_BETA_FSM_NUM_THREADS 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_BETA_FSM_SWTB 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_BETA_FORWARD_BETA 20:20 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS_BETA_SPM_ID 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS2 0x00418c08 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_STATUS2_BATCH_INTERLOCK_COUNT 13:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM 0x00418c04 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP64 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP65 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP66 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP67 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP68 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP69 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP70 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_STATIC_PATTERN_AA_8_GROUP 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_STATIC_PATTERN_55_8_GROUP 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_SELECT_GRP_MAX 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_SM_ID(i) (0x00418c10+(i)*4) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_SM_ID__SIZE_1 8 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_SM_ID_ID 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_SM_ID_ID_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PES_TPC_ID_MASK(i) (0x00418c30+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PES_TPC_ID_MASK__SIZE_1 3 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_LIVE_PHYSICAL_PES 0x00418c50 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_LIVE_PHYSICAL_PES_MASK 3:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x00418c6c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_GPMPD2PEL_ARB 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_GPMPD2PEL_ARB_AUTO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_GPMPD2PEL_ARB_ROUND_ROBIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_GPMPD2PEL_ARB_ALPHA 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_GPMPD2PEL_ARB_BETA 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_GPMPD2PEL_ARB_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_PD2GPM_SLICE_REDUCE 8:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_PD2GPM_SLICE_REDUCE_FULLSIZE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_PD2GPM_SLICE_REDUCE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_LOAD_BALANCE_LAST_TPC_SELECTION 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_LOAD_BALANCE_LAST_TPC_SELECTION_NO_ACTION 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_LOAD_BALANCE_LAST_TPC_SELECTION_EXCLUDE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_LOAD_BALANCE_LAST_TPC_SELECTION_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM_ROUND_ROBIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM_LOAD_BALANCED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM_ROUND_ROBIN_PES 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_HONOR_PD_DISTRIBUTION 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_HONOR_PD_DISTRIBUTION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_HONOR_PD_DISTRIBUTION_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_HONOR_PD_DISTRIBUTION_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL_AUTO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL_OFF 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL_ON 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL 20:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_NO_XTRA_SPACE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_BLOCK_ON_SPACE_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_BLOCK_ON_DRAIN_AND_SPACE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_BLOCK_UNTIL_DRAINS_ACKED 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_NO_BLOCK 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_STRICT_ALPHA_BETA_INTERLOCK 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_STRICT_ALPHA_BETA_INTERLOCK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_STRICT_ALPHA_BETA_INTERLOCK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_STRICT_ALPHA_BETA_INTERLOCK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_DISABLE_INTERLOCK 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_DISABLE_INTERLOCK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_DISABLE_INTERLOCK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_DISABLE_INTERLOCK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_BLOCK_ALPHA_WORK_IN_UNPARTITIONED_TO_ALPHA_TRANSITION 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_BLOCK_ALPHA_WORK_IN_UNPARTITIONED_TO_ALPHA_TRANSITION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_BLOCK_ALPHA_WORK_IN_UNPARTITIONED_TO_ALPHA_TRANSITION_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_BLOCK_ALPHA_WORK_IN_UNPARTITIONED_TO_ALPHA_TRANSITION_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_DISABLE_RTV_PREFETCH 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_DISABLE_RTV_PREFETCH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_DISABLE_RTV_PREFETCH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_DISABLE_RTV_PREFETCH_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_DISABLE_INSTRUCTION_PREFETCH 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_RESERVED 31:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_RESERVED_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG 0x00418c70 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG1 0x00418c74 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_PD_CG1_SLCG__PROD 0x7fffffc0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD 0x00418cff:0x00418c80 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG 0x00418c80 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DIST_3D 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DIST_3D_LOAD_BASED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DIST_3D_ROUND_ROBIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DIST_3D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DIST_2D 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DIST_2D_LOAD_BASED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DIST_2D_ROUND_ROBIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DIST_2D_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_RESERVED0 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_RESERVED0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DISABLE_INSTRUCTION_PREFETCH 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DETERMINISTIC_DIST 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DETERMINISTIC_DIST_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DETERMINISTIC_DIST_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DETERMINISTIC_DIST_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_RESERVED1 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_RESERVED1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_FORCE_TICKET_ZERO 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_FORCE_TICKET_ZERO_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_FORCE_TICKET_ZERO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_FORCE_TICKET_ZERO_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_PROP2X_ALLOW_SAME_TPC 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_PROP2X_ALLOW_SAME_TPC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_PROP2X_ALLOW_SAME_TPC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_PROP2X_ALLOW_SAME_TPC_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_RESERVED2 15:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_RESERVED2_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DIST_THRESHOLD_3D 21:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DIST_THRESHOLD_3D_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_RESERVED3 23:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_RESERVED3_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DIST_THRESHOLD_2D 29:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DIST_THRESHOLD_2D_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DRAIN_GFX_TPC_TWO_PHASE 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DRAIN_GFX_TPC_TWO_PHASE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_DRAIN_GFX_TPC_TWO_PHASE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_RESERVED4 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CONFIG_RESERVED4_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS 0x00418c84 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_LOAD 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM 0x00418c88 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_STATIC_PATTERN_2A_6_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_STATIC_PATTERN_15_6_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_SELECT_MAX 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_COLL 0x00418c90 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_COLL_COLL 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_DIST 0x00418c94 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_DIST_DIST 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_DIST_SOF 6:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_IN 0x00418c98 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_IN_COLL 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_IN_DIST 6:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_IN_PROP2GPM_SUBTL 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_IN_GPMPD2GPMSD_COMPUTE 18:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_OUT 0x00418c9c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_OUT_GPM2GCC_PIX 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_OUT_GPM2PROP_SUBTL 6:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_OUT_GPM2PROP_PIXOUT0 10:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_OUT_GPM2PROP_PIXOUT1 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_OUT_GPM2MPC_PIX 22:20 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_TPC(i) (0x00418ca0+(i)*4) /* R--4A */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_TPC__SIZE_1 6 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_TPC_MPC2GPM_SUBTL 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_STATUS_TPC_SMM2GPM_PIXOUT 6:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG 0x00418cf0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG1 0x00418cf4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_SD_CG1_SLCG__PROD 0x7ffffff8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT 0x00418d7f:0x00418d00 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM 0x00418d00 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_SELECT_MAX 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_ALPHA_WRITE_POINTERS 0x00418d04 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_ALPHA_WRITE_POINTERS_P0 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_ALPHA_WRITE_POINTERS_P1 6:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_ALPHA_WRITE_POINTERS_P2 10:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_ALPHA_WRITE_POINTERS_P3 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_ALPHA_WRITE_POINTERS_P4 18:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_ALPHA_WRITE_POINTERS_P5 22:20 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_ALPHA_WRITE_POINTERS_P6 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_ALPHA_WRITE_POINTERS_P7 30:28 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_BETA_WRITE_POINTERS 0x00418d08 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_BETA_WRITE_POINTERS_P0 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_BETA_WRITE_POINTERS_P1 6:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_BETA_WRITE_POINTERS_P2 10:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_BETA_WRITE_POINTERS_P3 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_BETA_WRITE_POINTERS_P4 18:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_BETA_WRITE_POINTERS_P5 22:20 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_BETA_WRITE_POINTERS_P6 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_BETA_WRITE_POINTERS_P7 30:28 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CONFIG 0x00418d0c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CONFIG_RESERVED 31:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CONFIG_RESERVED_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_SCOREBOARD_0 0x00418d10 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_SCOREBOARD_0_S0 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_SCOREBOARD_0_S1 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_SCOREBOARD_1 0x00418d14 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_SCOREBOARD_1_S2 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_SCOREBOARD_1_S3 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_SCOREBOARD_2 0x00418d18 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_SCOREBOARD_2_S4 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_SCOREBOARD_2_S5 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_SCOREBOARD_3 0x00418d1c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_SCOREBOARD_3_S6 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_SCOREBOARD_3_S7 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_STATUS 0x00418d20 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_STATUS_READ_POINTER 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_STATUS_FULL_FLAGS 23:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_STATUS_EMPTY_FLAGS 31:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG 0x00418d70 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG1 0x00418d74 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GPM_RPT_CG1_SLCG__PROD 0x7ffffff0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS 0x00418fff:0x00418f00 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG 0x00418f00 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG_ALPHA_NEXTSM_REDUCE_DIV16 4:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG_ALPHA_NEXTSM_REDUCE_DIV16_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG_ALPHA_NEXTSM_REDUCE_DIV16_FULLSIZE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG_BETA_NEXTSM_REDUCE_DIV16 9:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG_BETA_NEXTSM_REDUCE_DIV16_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG_BETA_NEXTSM_REDUCE_DIV16_FULLSIZE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG_TWO_PRIM_XBAR_MESSAGE 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG_TWO_PRIM_XBAR_MESSAGE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG_TWO_PRIM_XBAR_MESSAGE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG_TWO_PRIM_XBAR_MESSAGE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG_RESERVED 15:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CONFIG_RESERVED_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM 0x00418f08 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_STATIC_PATTERN_2A_7_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_STATIC_PATTERN_55_7_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_SELECT_MAX 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG 0x00418f0c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG1 0x00418f10 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_WDXPS_CG1_SLCG__PROD 0x7ffffff0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC 0x004193ff:0x00419000 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x00419000 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_L15 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_L15_ENABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_L15_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 /* -WIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE_TASK_INIT 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_WORLD_INSTR 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_WORLD_INSTR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_WORLD_INSTR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_WORLD_INSTR_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_NUM_WAYS_DISABLED 5:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_NUM_WAYS_DISABLED_0 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CONSTANTS_IN_PAGEPOOL_CHANNEL 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CONSTANTS_IN_PAGEPOOL_CHANNEL_NONBLOCKING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CONSTANTS_IN_PAGEPOOL_CHANNEL_BLOCKING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CONSTANTS_NOT_IN_PAGEPOOL_CHANNEL 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CONSTANTS_NOT_IN_PAGEPOOL_CHANNEL_NONBLOCKING 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CONSTANTS_NOT_IN_PAGEPOOL_CHANNEL_BLOCKING 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_VA_CONSTANTS_CHANNEL 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_VA_CONSTANTS_CHANNEL_NONBLOCKING 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_VA_CONSTANTS_CHANNEL_BLOCKING 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_INSTRUCTIONS_CHANNEL 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_INSTRUCTIONS_CHANNEL_NONBLOCKING 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_INSTRUCTIONS_CHANNEL_BLOCKING 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_TSL2_CHANNEL 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_TSL2_CHANNEL_NONBLOCKING 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_TSL2_CHANNEL_BLOCKING 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_ARB_DISABLE_HIT0 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_ARB_DISABLE_HIT0_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_ARB_DISABLE_HIT0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_ARB_DISABLE_HIT1 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_ARB_DISABLE_HIT1_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_ARB_DISABLE_HIT1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_ARB_DISABLE_MISS 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_ARB_DISABLE_MISS_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_ARB_DISABLE_MISS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_API 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_API_DX 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_API_OGL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CONSTANTS_IN_RTV_CHANNEL 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CONSTANTS_IN_RTV_CHANNEL_NONBLOCKING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CONSTANTS_IN_RTV_CHANNEL_BLOCKING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_SCREEN_INSTR 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_SCREEN_INSTR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_SCREEN_INSTR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_SCREEN_INSTR_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_WORLD_RTV 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_WORLD_RTV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_WORLD_RTV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_WORLD_RTV_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_PREFETCH_MAX_COUNT_PER_SET 22:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_PREFETCH_MAX_COUNT_PER_SET_INIT 0x4 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_PREFETCH_MAX_TOTAL 28:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_PREFETCH_MAX_TOTAL_INIT 0x20 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CYA_CONST_CL_FETCH 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CYA_CONST_CL_FETCH_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CYA_CONST_CL_FETCH_FULL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CYA_CONST_CL_FETCH_PARTIAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CYA_INVALIDATE_ALL 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CYA_INVALIDATE_ALL_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_CYA_INVALIDATE_ALL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_SCREEN_RTV 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_SCREEN_RTV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_SCREEN_RTV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_GFX_PREFETCH_SCREEN_RTV_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_3 0x00419014 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_3_PREFETCH_ENABLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_3_PREFETCH_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_3_PREFETCH_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_3_PREFETCH_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_3_PREFETCH_OFFSET 3:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_3_PREFETCH_OFFSET_256B 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_3_PREFETCH_OFFSET_768B 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_3_PREFETCH_OFFSET_1792B 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_3_PREFETCH_OFFSET_2816B 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_3_PREFETCH_OFFSET_3840B 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_3_PREFETCH_OFFSET_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x00419004 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_RM_RTV_CB_BASE 0x00419034 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GCC_RM_RTV_CB_BASE_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_RM_RTV_CB_BASE_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x00419008 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 9:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON 0x0041900c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_OUTPUT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_HITMISS2 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_HITMISS3 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_HITMISS4 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_HITMISS5 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_HITMISS6 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_STATIC_PATTERN_25_6_GROUP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_STATIC_PATTERN_1A_6_GROUP 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_LATENCY 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_MISC1 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_MISC2 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_SM2GCC_INP_REQ 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_OUTSTANDING_MISS_TO_RETURN 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_OUTSTANDING_INSTR_REQ 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_OUTSTANDING_CONST_REQ 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_OUTSTANDING_TEX_REQ 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_GPM2GCC_PIX 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_PIPE_STALL1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_PIPE_STALL2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_OCCUPANCY_MISS_BUFFER 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_INSTR_PREFETCH 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_TEX_INVAL_BUNDLES 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_QMD_PREFETCH 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_L15_HITMISS1 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_L15_HITMISS2 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_L15_HITMISS3 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_L15_HITMISS4 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_L15_GNIC_REQ 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_GCC_PREFETCH 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_PPCAM_HITMISS 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_IN_OUT_REQS 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_INVAL_REQS 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_QMD_CONST_PREFETCH 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_GFX_INST_PREFETCH 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_GFX_CONST_PREFETCH_0 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_GFX_CONST_PREFETCH_1 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_GFX_CONST_PREFETCH_2 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_SELECT_GFX_CONST_PREFETCH_3 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_PERFMON_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR 0x00419028 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR_ECC_CORRECTED 0:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR_ECC_CORRECTED_NOT_PENDING 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR_ECC_CORRECTED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR_ECC_UNCORRECTED 1:1 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR_ECC_UNCORRECTED_NOT_PENDING 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR_ECC_UNCORRECTED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG 0x00419020 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_CG1 0x00419024 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GCC_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_CG1_SLCG__PROD 0xff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK 0x00419040 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CONTROL 0x00419044 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CONTROL__PRIV_LEVEL_MASK 0x00419040 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CONTROL_INJECT_CORRECTED_ERR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CONTROL_INJECT_UNCORRECTED_ERR 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS 0x00419048 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK1_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK1_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK0 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK1 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK1_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK1_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_RESET_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CORRECTED_ERR_COUNT 0x0041904c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_UNCORRECTED_ERR_COUNT 0x00419054 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_ADDRESS 0x00419058 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_GCC_L15_ECC_ADDRESS_INDEX 16:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK 0x00419060 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "gcc_dbg" /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2 0x0041905c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2__PRIV_LEVEL_MASK 0x00419060 /* */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_SPARE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_GCC_DBG_2_SPARE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPC0 0x0041c000 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_TPC0_SM_CONFIG 0x0041c608 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPC1 0x0041c800 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_TPC1_SM_CONFIG 0x0041ce08 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPC2 0x0041d000 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_TPC2_SM_CONFIG 0x0041d608 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPC3 0x0041d800 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_TPC3_SM_CONFIG 0x0041de08 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPC4 0x0041e000 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_TPC4_SM_CONFIG 0x0041e608 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPC5 0x0041e800 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_TPC5_SM_CONFIG 0x0041ee08 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS 0x00419800 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SELECT 0x00419d20 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SELECT_INDEX 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SELECT_INDEX_LANE0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SELECT_INDEX_LANE1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SELECT_INDEX_ALL 0x3f /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SELECT_AUTO_INCREMENT 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SELECT_AUTO_INCREMENT_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SELECT_AUTO_INCREMENT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANES 0x00419d30 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANES_NUM_CHAINS 5:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN 0x00419d34 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE0_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE0_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE1_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE1_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE2_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE2_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE3_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE3_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE4 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE4_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE4_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE5_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE5_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE6_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE6_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE7_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE7_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE8 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE8_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE8_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE9 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE9_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE9_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE10 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE10_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE10_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE11 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE11_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE11_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE12 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE12_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE12_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE13 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE13_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE13_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE14 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE14_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE14_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE15 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE15_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE15_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE16 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE16_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE16_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE17 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE17_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RUN_LANE17_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS 0x00419d38 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE0 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE0_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE0_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE1 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE1_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE1_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE2 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE2_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE2_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE3 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE3_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE3_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE4 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE4_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE4_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE5 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE5_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE5_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE6 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE6_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE6_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE7 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE7_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE7_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE8 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE8_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE8_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE9 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE9_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE9_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE10 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE10_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE10_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE11 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE11_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE11_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE12 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE12_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE12_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE13 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE13_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE13_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE14 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE14_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE14_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE15 15:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE15_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE15_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE16 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE16_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE16_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE17 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE17_IDLE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_STATUS_LANE17_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK 0x00419dd0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_FUSE0 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_IFF_GPCCS_FECS_GSP_SEC2_FUSE1 0x8007c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CONTROL 0x00419d84 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CONTROL__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CONTROL_COMPRESSION 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CONTROL_COMPRESSION_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CONTROL_COMPRESSION_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CONTROL_BLOAT_BUDGET 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CONTROL_BLOAT_BUDGET_0 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CONTROL_COMPRESSION_SETTINGS 27:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CONTROL_COMPRESSION_SETTINGS__0 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SAVE_OFFSET 0x00419d88 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SAVE_OFFSET__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SAVE_OFFSET_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SAVE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RESTORE_OFFSET 0x00419d8c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RESTORE_OFFSET__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RESTORE_OFFSET_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RESTORE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CURRENT_OFFSET 0x00419dac /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CURRENT_OFFSET_V 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CURRENT_OFFSET_V_0 0x00000000 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CURRENT_SUBOFFSET 0x00419db0 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CURRENT_SUBOFFSET_V 5:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CURRENT_SUBOFFSET_V_0 0x00 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SIZE 0x00419d90 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SIZE__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SIZE_V 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SIZE_V_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_PREFETCH_OFFSET 0x00419d94 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_PREFETCH_OFFSET__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_PREFETCH_OFFSET_V 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_PREFETCH_OFFSET_V_10 0x0a /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SAVED_WORDS 0x00419db4 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SAVED_WORDS__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SAVED_WORDS_V 23:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SAVED_WORDS_V_0 0x000000 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RESTORE_WORDS 0x00419db8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RESTORE_WORDS__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RESTORE_WORDS_V 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_RESTORE_WORDS_V_0 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_DATA 0x00419d98 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_DATA__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_DATA_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_DATA_V_0 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_LOC 0x00419d9c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_LOC__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_LOC_RAMID 9:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_LOC_RAMID_V 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_LOC_OFFSET 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_LOC_OFFSET_V 0x000f /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_CFG 0x00419da0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_CFG__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_CFG_DELAY 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_CFG_DELAY_V 0x41 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_CFG_CREDITS 21:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_CFG_CREDITS_V 0x3f /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_CFG_AUTOSEEK 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_CFG_AUTOSEEK_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_CFG_AUTOSEEK_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_RCCLASS 0x00419dbc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_RCCLASS__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_RCCLASS_V 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_RCCLASS_V_3 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_RCCLASS_V_WFI 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_RCCLASS_V_GFXP 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS 0x00419da4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD 4:0 /* RW-VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_IDLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SEEK 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_DISCOVER_LENGTH 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SAVE 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RESTORE 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_LOAD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_READ_POP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_WRITE_PUSH 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_ENABLE 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_DISABLE 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_ENABLE 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_DISABLE 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_ENABLE 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_DISABLE 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_OVERRIDE 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_FLUSH 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SUSPEND 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_CURRENT 9:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_CURRENT_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_STATUS_CURRENT_BUSY 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC 0x00419da8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_IDLE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_SEEK 0x01 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_DISCOVER_LENGTH 0x02 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_SAVE 0x03 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_RESTORE 0x04 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_LOAD 0x05 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_READ_POP 0x06 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_WRITE_PUSH 0x07 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_RAMID_ENABLE 0x08 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_RAMID_DISABLE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_ENABLE 0x0a /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_DISABLE 0x0b /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_CHAIN_ENABLE 0x0c /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_CHAIN_DISABLE 0x0d /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_OVERRIDE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_FLUSH 0x0f /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_SUSPEND 0x10 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CMD_EXEC_CMD_SCRUB 0x11 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_COMPUTED_CHECKSUM 0x00419dc4 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_COMPUTED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SAVED_CHECKSUM 0x00419dc8 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SAVED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CHECKSUM 0x00419dcc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CHECKSUM__PRIV_LEVEL_MASK 0x00419dd0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CHECKSUM_CTRL_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CHECKSUM_CTRL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CHECKSUM_STATUS_MATCH 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_RC_LANE_CHECKSUM_STATUS_MISMATCH 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_CG1 0x00419d24 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_CG1_SLCG 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_LANE_CTL 0x00419d40 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES_V 0x8 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_LANE_CTL_WRR_WEIGHT 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_LANE_CTL_WRR_WEIGHT_V 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_BASE_ADDR 0x00419d44 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_BASE_ADDR_F 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_BASE_ADDR_F_V 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_HI_BASE_ADDR 0x00419d78 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_HI_BASE_ADDR_F 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_HI_BASE_ADDR_F_V 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_ENGINE_CTL 0x00419d7c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_ENGINE_CTL_ENGINE_ID 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_ENGINE_CTL_ENGINE_ID_VEID0 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_ENGINE_CTL_ENGINE_ID_BAR2_FN0 0xc0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_ENGINE_CTL_VEID 21:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_ENGINE_CTL_VEID_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_ENGINE_CTL_GFID 29:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_ENGINE_CTL_GFID_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK 0x00419d68 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD 0x00419d50 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD__PRIV_LEVEL_MASK 0x00419d68 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_IDLE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_FB_OP_FLUSH 0x05 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_FB_OP_SOFT_FLUSH 0x06 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_FB_OP_BIND_INST_BLK_PTR 0x07 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_FB_OP_MMU_TLB_INVALIDATE 0x09 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_PREFETCH 0x0a /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_FB_OP_PHYSICAL_L2_CACHE_MGMT 0x0b /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_CACHE_MGMT 0x0c /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_FB_OP_L2_PEER_INVALIDATE 0x0d /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_FB_OP_L2_SYSMEM_INVALIDATE 0x0e /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_CLEAN_COMPTAGS 0x0f /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_FLUSH_DIRTY 0x10 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_CMD_MEMBAR 0x01 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_SUB_OP 8:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_SUB_OP_INVALIDATE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_SUB_OP_CLEAN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_SUB_OP_DEMOTE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_ACK 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_ACK_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_ACK_FLUSH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_ACK_TLB 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_ACK_MEM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_ACK_NONE_REQUIRED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_ACK_GLOBALLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_ACK_INTRANODE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_HALT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_HALT_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_HALT_REQUEST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_UNHALT 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_UNHALT_V 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CTX_CMD_UNHALT_REQUEST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_L2_EVICTION_CTL 0x00419d54 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_L2_EVICTION_CTL_WR 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_L2_EVICTION_CTL_WR_FIRST 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_L2_EVICTION_CTL_WR_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_L2_EVICTION_CTL_WR_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_L2_EVICTION_CTL_RD 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_L2_EVICTION_CTL_RD_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_L2_EVICTION_CTL_RD_NORMAL 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_L2_EVICTION_CTL_RD_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_PRIV 0x00419d58 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_PRIV_OVERRIDE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_PRIV_OVERRIDE_PRIV 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_PRIV_OVERRIDE_NONPRIV 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS 0x00419d5c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_CLEAR 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_CLEAR_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_CLEAR_CLEAR 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_ACK 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_ACK_OK 0x1 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_ACK_NACK 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_SUBID 15:2 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_OUTSTANDING_TRANSACTIONS 23:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_BUFFER_NOT_EMPTY 24:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_FLUSH_WHEN_BUSY 28:28 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_FLUSH_WHEN_BUSY_DEFAULT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_FLUSH_WHEN_BUSY_ERROR 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_HALTED 30:30 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_STATUS_BUSY 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CMD_OVERRIDE 0x00419d60 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CMD_OVERRIDE_CMD 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CMD_OVERRIDE_CMD_VIRTUAL 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_VID_MEM 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_NONCOHERENT 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_COHERENT 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CMD_OVERRIDE_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CMD_OVERRIDE_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_CMD_OVERRIDE_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR 0x00419d6c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR__PRIV_LEVEL_MASK 0x00419d68 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_RC_ID 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_RC_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_RC_SECURE_LEVEL 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_RC_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PVS_ID 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PVS_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PVS_SECURE_LEVEL 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_PVS_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_CMD_ID 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_CMD_ID_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_CMD_SECURE_LEVEL 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_CMD_SECURE_LEVEL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_BLOCKED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_ALLOWED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK 0x00419d70 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG 0x00419d74 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG__PRIV_LEVEL_MASK 0x00419d70 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T0 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T1 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T2 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T3 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T4 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T5 23:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T6 27:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T7 31:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_ARB_FALCON_REGIONCFG_T7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x00419d00 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_PE 2:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_PE_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_PE_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_PE_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_PE_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_PE_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_PE_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_PE_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_PE_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_MPC 5:3 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_MPC_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_MPC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_MPC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_MPC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_MPC_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_MPC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_MPC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_MPC_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_SM 8:6 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_SM_EMPTY 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_SM_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_SM_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_SM_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_SM_PREEMPTED 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_SM_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_SM_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0_SM_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION 0x00419d08 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_SM 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_SM_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_SM_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_PE 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_PE_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_PE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_MPC 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_MPC_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_MPC_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x00419d0c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN_SM 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN_SM_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN_SM_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN_PE 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN_PE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN_PE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN_MPC 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN_MPC_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN_MPC_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_DEBUG 0x00419d10 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_DEBUG_STATUS_FILTER 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_DEBUG_STATUS_FILTER_INIT 0x14 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_DEBUG_STATUS_FILTER_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00419900 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLKCG_CG 0x00419804 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLKCG_CG__PRIV_LEVEL_MASK 0x00419900 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLKCG_CG_BLKACTIVITY_ENABLE 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLKCG_CG_BLKACTIVITY_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLKCG_CG_BLKACTIVITY_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLKCG_CG_BLKACTIVITY_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLKCG_CG_BLKACTIVITY_ERR 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLKCG_CG_BLKACTIVITY_ERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLKCG_CG_BLKACTIVITY_ERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLKCG_CG_BLKACTIVITY_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG 0x00419810 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_DEBUG_SPARE_3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x0041980c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_PHASE_ARB_DETERM 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_PHASE_ARB_DETERM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_PHASE_ARB_DETERM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_PHASE_ARB_DETERM_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_CACHE_INVAL_METHOD_EN 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_CACHE_INVAL_METHOD_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_CACHE_INVAL_METHOD_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_CACHE_INVAL_METHOD_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_DEBUG_SPARE_2 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_DEBUG_SPARE_2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_DEBUG_SPARE_2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_DEBUG_SPARE_2_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_INVAL_DISABLE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_INVAL_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_INVAL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_INVAL_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_CPI_FORCE_PER_TASK_CACHE_INVAL 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_CPI_FORCE_PER_TASK_CACHE_INVAL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_CPI_FORCE_PER_TASK_CACHE_INVAL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_CPI_FORCE_PER_TASK_CACHE_INVAL_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_WRACK_DISABLE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_WRACK_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_WRACK_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_WRACK_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_CPI_VC_IN_CPO_OPT_MODE 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_CPI_VC_IN_CPO_OPT_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_CPI_VC_IN_CPO_OPT_MODE_IS_BLOCKING 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_CPI_VC_IN_CPO_OPT_MODE_IS_NON_BLOCKING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_XBAR_PORT_ID 0x00419844 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_XBAR_PORT_ID_VALUE 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_XBAR_PORT_ID_VALUE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW 0x00419838 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW_READ_PACKING 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW_READ_PACKING_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW_READ_PACKING_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW_READ_PACKING_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW_WRITE_PACKING 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW_WRITE_PACKING_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW_WRITE_PACKING_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW_WRITE_PACKING_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW_READ_CMD_HOLDOFF 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW_READ_CMD_HOLDOFF_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW_ACACHE_READ_CMD_HOLDOFF 7:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_MIW_ACACHE_READ_CMD_HOLDOFF_INIT 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE 0x0041984c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_VAF_LINES 11:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_STRI_LINES 23:12 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_GPULL_LINES 24:24 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_CACHE_DISABLE 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_CACHE_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_CACHE_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_CACHE_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_VAF_INVAL_DISABLE 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_VAF_INVAL_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_VAF_INVAL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_VAF_INVAL_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_STRI_INVAL_DISABLE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_STRI_INVAL_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_STRI_INVAL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_ACACHE_STRI_INVAL_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI 0x00419850 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI_LRU_DISABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI_LRU_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI_LRU_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI_LRU_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI_INVAL_DISABLE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI_INVAL_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI_INVAL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI_INVAL_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI_LRU_KEEP_HIST_ENABLE 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI_LRU_KEEP_HIST_ENABLE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI_LRU_KEEP_HIST_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STRI_LRU_KEEP_HIST_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM 0x00419854 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STATUS 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STATUS_ACACHE 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STATUS_PIF 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STATUS_PIN 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STATUS_STRI 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STATUS_TG 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STATUS_VAF 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STATUS_VSC 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CG_STATUS_ACACHE 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CG_STATUS_PIF 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CG_STATUS_PIN 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CG_STATUS_STRI 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CG_STATUS_TG 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CG_STATUS_VAF 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CG_STATUS_VSC 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CG_STATUS 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_BLK_ACTIVITY 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_WAKEUP 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_ACACHE_GRP_0 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_ACACHE_GRP_1 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_ACACHE_GRP_2 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_ACACHE_GRP_3 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_ACACHE_GRP_4 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CPO_GRP_0 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CPO_GRP_1 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_PIF_GRP_0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_PIF_GRP_1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_PIF_GRP_2 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_PIN_GRP_0 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_PIN_GRP_1 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_SSYNC_GRP_0 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STREAM_GRP_0 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STREAM_GRP_1 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STREAM_GRP_2 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STREAM_GRP_3 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STRI_GRP_0 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_0 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_1 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_2 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_3 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_4 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_5 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_6 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_7 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_8 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_9 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_10 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_11 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_12 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_TG_GRP_13 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_0 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_1 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_2 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_3 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_4 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_5 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_6 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_7 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_8 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VPC_GRP_0 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VPC_GRP_1 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VPC_GRP_2 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VPC_GRP_3 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VPC_GRP_4 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VPC_GRP_5 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VPC_GRP_6 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VPC_GRP_7 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VPC_GRP_8 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_PVLDRDY1 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_PVLDRDY2 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_PVLDRDY3 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_PVLDRDY4 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VALID1 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VALID2 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VALID3 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_PVLDRDY5 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_PVLDRDY6 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VPC_GRP_9 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VPC_GRP_10 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VPC_GRP_11 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_PG_STATUS 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STRI_GRP_1 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_9 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_11 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_12 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_14 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_15 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_16 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_17 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_18 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_19 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_20 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_VAF_GRP_22 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STRI_GRP_2 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_BA_GRP_1 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STATIC_PATTERN_AAA_12_GROUP 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_STATIC_PATTERN_555_12_GROUP 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_SINGLE_PASS_GRP_1 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_GPCID_PEID_GROUP 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CTL_EN 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CTL_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CTL_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PM_SELECT_CTL_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CACHE_INVALIDATE 0x00419858 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CACHE_INVALIDATE_ENABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CACHE_INVALIDATE_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CACHE_INVALIDATE_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CACHE_INVALIDATE_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS 0x00419860 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_PE 2:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_PE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_PIF 5:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_PIF_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_PIN 8:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_PIN_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_VAF 11:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_VAF_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_ACACHE 14:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_ACACHE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_STRI 17:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_STRI_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_TGA 20:18 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_TGA_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_GSPILL 23:21 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_GSPILL_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_GPULL 26:24 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_GPULL_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_VSC 29:27 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_STATUS_VSC_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x00419848 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY 0x00419864 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_CPI 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_CPI_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_CPI_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_CPI_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_CPI_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_STRI 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_STRI_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_STRI_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_STRI_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_STRI_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_VPC 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_VPC_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_VPC_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_VPC_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_VPC_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_STREAM 11:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_STREAM_FIRST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_STREAM_NORMAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_STREAM_LAST 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_L2_EVICT_POLICY_STREAM_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG 0x00419868 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG1 0x0041986c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG1_SLCG 23:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG1_SLCG_ENABLED 0x000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG1_SLCG_DISABLED 0x7fffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_CG1_SLCG__PROD 0x000082 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR 0x00419884 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_PIF_ERR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_PIF_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_PIF_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_PIN_ERR 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_PIN_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_PIN_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_VAF_ERR 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_VAF_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_VAF_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_ACACHE_ERR 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_ACACHE_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_ACACHE_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_STRI_ERR 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_STRI_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_STRI_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_TG_ERR 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_TG_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_TG_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_GSPILL_ERR 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_GSPILL_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_GSPILL_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_GPULL_ERR 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_GPULL_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_GPULL_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_VSC_ERR 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_VSC_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_VSC_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_RESET_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_RESET_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_HWW_ESR_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_A 0x00419894 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_A__PRIV_LEVEL_MASK 0x00419900 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_A_1 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_A_1_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_A_2 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_A_2_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_A_3 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_A_3_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_B 0x00419898 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_B__PRIV_LEVEL_MASK 0x00419900 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_B_4 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_B_4_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_B_5 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_B_5_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_B_6 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_B_6_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_C 0x0041989c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_C__PRIV_LEVEL_MASK 0x00419900 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_C_7 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_C_7_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_C_8 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_C_8_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_C_9 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_PE_BLK_ACTIVITY_WEIGHTS_C_9_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00419b00 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL 0x00419b04 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_STATUS 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_ACTIVE_WARPS 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_ACTIVE_WARPS2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_RFA_WARP_CANT_DRAIN_OUT_OF_ORDER 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_RFA_WARP_CANT_DRAIN 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_ICC 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_ACTIVE_CTAS 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_TRAP 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_SHADER_PROGRAM 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_SFE_DEBUG0 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_PROFILER 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_STATIC_PATTERN0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_STATIC_PATTERN1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_SIGDUMP_DEBUG 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG_ACTIVE_WARPS_FULL 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG_ACTIVE_WARPS_PS_FULL 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG_ACTIVE_WARPS_VTG_FULL 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_CILP_DEBUG 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG1 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG2 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG3 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG4 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG5 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG6 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG7 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG8 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG9 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_DEBUG10 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_SINGLE_PASS0 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_SINGLE_PASS1 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_SINGLE_PASS2 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_SINGLE_PASS3 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_FULL0 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_NMEAS 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_SINGLE_PASS4 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_SINGLE_PASS5 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_APM_GROUP_5 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_APM_GROUP_4 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_APM_GROUP_3 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_APM_GROUP_2 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_APM_GROUP_1 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_APM_GROUP_0 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_ENABLE 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_CORE_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL 14:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_STATUS_ACTIVITY 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_STATUS_ACTIVITY1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_ACTIVE_WARPS 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_INST_ISSUE_EXECUTED_IPC 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_REGISTER_BANK_UTIL 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_1 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_2 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_3 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_4 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_5 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_6 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_7 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_USCH_1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_USCH_2 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_USCH_3 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_1 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_2 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_3 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_4 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_5 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_6 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_7 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_8 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_9 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_THREAD_INST_EXECUTED 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_IMC 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_TEX 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_PMTRIG 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_THREADS_LAUNCHED 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_LSU_WB_OPS 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_CANT_DISPATCH 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_TEX_PENDING 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_MIO_0 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_BRU 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_REGISTER_READ 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_REGISTER_READ_PART1 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_REGISTER_READ_PART2 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_UNWEIGHTED_SCH_CANT_ISSUE_1 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_UNWEIGHTED_SCH_CANT_ISSUE_2 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_IFB 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_TEX_WB_INST_PENDING_HIST 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG0 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG1 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG2 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG3 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG4 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG5 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG6 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG7 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG8 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG9 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG10 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG11 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG12 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG13 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_DEBUG0 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_BRU_DEBUG0 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_UNIFORM_DATA_DETECT 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DATA_ACTIVITY0 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DATA_ACTIVITY1 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_LRF_READ_0 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_LRF_READ_1 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_WARP_OFF_DECK_REASON 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_THREAD_OCCUPANCY0 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_THREAD_OCCUPANCY1 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_THREAD_OCCUPANCY2 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_STATIC_PATTERN0 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_STATIC_PATTERN1 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_POWER_THROTTLE 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_IDE_SLEEPER 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_BLOCK_ACTIVITY 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_BLOCK_ACTIVITY1 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_BLOCK_ACTIVITY2 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_SINGLE_PASS0 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_10 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_11 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_12 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_13 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_14 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_15 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_APM_GROUP_11 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_APM_GROUP_10 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_APM_GROUP_9 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_APM_GROUP_8 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_APM_GROUP_7 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_APM_GROUP_6 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_APM_GROUP_5 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_APM_GROUP_4 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_APM_GROUP_3 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_APM_GROUP_2 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_APM_GROUP_1 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_APM_GROUP_0 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_ENABLE 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_QCTL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL 22:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_STATUS_0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_STATUS_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_STATUS_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIO_STATUS_PART0 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIO_STATUS_PART1 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_PIXOUT 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_IDC 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOP_PART0 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOP_PART1 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOP_PART2 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_PQ_PART0 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_PQ_PART1 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_PQ_2 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_PQ_3 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOS_PART0 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOS_PART1 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_PIXOUT_2 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_POSTCOALESCE 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_IQ_FULL_PART0 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_IQ_FULL_PART1 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_TEXIO 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOP_DEBUG0_PART0 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOP_DEBUG1_PART0 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOP_DEBUG2_PART0 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOP_DEBUG3_PART1 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_TEXIO_DEBUG0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_TEXIO_DEBUG1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_TEXIO_DEBUG2 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_TEXIO_DEBUG3 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG0_PART0 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG1_PART0 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG2_PART0 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG0_PART1 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG1_PART1 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG2_PART1 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG2_PART2 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_PIXOUT_DEBUG0 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_MMISC_DEBUG0 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_STATIC_PATTERN0 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_STATIC_PATTERN1 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_DEBUG1 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_DEBUG2 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_DEBUG3 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_DEBUG4 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_DEBUG5 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_DEBUG6 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_DEBUG7 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_DEBUG8 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_DEBUG9 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_DEBUG10 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_DEBUG11 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_SINGLE_PASS0 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_L1DATA_PART0 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_SINGLE_PASS_COMPUTE 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_T2D_PART0 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_T2D_PART1 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_PMPRED0 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_PMPRED1 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_PMPRED2 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_PMPRED3 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_SINGLE_PASS1 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_POSTCOALESCE2 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_POSTCOALESCE3 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_PMPRED4 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_DEBUG12 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_APM_GROUP_5 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_APM_GROUP_4 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_APM_GROUP_3 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_APM_GROUP_2 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_APM_GROUP_1 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_APM_GROUP_0 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_ENABLE 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_CTRL_MIO_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_DIDT_WEIGHTS_CTL 0x00419be0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_DIDT_WEIGHTS_CTL__PRIV_LEVEL_MASK 0x00419b00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_DIDT_WEIGHTS_CTL_INDEX 1:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_DIDT_WEIGHTS_CTL_INDEX_ZERO 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_DIDT_WEIGHTS_CTL_INDEX_MIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_DIDT_WEIGHTS_CTL_INDEX_MAX 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_DIDT_WEIGHTS_DATA 0x00419be4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_DIDT_WEIGHTS_DATA__PRIV_LEVEL_MASK 0x00419b00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_DIDT_WEIGHTS_DATA__APERTURE_INDEX_OFFSET 0xfffffffc /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_DIDT_WEIGHTS_DATA_DATA 31:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_DIDT_WEIGHTS_DATA_DATA_INIT 0x00000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH 0x00419b30 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_WARP_COUNT 7:0 /* R--UF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_MAJOR 19:16 /* R--UF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_MAJOR_5 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_MAJOR_7 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_MAJOR_8 0x8 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_MINOR 15:8 /* R--UF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_MINOR_00 0x00 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_MINOR_01 0x01 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_MINOR_02 0x02 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_MINOR_03 0x03 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_MINOR_05 0x05 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_MINOR_06 0x06 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_MINOR_07 0x07 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION 19:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_5_00 0x500 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_5_02 0x502 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_5_03 0x503 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_5_05 0x505 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_5_06 0x506 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_5_07 0x507 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_7_00 0x700 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_7_01 0x701 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_8_02 0x802 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_8_04 0x804 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SPA_VERSION_8_06 0x806 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MAJOR 31:28 /* R--UF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MAJOR_5 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MAJOR_6 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MAJOR_7 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MAJOR_8 0x8 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MINOR 27:20 /* R--UF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MINOR_00 0x00 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MINOR_01 0x01 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MINOR_02 0x02 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MINOR_03 0x03 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MINOR_05 0x05 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MINOR_06 0x06 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_MINOR_07 0x07 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION 31:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_5_00 0x500 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_5_02 0x502 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_5_03 0x503 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_5_05 0x505 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_5_06 0x506 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_6_00 0x600 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_6_01 0x601 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_6_02 0x602 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_7_00 0x700 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_7_01 0x701 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_8_02 0x802 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_8_04 0x804 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_8_06 0x806 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ARCH_SM_VERSION_8_07 0x807 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MACHINE_ID0 0x00419b34 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MACHINE_ID0_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MACHINE_ID0_V_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CONTEXT_SAVE_ADDR 0x00419b38 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CONTEXT_SAVE_ADDR_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CONTEXT_SAVE_ADDR_V_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x00419b3c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_IDC_CCACHE 1:1 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_IDC_CCACHE_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_IDC_CCACHE_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_IMM_CCACHE0 2:2 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_IMM_CCACHE0_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_IMM_CCACHE0_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_STATE_IMC_IV 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_STATE_IMC_IV_INCLUDE_TPC_MODE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_STATE_IMC_IV_EXCLUDE_TPC_MODE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_FILTER 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_FILTER_ENABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_FILTER_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_ALL_BANKS 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_ALL_BANKS_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_ALL_BANKS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_CBREF 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_CBREF_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_CBREF_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_CBREF_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_RTV 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_RTV_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_RTV_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_RTV_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_VEID 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_VEID_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_VEID_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_VEID_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_ICC_WAKEUP_BROADCAST_ENABLE 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_ICC_WAKEUP_BROADCAST_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_ICC_WAKEUP_BROADCAST_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_ICC_WAKEUP_BROADCAST_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_BINDLESS_START_END 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_BINDLESS_START_END_CALCULATE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_BINDLESS_START_END_SINGLE_SECTOR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_BINDLESS_START_END_ZERO_THREE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_BINDLESS_START_END_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK 0x00419b94 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_PL2_AND_PL3_ENABLED 0xc /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_CTXSW_UCODE_ENABLED 0x00076 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL 0x00419b40 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL__PRIV_LEVEL_MASK 0x00419b94 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_VPR_SCRUB 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_VPR_SCRUB_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_VPR_SCRUB_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_VPR_SCRUB_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_VPR_SCRUB_STATUS 4:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_VPR_SCRUB_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PRIVATE_CONTROL_VPR_SCRUB_STATUS_DONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL 0x00419b44 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_ICC_TAG_PREFETCH_LIMIT 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_ICC_TAG_PREFETCH_LIMIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_ICC_TAG_PREFETCH_LIMIT_8 0x8 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_ICC_PREFETCH 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_ICC_PREFETCH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_ICC_PREFETCH_PLUS_1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_ICC_PREFETCH_PLUS_2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_ICC_PREFETCH_PLUS_3 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_ICC_PREFETCH_PLUS_4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_ICC_PREFETCH_PLUS_6 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_ICC_PREFETCH_PLUS_8 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_ICC_PREFETCH_PLUS_10 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_0 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_0_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_1 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_1_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_2 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_2_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_3 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_3_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_4_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_5_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_6_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_FET_CONTROL_CYA_7_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x00419b48 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_EOS 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_EOS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_EOS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_EOS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_ALLOC_BATCH 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_ALLOC_BATCH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_ALLOC_BATCH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_ALLOC_BATCH_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_MPC_PRIORITY 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_MPC_PRIORITY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_MPC_PRIORITY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_MPC_PRIORITY_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_VTG_BOOST 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_VTG_BOOST_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_VTG_BOOST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_VTG_BOOST_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_BATCH_BOOST 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_BATCH_BOOST_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_BATCH_BOOST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_BATCH_BOOST_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_CACHE_MISS_BOOST 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_CACHE_MISS_BOOST_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_CACHE_MISS_BOOST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_CACHE_MISS_BOOST_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_SUBTILE_HOLD 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_SUBTILE_HOLD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_SUBTILE_HOLD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_SUBTILE_HOLD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER 15:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_4 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_5 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_6 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_7 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_8 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_9 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_10 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_11 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_12 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_13 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_14 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_15 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_16 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_17 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_18 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_INF 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_INIT 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_ROTATION_CS 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_ROTATION_CS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_ROTATION_CS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_ROTATION_CS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_ROTATION_PS 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_ROTATION_PS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_ROTATION_PS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_ROTATION_PS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_ROTATION_VTG 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_ROTATION_VTG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_ROTATION_VTG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_AGE_ROTATION_VTG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_CTA_AS_TILE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_CTA_AS_TILE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_CTA_AS_TILE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_CTA_AS_TILE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_EXIT_WAIT_FOR_ERRBAR 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_EXIT_WAIT_FOR_ERRBAR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_EXIT_WAIT_FOR_ERRBAR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_EXIT_WAIT_FOR_ERRBAR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_L0IC 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_L0IC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_L0IC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_L0IC_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_UNLOCK_DROPPED_MISS 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_UNLOCK_DROPPED_MISS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_UNLOCK_DROPPED_MISS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_UNLOCK_DROPPED_MISS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FULLTAG_WAKEUP_ALL 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FULLTAG_WAKEUP_ALL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FULLTAG_WAKEUP_ALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FULLTAG_WAKEUP_ALL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_UNCOND_BRANCH_OPT 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_UNCOND_BRANCH_OPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_UNCOND_BRANCH_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_UNCOND_BRANCH_OPT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_DISABLE_DISCARD_NEXT_L0IC_HIT 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_DISABLE_DISCARD_NEXT_L0IC_HIT_DISCARD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_DISABLE_DISCARD_NEXT_L0IC_HIT_NO_DISCARD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_DISABLE_DISCARD_NEXT_L0IC_HIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_ALLOW_GSCHED_ON_FWD_PROGRESS 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_ALLOW_GSCHED_ON_FWD_PROGRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_ALLOW_GSCHED_ON_FWD_PROGRESS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_ALLOW_GSCHED_ON_FWD_PROGRESS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_EXTRA_DMMA_WAIT 28:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_EXTRA_DMMA_WAIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FP16_FWD_PROGRESS_WATERMK 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_FP16_FWD_PROGRESS_WATERMK_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_SPARE 31:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_SPARE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED 0x00419b50 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_SAFE_WAIT 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_SAFE_WAIT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_SAFE_WAIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_SAFE_WAIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_REQ_ALL 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_REQ_ALL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_REQ_ALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_REQ_ALL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FWD_PROGRESS 6:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FWD_PROGRESS_DISABLE 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FWD_PROGRESS_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_LONG_WAIT 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_LONG_WAIT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_LONG_WAIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_LONG_WAIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_GROUP_BIT 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_GROUP_BIT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_GROUP_BIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_GROUP_BIT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_DEPBAR_0 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_DEPBAR_0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_DEPBAR_0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FORCE_DEPBAR_0_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_GROUP_BIT_CLR_ON_STALL 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_GROUP_BIT_CLR_ON_STALL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_GROUP_BIT_CLR_ON_STALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_GROUP_BIT_CLR_ON_STALL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_DEFER_BLOCKING 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_DEFER_BLOCKING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_DEFER_BLOCKING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_DEFER_BLOCKING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_EXE_COLLAPSING 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_EXE_COLLAPSING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_EXE_COLLAPSING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_EXE_COLLAPSING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_IFB_READ_OPT 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_IFB_READ_OPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_IFB_READ_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_IFB_READ_OPT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_EXTRA_MMA_S_WAIT 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_EXTRA_MMA_S_WAIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_EXTRA_MMA_M_WAIT 16:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_EXTRA_MMA_M_WAIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_EXTRA_MMA_L_WAIT 31:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_EXTRA_MMA_L_WAIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_IPB_BYPASS 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_IPB_BYPASS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_IPB_BYPASS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_IPB_BYPASS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_B2B_EXIT_ON_SHADOWPIPE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_B2B_EXIT_ON_SHADOWPIPE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_B2B_EXIT_ON_SHADOWPIPE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_B2B_EXIT_ON_SHADOWPIPE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA16 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA16_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA16_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA16_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA32 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA32_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA32_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA32_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMAE8M10 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMAE8M10_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMAE8M10_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMAE8M10_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA8832 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA8832_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA8832_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA8832_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_BMMA 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_BMMA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_BMMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_BMMA_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_FFMA 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_FFMA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_FFMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_FFMA_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IDP4A 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IDP4A_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IDP4A_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IDP4A_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DMMA 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DMMA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DMMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DMMA_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DFMA 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DFMA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DFMA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DFMA_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK 0x00419b78 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL 0x00419b54 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL__PRIV_LEVEL_MASK 0x00419b78 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP0_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP0_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP1_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP1_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP2_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP2_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP3_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP3_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP_TASK 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_SCRUB_QRFDP_DONE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS 0x00419b58 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP1 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP1_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP1_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP2 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP2_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP2_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP3 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP3_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP3_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP0 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP1 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP1_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP1_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP2 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP2_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP2_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP3 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP3_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP3_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP0 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP0_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP0_ACTIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP1 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP1_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP1_ACTIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP2 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP2_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP2_ACTIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP3 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP3_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP3_ACTIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP(i) (8+(i)):(8+(i)) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP(i) (16+(i)):(16+(i)) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP__SIZE_1 4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP_PASSED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_SCRUB_QRFDP_FAILED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CORRECTED_ERR_COUNT 0x00419b5c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_UNCORRECTED_ERR_COUNT 0x00419b60 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_ADDRESS 0x00419b64 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_ADDRESS_INDEX 14:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_ADDRESS_SM_ID 14:14 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_ADDRESS_QUADRANT_ID 13:12 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_ADDRESS_QUAD_ID 11:10 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_LRF_ECC_ADDRESS_BANK_ID 9:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL 0x00419b68 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL__PRIV_LEVEL_MASK 0x00419b78 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_0_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_0_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_TASK 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_DONE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS 0x00419b6c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_0 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1(i) (2+(i)):(2+(i)) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT 0x00419b70 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT 0x00419b74 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK 0x00419b7c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL2_ENABLED 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL23_ENABLED 0xc /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL2_ENABLED 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE 0x00419b80 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE__PRIV_LEVEL_MASK 0x00419b7c /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_ISSUE_STAGGER_BASE 5:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_ISSUE_STAGGER_BASE_INIT 0x00 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_ISSUE_STAGGER_INCR 13:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_ISSUE_STAGGER_INCR_INIT 0x00 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_ISSUE_STATUS 14:14 /* R-BVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_ISSUE_STATUS_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_ISSUE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_ISSUE_STATUS_INIT 0x0 /* R-B-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_ISSUE_ENABLE 15:15 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_ISSUE_ENABLE_NO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_ISSUE_ENABLE_YES 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_ISSUE_ENABLE_INIT 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_DISP_STAGGER_BASE 21:16 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_DISP_STAGGER_BASE_INIT 0x00 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_DISP_STAGGER_INCR 29:24 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_DISP_STAGGER_INCR_INIT 0x00 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_DISP_STATUS 30:30 /* R-BVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_DISP_STATUS_INACTIVE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_DISP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_DISP_STATUS_INIT 0x0 /* R-B-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_DISP_ENABLE 31:31 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_DISP_ENABLE_NO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_DISP_ENABLE_YES 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_HIPWR_THROTTLE_DISP_ENABLE_INIT 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_CTRL1 0x00419bfc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_CTRL1_FMAH_THROTTLE_MIN 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_CTRL1_FMAH_THROTTLE_MIN_INIT 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_CTRL1_FMAH_THROTTLE_MAX 24:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_CTRL1_FMAH_THROTTLE_MAX_INIT 0x0d /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_CTRL1_FMAH_THROTTLE_INC 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_CTRL1_FMAH_THROTTLE_INC_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_CTRL1_FMAH_THROTTLE_ENABLE 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_CTRL1_FMAH_THROTTLE_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DFD_CONTROL 0x00419b98 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DFD_CONTROL_CMD 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DFD_CONTROL_CMD_NOP 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DFD_DATA 0x00419b9c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DFD_DATA_VALUE 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DFD_DATA_VALUE_EMPTY 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x00419ba0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_INCLUDE_RFA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_TTU 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_TTU_EXCLUDE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_TTU_INCLUDE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_TTU_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL_0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL_1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_BR_FALLTHRU_OPT 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_BR_FALLTHRU_OPT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_BR_FALLTHRU_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_BR_FALLTHRU_OPT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_8 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_8_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_8_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_8_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_9 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_9_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_9_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_9_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_10 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_10_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_10_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_10_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_11 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_11_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_11_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_11_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_12 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_12_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_12_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_12_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_13 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_13_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_13_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_13_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_14 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_14_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_14_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_14_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_15 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_15_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_15_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_CYA_15_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_FFMA_DATAPATH 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_FFMA_DATAPATH_USE_BUNDLE_CONFIG 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_FFMA_DATAPATH_USE_BOTH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_FFMA_DATAPATH_USE_FMA_LITE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL 0x00419ba4 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_COLLECTOR_REUSE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_COLLECTOR_REUSE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_COLLECTOR_REUSE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_2_CYCLE_COLLECTION 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_2_CYCLE_COLLECTION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_2_CYCLE_COLLECTION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_FTZ_NARROWS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_FTZ_NARROWS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_FTZ_NARROWS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_FTZ_NARROWS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_KILLED_LD_IS_NOP 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_KILLED_LD_IS_NOP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_KILLED_LD_IS_NOP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_KILLED_LD_IS_NOP_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_FORCE_ALLOW_GLOBAL_STORE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_FORCE_ALLOW_GLOBAL_STORE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_FORCE_ALLOW_GLOBAL_STORE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_FORCE_ALLOW_GLOBAL_STORE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_COLLECTOR_FP64_REUSE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_COLLECTOR_FP64_REUSE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_COLLECTOR_FP64_REUSE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_FP64_PAIRING 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_FP64_PAIRING_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_FP64_PAIRING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_DDP_RAM_REUSE 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_DDP_RAM_REUSE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_DDP_RAM_REUSE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_PIXOUT_READ_PARALLEL 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_PIXOUT_READ_PARALLEL_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_PIXOUT_READ_PARALLEL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_TOQ_STATUS_STALL 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_TOQ_STATUS_STALL_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_TOQ_STATUS_STALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_RFDP_UNIFORM_DATA_DETECT 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_RFDP_UNIFORM_DATA_DETECT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_RFDP_UNIFORM_DATA_DETECT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_RE_SUPPRESS 12:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_RE_SUPPRESS_ON_PT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_RE_SUPPRESS_ON_FULL_MASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_RE_SUPPRESS_DISABLE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_VTG_SHADER_POP 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_VTG_SHADER_POP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_VTG_SHADER_POP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_PIXEL_SHADER_POP 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_PIXEL_SHADER_POP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_PIXEL_SHADER_POP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_COMPUTE_SHADER_POP 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_COMPUTE_SHADER_POP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_COMPUTE_SHADER_POP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_RE_SUPPRESS_FOR_WT 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_RE_SUPPRESS_FOR_WT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_RE_SUPPRESS_FOR_WT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_CYA1 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_CYA1_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_CANCEL_REUSE_ON_BYPASS 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_CANCEL_REUSE_ON_BYPASS_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_CANCEL_REUSE_ON_BYPASS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_ACTIVE_MASK_CG 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_ACTIVE_MASK_CG_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_ACTIVE_MASK_CG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_AND_C_REUSE 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_AND_C_REUSE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_AND_C_REUSE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_COMPUTE_SHADER_QUAD 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_TTU_INST_OUTSIDE_MACRO 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_TTU_INST_OUTSIDE_MACRO_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_TTU_INST_OUTSIDE_MACRO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_NON_TTU_INST_IN_MACRO 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_NON_TTU_INST_IN_MACRO_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_NON_TTU_INST_IN_MACRO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_SPARE 31:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL_SPARE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2 0x00419ba8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_PIX_PQ_WATERMARK 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_PIX_PQ_WATERMARK_MIN 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_PIX_PQ_WATERMARK_MAX 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_PIX_PQ_WATERMARK_INIT 0x19 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_SHM_PQ_WATERMARK 13:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_SHM_PQ_WATERMARK_MIN 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_SHM_PQ_WATERMARK_MAX 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_SHM_PQ_WATERMARK_INIT 0x1c /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_TEX_PQ_WATERMARK 20:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_TEX_PQ_WATERMARK_MIN 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_TEX_PQ_WATERMARK_MAX 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_TEX_PQ_WATERMARK_INIT 0x18 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_GRP1_PQ_WATERMARK 25:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_GRP1_PQ_WATERMARK_MIN 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_GRP1_PQ_WATERMARK_MAX 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_GRP1_PQ_WATERMARK_INIT 0x14 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL 27:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_8_CYCLES 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_16_CYCLES 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_32_CYCLES 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_AGUL_THROTTLE 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_AGUL_THROTTLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_AGUL_THROTTLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_AGUL_THROTTLE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_WAKEUP_AUX_ENTRY 29:29 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_WAKEUP_AUX_ENTRY_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_WAKEUP_AUX_ENTRY_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_RESET_ALL_PQ 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_RESET_ALL_PQ_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_RESET_ALL_PQ_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_SPARE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL2_SPARE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3 0x00419bc8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_AGUL_THROTTLE_ALWAYS_ON 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_AGUL_THROTTLE_ALWAYS_ON_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_AGUL_THROTTLE_ALWAYS_ON_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_AGUL_THROTTLE_ALWAYS_ON_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_AGUL_THROTTLE_SHM 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_AGUL_THROTTLE_SHM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_AGUL_THROTTLE_SHM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_AGUL_THROTTLE_SHM_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_AGUL_THROTTLE_WATERMARK 6:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_AGUL_THROTTLE_WATERMARK_MIN 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_AGUL_THROTTLE_WATERMARK_MAX 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_AGUL_THROTTLE_WATERMARK_INIT 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_CLEAR_CREDIT_ON_RFA_STATUS 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_CLEAR_CREDIT_ON_RFA_STATUS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_CLEAR_CREDIT_ON_RFA_STATUS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_CLEAR_CREDIT_ON_RFA_STATUS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_CLEAR_CREDIT_ON_LST_STATUS 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_CLEAR_CREDIT_ON_LST_STATUS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_CLEAR_CREDIT_ON_LST_STATUS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_CLEAR_CREDIT_ON_LST_STATUS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_THRESHOLD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_EXT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_BOTH 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD 12:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_32 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_64 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_128 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_255 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS_DISABLE_ON_ECC 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS_ENABLE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_STALL_MUFU_ON_ECC 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_STALL_MUFU_ON_ECC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_STALL_MUFU_ON_ECC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_STALL_MUFU_ON_ECC_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT 18:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_VAL1 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_VAL2 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_VAL3 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_VAL4 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_TPQ_PARTIAL_GRANT 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_TPQ_PARTIAL_GRANT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_TPQ_PARTIAL_GRANT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_TPQ_PARTIAL_GRANT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_TTU_TPQ_PARTIAL_GRANT 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_TTU_TPQ_PARTIAL_GRANT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_TTU_TPQ_PARTIAL_GRANT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_TTU_TPQ_PARTIAL_GRANT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_TPQ_GRANT_WITH_AUX_REPLAY 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_TPQ_GRANT_WITH_AUX_REPLAY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_TPQ_GRANT_WITH_AUX_REPLAY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_TPQ_GRANT_WITH_AUX_REPLAY_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD 23:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_VAL0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_VAL1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_VAL2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_VAL3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB 25:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB_THRESHOLD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB_ALWAYS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD 28:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_VAL0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_VAL1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_VAL2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_VAL3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_INIT 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_SPARE 31:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DISP_CTRL3_SPARE_INIT 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_OBSERVE 0x00419bac /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_OBSERVE_CYA_6 6:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_OBSERVE_CYA_7 7:7 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_OBSERVE_CYA_8 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_OBSERVE_CYA_9 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_OBSERVE_CYA_10 10:10 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_OBSERVE_CYA_11 11:11 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_OBSERVE_CYA_12 12:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_OBSERVE_CYA_13 13:13 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_OBSERVE_CYA_14 14:14 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_OBSERVE_CYA_15 15:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x00419bb0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL_0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL_1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WRITE_PRI_CTL 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WRITE_PRI_CTL_BOTH 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WRITE_PRI_CTL_SELECT_ONE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_PULSE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_PULSE_NEVER 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_PULSE_ON_SM_NONIDLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_PULSE_ALWAYS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT1 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT2 11:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT3 15:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1 19:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC 23:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK 25:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL 27:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL 29:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_BA_BLCG_WAKEUP 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_BA_BLCG_WAKEUP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1 0x00419bcc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_COUNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_COUNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_COUNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_CTL 0x00419cf0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_CTL_INDEX 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_CTL_INDEX_MIN 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_CTL_INDEX_MAX 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_CTL_TRIGGER 11:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_CTL_TRIGGER_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_CTL_CONTROL 30:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_CTL_CONTROL_INIT 0x00000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_CTL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_CTL_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_DATA 0x00419cf4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_DATA_DATA 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_THROTTLE_DATA_DATA_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_VST_CTL 0x00419cf8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_VST_CTL_INDEX 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_VST_CTL_INDEX_MIN 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_VST_CTL_INDEX_MAX 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_VST_CTL_CONTROL 30:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_VST_CTL_CONTROL_INIT 0x0000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_VST_CTL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_VST_CTL_ENABLE_NO 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_VST_CTL_ENABLE_YES 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_VST_DATA 0x00419cfc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_VST_DATA_DATA 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_POWER_VST_DATA_DATA_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL 0x00419bb4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FMAI 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FMAI_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FMAI_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FMAI_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FMAI_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FXU 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FXU_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FXU_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FXU_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FXU_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FU 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FU_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FU_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FU_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FU_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_X2X 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_X2X_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_X2X_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_X2X_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_X2X_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_RFDP 9:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_RFDP_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_RFDP_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_RFDP_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_RFDP_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_SFPQ_FMA64 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_SFPQ_FMA64_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_SFPQ_FMA64_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_SFPQ_FMA64_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_SFPQ_FMA64_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_IMMA 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_IMMA_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_IMMA_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_IMMA_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_IMMA_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FP16G0DP 17:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FP16G0DP_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FP16G0DP_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FP16G0DP_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FP16G0DP_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FP16G1DP 19:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FP16G1DP_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FP16G1DP_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FP16G1DP_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_FP16G1DP_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_CORE2LST_WAKEUP 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_CORE2LST_WAKEUP_USE_MIOC_WAKEUP 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_CORE2LST_WAKEUP_USE_MIOC_STATUS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_F_PIPE 22:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_F_PIPE_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_F_PIPE_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_F_PIPE_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_F_PIPE_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_M_PIPE 24:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_M_PIPE_ENABLED_ALWAYS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_M_PIPE_ENABLED_DISP_WAKEUP 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_M_PIPE_ENABLED_DISP_STATUS_WAKEUP 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_WAKEUP_CONTROL_M_PIPE_ENABLED_SM_STATUS_WAKEUP 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_QUAD_BA_CONTROL 0x00419bb8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_QUAD_BA_CONTROL__PRIV_LEVEL_MASK 0x00419b00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_QUAD_BA_CONTROL_INDEX 4:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_QUAD_BA_CONTROL_INDEX_ZERO 0x00 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_QUAD_BA_CONTROL_INDEX_MIN 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_QUAD_BA_CONTROL_INDEX_MAX 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_QUAD_BA_DATA 0x00419bbc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_QUAD_BA_DATA__PRIV_LEVEL_MASK 0x00419b00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_QUAD_BA_DATA__APERTURE_INDEX_OFFSET 0xfffffffc /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_QUAD_BA_DATA_DATA 27:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_QUAD_BA_DATA_DATA_INIT 0x0000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_BA_CONTROL 0x00419bc0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_BA_CONTROL__PRIV_LEVEL_MASK 0x00419b00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_BA_CONTROL_INDEX 1:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_BA_CONTROL_INDEX_ZERO 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_BA_CONTROL_INDEX_MIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_BA_CONTROL_INDEX_MAX 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_BA_DATA 0x00419bc4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_BA_DATA__PRIV_LEVEL_MASK 0x00419b00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_BA_DATA__APERTURE_INDEX_OFFSET 0xfffffffc /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_BA_DATA_DATA 27:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_BA_DATA_DATA_INIT 0x0000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_BA_CONTROL 0x00419bd0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_BA_CONTROL__PRIV_LEVEL_MASK 0x00419b00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_BA_CONTROL_INDEX 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_BA_CONTROL_INDEX_ZERO 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_BA_CONTROL_INDEX_MIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_BA_CONTROL_INDEX_MAX 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_BA_DATA 0x00419bd4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_BA_DATA__PRIV_LEVEL_MASK 0x00419b00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_BA_DATA__APERTURE_INDEX_OFFSET 0xfffffffc /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_BA_DATA_DATA 27:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_BA_DATA_DATA_INIT 0x0000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_BA_CONTROL 0x00419e68 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_BA_CONTROL__PRIV_LEVEL_MASK 0x00419b00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_BA_CONTROL_INDEX 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_BA_CONTROL_INDEX_ZERO 0x0 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_BA_CONTROL_INDEX_MIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_BA_CONTROL_INDEX_MAX 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_BA_DATA 0x00419e6c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_BA_DATA__PRIV_LEVEL_MASK 0x00419b00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_BA_DATA__APERTURE_INDEX_OFFSET 0xfffffffc /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_BA_DATA_DATA 27:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_BA_DATA_DATA_INIT 0x0000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG 0x00419c80 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_IDLE_CG_DLY_CNT__PROD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG1 0x00419c84 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG1_SLCG 17:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG1_SLCG_ENABLED 0x00000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG1_SLCG_DISABLED 0x1ffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_0_CG1_SLCG__PROD 0x1fffe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG 0x00419c88 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_IDLE_CG_DLY_CNT__PROD 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG1 0x00419c8c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_1_CG1_SLCG__PROD 0x7fb8f9c2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG 0x00419c90 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_IDLE_CG_DLY_CNT__PROD 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG1 0x00419c94 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG1_SLCG 29:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG1_SLCG_DISABLED 0x1fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_2_CG1_SLCG__PROD 0x1cf80180 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG 0x00419c98 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG1 0x00419c9c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_3_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG 0x00419ca0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_IDLE_CG_DLY_CNT__PROD 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG1 0x00419ca4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG1_SLCG 13:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG1_SLCG_DISABLED 0x1fff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_4_CG1_SLCG__PROD 0x1ffe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG 0x00419ca8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_IDLE_CG_DLY_CNT__PROD 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG1 0x00419cac /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_5_CG1_SLCG__PROD 0xfc00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG 0x00419cb0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_IDLE_CG_DLY_CNT__PROD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG1 0x00419cb4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG1_SLCG 12:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG1_SLCG_ENABLED 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG1_SLCG_DISABLED 0xfff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_BLCG_6_CG1_SLCG__PROD 0xeb0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG 0x00419ce8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_MEMBAR_WINDOW 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_MEMBAR_WINDOW_INIT 0x02 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_X4 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_X16 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_X64 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_X256 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_TEX2D_CONTROL 13:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_TEX2D_CONTROL_HALF0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_TEX2D_CONTROL_HALF1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_TEX2D_CONTROL_BOTH 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_TEX2D_CONTROL_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_PIX_CMD_DONE_STALL_PFM3D 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_PIX_CMD_DONE_STALL_PFM3D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_PIX_CMD_DONE_STALL_PFM3D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_PIX_CMD_DONE_STALL_PFM3D_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_MIOP_SPARE 23:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG_MIOP_SPARE_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2 0x00419cec /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_MIOS_SPARE 2:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_MIOS_SPARE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_PIXOUT_LOW_WATERMARK 5:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_PIXOUT_LOW_WATERMARK_INIT 0x5 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_IMC_TAG_HASH_CTRL 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_IMC_TAG_HASH_CTRL_GALOIS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_IMC_TAG_HASH_CTRL_NON_GALOIS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_IMC_TAG_HASH_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_TTU_BLCG_INPUT_CTRL 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_TTU_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_TTU_BLCG_INPUT_CTRL_INCLUDE_RFA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_TTU_BLCG_INPUT_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_MIOS_BLCG_INPUT_CTRL 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_MIOS_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_MIOS_BLCG_INPUT_CTRL_INCLUDE_RFA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_MIOS_BLCG_INPUT_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_MIOP_BLCG_INPUT_CTRL 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_MIOP_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_MIOP_BLCG_INPUT_CTRL_INCLUDE_RFA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_MIOP_BLCG_INPUT_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_OUTSTANDING_MIOS_WB_REQ_COUNT 16:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_OUTSTANDING_MIOS_WB_REQ_COUNT_DISABLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_OUTSTANDING_MIOS_WB_REQ_COUNT_16 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_OUTSTANDING_TEX_WB_REQ_COUNT 21:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_OUTSTANDING_TEX_WB_REQ_COUNT_DISABLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_OUTSTANDING_TEX_WB_REQ_COUNT_16 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_OUTSTANDING_ADU_WB_REQ_COUNT 26:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_OUTSTANDING_ADU_WB_REQ_COUNT_DISABLE 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_OUTSTANDING_ADU_WB_REQ_COUNT_16 0x10 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_DETECT_UNIFORM_LD 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_DETECT_UNIFORM_LD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_DETECT_UNIFORM_LD_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_FC_RESERVED_FOR_SUST_NUM_CYCLES 30:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_FC_RESERVED_FOR_SUST_NUM_CYCLES_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_SUST_STEAL 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_SUST_STEAL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_SUST_STEAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_MIO_CFG2_SUST_STEAL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL 0x00419bd8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_FAST_POINT_SAMPLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_FAST_POINT_SAMPLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_FAST_POINT_SAMPLE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP 2:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_DEFAULT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_TO_CG 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_TO_CV 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_BYPASS 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP 4:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_DEFAULT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_TO_CG 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_TO_CV 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_BYPASS 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_TEX2SMM_ERR_RESPONSE_FORWARD 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_TEX2SMM_ERR_RESPONSE_FORWARD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_TEX2SMM_ERR_RESPONSE_FORWARD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_TEX2SMM_ERR_RESPONSE_FORWARD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE_INSTR 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE_FORCE_RTZ 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE_FORCE_RTNE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE 10:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_X86_63_47_MATCH 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_ARM_63_48_MATCH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_POWER_63_46_ZERO 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_POWER_63_49_ZERO 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_ARM_55_48_MATCH 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_NO_CHECK 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_SPARE 18:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEXIO_CONTROL_SPARE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_SAMP_CTRL 0x00419bdc /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_SAMP_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_SAMP_CTRL_ENABLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_SAMP_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_SAMP_CTRL_TIMER 5:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_PM_SAMP_CTRL_TIMER_INIT 0x05 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CONFIG 0x00419e08 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CONFIG_TPC_ID 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CONFIG_TPC_ID_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TPC_ESR_SM_SEL 0x00419e0c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TPC_ESR_SM_SEL_SM0_ERROR 0:0 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TPC_ESR_SM_SEL_SM0_ERROR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TPC_ESR_SM_SEL_SM0_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TPC_ESR_SM_SEL_SM1_ERROR 1:1 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TPC_ESR_SM_SEL_SM1_ERROR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TPC_ESR_SM_SEL_SM1_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TPC_ESR_SM_SEL_SMC_ERROR 2:2 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TPC_ESR_SM_SEL_SMC_ERROR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TPC_ESR_SM_SEL_SMC_ERROR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x00419e10 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_VAT_ALARM 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_VAT_ALARM_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_VAT_ALARM_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_CORRECTED 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_CORRECTED_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_CORRECTED_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_UNCORRECTED 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_UNCORRECTED_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_UNCORRECTED_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x00419e14 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_VAT_ALARM 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_VAT_ALARM_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_VAT_ALARM_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_ECC_CORRECTED 4:4 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_ECC_CORRECTED_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_ECC_CORRECTED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_ECC_UNCORRECTED 5:5 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_ECC_UNCORRECTED_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_ECC_UNCORRECTED_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL 0x00419e18 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_NANOSLEEP_MIN 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_NANOSLEEP_MIN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_NANOSLEEP_MAX 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_NANOSLEEP_MAX_INIT 0xf /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_YIELD_NOP_CNT 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_YIELD_NOP_CNT_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_CYA_PESSIMISTIC_YIELD 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_CYA_PESSIMISTIC_YIELD_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_CYA_PESSIMISTIC_YIELD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_CYA_FORCE_ALIASED 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_CYA_FORCE_ALIASED_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_CYA_FORCE_ALIASED_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_CYA_DISABLE_OPT_TOP 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_CYA_DISABLE_OPT_TOP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_CYA_DISABLE_OPT_TOP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_BSSY_REPLACE_MASK 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_BSSY_REPLACE_MASK_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_BSSY_REPLACE_MASK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_BSYNC_EMPTY_STACK_YIELD 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_BSYNC_EMPTY_STACK_YIELD_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_BSYNC_EMPTY_STACK_YIELD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_ELECTION_RELEASE_BARRIER 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_ELECTION_RELEASE_BARRIER_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_ELECTION_RELEASE_BARRIER_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_CNTRL_ELECTION_RELEASE_BARRIER__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL 0x00419bf0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SKIP_READ 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SKIP_READ_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SKIP_READ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SKIP_READ_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_HASH_LG 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_HASH_LG_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_HASH_LG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_HASH_LG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_HASH_TEX 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_HASH_TEX_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_HASH_TEX_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_HASH_TEX_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_L1_ATOMIC 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_L1_ATOMIC_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_L1_ATOMIC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_L1_ATOMIC_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_SURFACE_LD 5:5 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_SURFACE_LD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_SURFACE_LD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_SURFACE_LD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_2D 6:6 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_2D_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_2D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_2D_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_LOCAL 7:7 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_LOCAL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_LOCAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_LOCAL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_GLOBAL 8:8 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_GLOBAL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_GLOBAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_GLOBAL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_TEX 9:9 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_TEX_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_TEX_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_TEX_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_SURFACE_ST 10:10 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_SURFACE_ST_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_SURFACE_ST_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_SURFACE_ST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_CTRL 10:5 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_CTRL_EN_NONE 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CACHE_CTRL_EN_ALL 0x3f /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SCRUBBER_READY_COUNT 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SCRUBBER_READY_COUNT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SCRUBBER_READY_COUNT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SCRUBBER_READY_COUNT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_WRITE_ALLOC_SURFACE 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_WRITE_ALLOC_SURFACE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_WRITE_ALLOC_SURFACE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_WRITE_ALLOC_SURFACE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_WRITE_ALLOC_GLOBAL 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_WRITE_ALLOC_GLOBAL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_WRITE_ALLOC_GLOBAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_WRITE_ALLOC_GLOBAL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_WRITE_ALLOC_LOCAL 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_WRITE_ALLOC_LOCAL_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_WRITE_ALLOC_LOCAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_WRITE_ALLOC_LOCAL_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_DUAL_LOD_SERIAL 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_DUAL_LOD_SERIAL_AUTO 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_DUAL_LOD_SERIAL_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_REPLACEMENT_ALLOC_RANK_EU_AS_EN 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_REPLACEMENT_ALLOC_RANK_EU_AS_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_REPLACEMENT_ALLOC_RANK_EU_AS_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_REPLACEMENT_ALLOC_RANK_EU_AS_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_REPLACEMENT_HIT_RANK_EN 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_REPLACEMENT_HIT_RANK_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_REPLACEMENT_HIT_RANK_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_REPLACEMENT_HIT_RANK_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_LG_THROTTLE_T2D 22:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_LG_THROTTLE_T2D_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_LG_THROTTLE_DSLOT 27:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_LG_THROTTLE_DSLOT_INIT 0x08 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_ALWAYS_CUT_COLLECTOR 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_ALWAYS_CUT_COLLECTOR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_ALWAYS_CUT_COLLECTOR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_ALWAYS_CUT_COLLECTOR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SURFACE_CUT_COLLECTOR 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SURFACE_CUT_COLLECTOR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SURFACE_CUT_COLLECTOR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_SURFACE_CUT_COLLECTOR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_RESET_L1_ON_LEAK 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_RESET_L1_ON_LEAK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_RESET_L1_ON_LEAK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_RESET_L1_ON_LEAK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CLEAR_EV_LONG_ON_3DPFM 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CLEAR_EV_LONG_ON_3DPFM_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CLEAR_EV_LONG_ON_3DPFM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL_CLEAR_EV_LONG_ON_3DPFM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2 0x00419bf4 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_RED 0:0 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_RED_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_RED_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_RED_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_ATOM_CAS 1:1 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_ATOM_CAS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_ATOM_CAS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_ATOM_CAS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_ATOM 2:2 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_ATOM_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_ATOM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_ATOM_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_LG 3:3 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_LG_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_LG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_LG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_SURFACE 4:4 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_SURFACE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_SURFACE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_SURFACE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_ATOMIC_CTRL 4:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_ATOMIC_CTRL_EN_NONE 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CONCAT_ATOMIC_CTRL_EN_ALL 0x1f /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_LG_WR_COALESCE_EN 5:5 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_LG_WR_COALESCE_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_LG_WR_COALESCE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_LG_WR_COALESCE_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_LG_RD_COALESCE_EN 6:6 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_LG_RD_COALESCE_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_LG_RD_COALESCE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_LG_RD_COALESCE_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_SU_WR_COALESCE_EN 7:7 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_SU_WR_COALESCE_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_SU_WR_COALESCE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_SU_WR_COALESCE_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_SU_RD_COALESCE_EN 8:8 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_SU_RD_COALESCE_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_SU_RD_COALESCE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_SU_RD_COALESCE_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_TEX_RD_COALESCE_EN 9:9 /* RWIUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_TEX_RD_COALESCE_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_TEX_RD_COALESCE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_TEX_RD_COALESCE_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_COALESCE_EN_CTRL 9:5 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_COALESCE_EN_CTRL_EN_NONE 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_COALESCE_EN_CTRL_EN_ALL 0x1f /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_LIFE_EXTN_EN 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_LIFE_EXTN_EN_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_LIFE_EXTN_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_LIFE_EXTN_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_LATFIFO_DEPTH_DIV4 18:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_LATFIFO_DEPTH_DIV4_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_TIMEOUT 22:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_TIMEOUT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_TIMEOUT_PRESCALAR 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_TIMEOUT_PRESCALAR_X2K 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_TIMEOUT_PRESCALAR_X16K 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_TIMEOUT_PRESCALAR_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DETECT_DSLOT_LEAK 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DETECT_DSLOT_LEAK_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DETECT_DSLOT_LEAK_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DETECT_DSLOT_LEAK__PROD 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DETECT_REFCOUNTER_ERR 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DETECT_REFCOUNTER_ERR_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DETECT_REFCOUNTER_ERR_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DETECT_REFCOUNTER_ERR__PROD 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DETECT_L1MISS_LEAK 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DETECT_L1MISS_LEAK_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DETECT_L1MISS_LEAK_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_STORE_COALESCE_GAP_EN 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_STORE_COALESCE_GAP_EN_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_STORE_COALESCE_GAP_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_STORE_COALESCE_GAP_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_COALESCE_FLUSH 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_COALESCE_FLUSH_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_COALESCE_FLUSH_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_NO_EVICT_LONG 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_NO_EVICT_LONG_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_NO_EVICT_LONG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_NO_EVICT_LONG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_LD_COMMIT 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_LD_COMMIT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_LD_COMMIT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_CBUF_LD_COMMIT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DBE_PRTY_CYA 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DBE_PRTY_CYA_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DBE_PRTY_CYA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1TAG_CTRL2_DBE_PRTY_CYA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL 0x00419bf8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_LG_THROTTLE_ENABLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_LG_THROTTLE_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_LG_THROTTLE_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_LG_THROTTLE_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_MAIN_COLLECTOR_LOOK_AHEAD_ENABLE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_MAIN_COLLECTOR_LOOK_AHEAD_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_MAIN_COLLECTOR_LOOK_AHEAD_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_MAIN_COLLECTOR_LOOK_AHEAD_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIDE_COLLECTOR_LOOK_AHEAD_ENABLE 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIDE_COLLECTOR_LOOK_AHEAD_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIDE_COLLECTOR_LOOK_AHEAD_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIDE_COLLECTOR_LOOK_AHEAD_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIDE_COLLECTOR_PAIRING_ENABLE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIDE_COLLECTOR_PAIRING_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIDE_COLLECTOR_PAIRING_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIDE_COLLECTOR_PAIRING_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_HOLDING_BUFFER_BYPASS_ENABLE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_HOLDING_BUFFER_BYPASS_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_HOLDING_BUFFER_BYPASS_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_HOLDING_BUFFER_BYPASS_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_STALL_GNIC_REQUESTS_ENABLE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_STALL_GNIC_REQUESTS_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_STALL_GNIC_REQUESTS_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_STALL_GNIC_REQUESTS_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_STALL_4Q_REQUESTS_ENABLE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_STALL_4Q_REQUESTS_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_STALL_4Q_REQUESTS_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_STALL_4Q_REQUESTS_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TEX_ENABLE 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TEX_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TEX_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TEX_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_TCR_TEX_ENABLE 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_TCR_TEX_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_TCR_TEX_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_TCR_TEX_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_TCR_READ_PARTIAL_SECTOR_ENABLE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_TCR_READ_PARTIAL_SECTOR_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_TCR_READ_PARTIAL_SECTOR_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_TCR_READ_PARTIAL_SECTOR_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SM_READ_STARVATION_THRESHOLD_COUNT 14:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SM_READ_STARVATION_THRESHOLD_COUNT_INIT 0x4 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SM_READ_STALL_TEX_TCR_NUM_CYCLES 17:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SM_READ_STALL_TEX_TCR_NUM_CYCLES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_TEX_READ_STARVATION_THRESHOLD_COUNT 20:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_TEX_READ_STARVATION_THRESHOLD_COUNT_INIT 0x4 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_TEX_READ_STALL_TCR_NUM_CYCLES 23:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_TEX_READ_STALL_TCR_NUM_CYCLES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIDE_COLLECTOR_FAST_BDI_ENABLE 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIDE_COLLECTOR_FAST_BDI_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIDE_COLLECTOR_FAST_BDI_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIDE_COLLECTOR_FAST_BDI_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_TTU_READ_STARVATION_THRESHOLD_COUNT 27:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_TTU_READ_STARVATION_THRESHOLD_COUNT_INIT 0x4 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_TTU_READ_STALL_TEX_TCR_NUM_CYCLES 30:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_TTU_READ_STALL_TEX_TCR_NUM_CYCLES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TTU_ENABLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TTU_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TTU_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TTU_ENABLE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_ADDRESS 0x00419e1c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_ADDRESS_INDEX 17:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_ADDRESS_SM_ID 17:17 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_ADDRESS_SUBBANK_ID 16:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_DATA_ECC_ADDRESS_BANK_ID 14:10 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL 0x00419e20 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL__PRIV_LEVEL_MASK 0x00419b78 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_0_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_0_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_TASK 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_DONE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_PIXPRF 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_PIXPRF_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_PIXPRF_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_PIXPRF_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_MISS_FIFO 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_MISS_FIFO_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_MISS_FIFO_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CONTROL_SCRUB_MISS_FIFO_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS 0x00419e24 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_0 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1(i) (2+(i)):(2+(i)) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_PIXPRF 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_PIXPRF_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_PIXPRF_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_MISS_FIFO 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_MISS_FIFO_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_MISS_FIFO_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_PIXPRF 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_PIXPRF_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_PIXPRF_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_MISS_FIFO 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_MISS_FIFO_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_MISS_FIFO_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT 0x00419e28 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT 0x00419e2c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS 0x00419e30 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_SM_ID 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_STRUCT 14:13 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_STRUCT_EL1 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_STRUCT_PIXPRF 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_STRUCT_MISS_FIFO_T2D 0x2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_STRUCT_MISS_FIFO_W2D 0x3 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_EL1_BANK_ID 7:6 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_EL1_SET_ID 5:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_BANK_ID 7:6 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_SET_ID 5:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_PIXPRF_SM_ID 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_PIXPRF_STRUCT 14:13 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_PIXPRF_BANK_ID 9:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_PIXPRF_ROW 6:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_L1_TAG_ECC_ADDRESS_MISS_FIFO_SUBFIFO 12:10 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL 0x00419e34 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL__PRIV_LEVEL_MASK 0x00419b78 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM0_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM0_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM0 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM0_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM0_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM_TASK 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM_DONE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM(i) (2+(i)):(2+(i)) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM_TASK 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM_INIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM_DONE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS 0x00419e38 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM0 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM0 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM0 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM0_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM(i) (i):(i) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM(i) (2+(i)):(2+(i)) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM(i) (4+(i)):(4+(i)) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM(i) (6+(i)):(6+(i)) /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM_NOT_PENDING 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM_PENDING 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CORRECTED_ERR_COUNT 0x00419e3c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_UNCORRECTED_ERR_COUNT 0x00419e40 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_ADDRESS 0x00419e44 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_ADDRESS_INDEX 12:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_ADDRESS_SM_ID 12:12 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_ADDRESS_STRUCT 11:11 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_ADDRESS_STRUCT_WARP 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_ADDRESS_STRUCT_BARRIER 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_CBU_ECC_ADDRESS_ROW 10:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL 0x00419e48 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL__PRIV_LEVEL_MASK 0x00419b78 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_SCRUB_L1_DATA 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_SCRUB_L1_DATA_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_SCRUB_L1_DATA_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_SCRUB_L1_DATA_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS 0x00419e4c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_L1_DATA 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_L1_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_L1_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_L1_DATA 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_L1_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_L1_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CORRECTED_ERR_COUNT 0x00419e50 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT 0x00419e54 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_ADDRESS 0x00419e58 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_ADDRESS_SM_ID 17:17 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_ADDRESS_STRUCT 16:16 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_ADDRESS_STRUCT_L1 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_ADDRESS_SUBSTRUCT 14:14 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_ADDRESS_SUBSTRUCT_DATA 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_ADDRESS_QUAD_ID 13:12 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_ICACHE_ECC_ADDRESS_ROW 10:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL 0x00419b84 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL__PRIV_LEVEL_MASK 0x00419b78 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_DATA 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_DATA_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_DATA_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_DATA_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_PREDECODE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_PREDECODE_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_PREDECODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_PREDECODE_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_SCRUB_URF_DATA 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_SCRUB_URF_DATA_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_SCRUB_URF_DATA_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_SCRUB_URF_DATA_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS 0x00419b88 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_DATA 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_PREDECODE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_PREDECODE_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_PREDECODE_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_URF_DATA 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_URF_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_URF_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_DATA 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_PREDECODE 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_PREDECODE_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_PREDECODE_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_URF_DATA 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_URF_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_URF_DATA_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CORRECTED_ERR_COUNT 0x00419b8c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT 0x00419b90 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_ADDRESS 0x00419b4c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_ADDRESS_URF_DATA 0x00000002 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_ADDRESS_SM_ID 17:17 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_ADDRESS_STRUCT 16:14 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_ADDRESS_STRUCT_L0IC_DATA 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_ADDRESS_STRUCT_L0IC_PREDECODE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_ADDRESS_QUAD_ID 13:12 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_RAMS_ECC_ADDRESS_ROW 10:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL 0x00419e5c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0_USE_TAG 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0_USE_TAG_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0_USE_TAG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0_USE_TAG_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0_TAG_USE_SM_ID 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0_TAG_USE_SM_ID_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0_TAG_USE_SM_ID_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0_TAG_USE_SM_ID_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0TC_SLOW_REQUEST 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0TC_SLOW_REQUEST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0TC_SLOW_REQUEST_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0TC_SLOW_REQUEST_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TIF_PER_SM_TICKET 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TIF_PER_SM_TICKET_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TIF_PER_SM_TICKET_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TIF_PER_SM_TICKET_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD 6:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_4 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_8 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_16 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RCT_SHEAR_TRANSFORM_PRECISION 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RCT_SHEAR_TRANSFORM_PRECISION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RCT_SHEAR_TRANSFORM_PRECISION_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RCT_SHEAR_TRANSFORM_PRECISION_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_CNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_CNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_CNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TCKT_CLR_WAIT_ON_HPIPE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TCKT_CLR_WAIT_ON_HPIPE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TCKT_CLR_WAIT_ON_HPIPE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TCKT_CLR_WAIT_ON_HPIPE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0CC_REQ_HIGH_PRIORITY 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0CC_REQ_HIGH_PRIORITY_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0CC_REQ_HIGH_PRIORITY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0CC_REQ_HIGH_PRIORITY_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD 14:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_CNT1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_CNT2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_CNT3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_MEMARB_L1C_HASH_USE_SM_ID 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_MEMARB_L1C_HASH_USE_SM_ID_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_MEMARB_L1C_HASH_USE_SM_ID_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_MEMARB_L1C_HASH_USE_SM_ID_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RTT_TRIANGLE_PAIR_SUPPORT 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RTT_TRIANGLE_PAIR_SUPPORT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RTT_TRIANGLE_PAIR_SUPPORT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RTT_TRIANGLE_PAIR_SUPPORT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE 19:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_VAL1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_VAL2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_VAL3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_VAL4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE 22:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_VAL1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_VAL2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_VAL3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_VAL4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RMU_RAY_ACTV_ERROR_CHECK 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RMU_RAY_ACTV_ERROR_CHECK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RMU_RAY_ACTV_ERROR_CHECK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RMU_RAY_ACTV_ERROR_CHECK_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TIF_GREEDY_TCKT_ALLOCATE 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TIF_GREEDY_TCKT_ALLOCATE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TIF_GREEDY_TCKT_ALLOCATE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_TIF_GREEDY_TCKT_ALLOCATE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_MEMARB_L1C_HASH 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_MEMARB_L1C_HASH_CHOICE0 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_MEMARB_L1C_HASH_CHOICE1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_MEMARB_L1C_HASH_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RCT_FRA_SUPPORT 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RCT_FRA_SUPPORT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RCT_FRA_SUPPORT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_RCT_FRA_SUPPORT_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_SPARE 31:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL_SPARE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2 0x00419e60 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_CLR_TCKT_ON_RFA_STATUS 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_CLR_TCKT_ON_RFA_STATUS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_CLR_TCKT_ON_RFA_STATUS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_CLR_TCKT_ON_RFA_STATUS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_CLR_RAY_ON_RFA_STATUS 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_CLR_RAY_ON_RFA_STATUS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_CLR_RAY_ON_RFA_STATUS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_CLR_RAY_ON_RFA_STATUS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_CLR_L0_ON_RFA_STATUS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_CLR_L0_ON_RFA_STATUS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_CLR_L0_ON_RFA_STATUS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_CLR_L0_ON_RFA_STATUS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_FORCE_TTU_TIMEOUT 4:4 /* -WIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_FORCE_TTU_TIMEOUT_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_FORCE_TTU_TIMEOUT_INIT 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC1_WATERMARK 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC1_WATERMARK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC1_WATERMARK_MIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC1_WATERMARK_MAX 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC1_WATERMARK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC2_WATERMARK 11:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC2_WATERMARK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC2_WATERMARK_MIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC2_WATERMARK_MAX 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC2_WATERMARK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC3_WATERMARK 15:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC3_WATERMARK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC3_WATERMARK_MIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC3_WATERMARK_MAX 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC3_WATERMARK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC4_WATERMARK 19:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC4_WATERMARK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC4_WATERMARK_MIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC4_WATERMARK_MAX 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_RESRC4_WATERMARK_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_SPARE 31:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_CTRL2_SPARE_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL 0x00419e64 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_DBG0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_DBG1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_DBG2 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_SINGLE_PASS0 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_SINGLE_PASS1 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_STATIC_PATTERN0 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_STATIC_PATTERN1 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_SIGDUMP_DEBUG 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP25 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP26 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP27 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP28 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP29 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP30 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP31 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP32 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_GRP33 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_APM_GROUP_7 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_APM_GROUP_6 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_APM_GROUP_5 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_APM_GROUP_4 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_APM_GROUP_3 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_APM_GROUP_2 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_APM_GROUP_1 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_APM_GROUP_0 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_ENABLE 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TTU_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS 0x00419e70 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SFE 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SFE_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SFE_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SFE_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SFE_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SFE_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SFE_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SFE_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL0 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL0_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL0_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL1 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL1_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_SCTL1_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C0 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C0_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C0_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C1 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C1_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_L1C1_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM0 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM0_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM0_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM1 20:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM1_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXAM1_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF0 23:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF0_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF0_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF1 26:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF1_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TEXDF1_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TTU 29:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TTU_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TTU_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TTU_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TTU_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TTU_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TTU_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_STATUS_TTU_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS 0x00419e74 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA0 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA0_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA0_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA1 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA1_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_RFA1_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_SMGR 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_SMGR_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_SMGR_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_SMGR_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_SMGR_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_SMGR_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_SMGR_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_SMGR_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_MMISC 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_MMISC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_MMISC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_MMISC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_MMISC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_MMISC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_MMISC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_MMISC_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PFET 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PFET_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PFET_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PFET_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PFET_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PFET_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PFET_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PFET_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_ICC 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_ICC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_ICC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_ICC_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_ICC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_ICC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_ICC_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_ICC_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_GIF 20:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_GIF_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_GIF_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_GIF_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_GIF_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_GIF_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_GIF_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_GIF_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER0 23:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER0_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER0_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER0_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER0_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER0_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER0_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER0_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER1 26:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER1_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER1_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER1_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER1_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER1_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER1_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_SFE_STATUS_PROFILER1_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEX_CTRL 0x00419a14 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEX_CTRL_TEXAM_BLCG_INPUT_CTRL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEX_CTRL_TEXAM_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEX_CTRL_TEXAM_BLCG_INPUT_CTRL_INCLUDE_RFA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEX_CTRL_TEXAM_BLCG_INPUT_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEX_CTRL_TEXDF_BLCG_INPUT_CTRL 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEX_CTRL_TEXDF_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEX_CTRL_TEXDF_BLCG_INPUT_CTRL_INCLUDE_RFA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEX_CTRL_TEXDF_BLCG_INPUT_CTRL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEX_CTRL_SPARE 31:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM_TEX_CTRL_SPARE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_STATUS0 0x00419e80 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_STATUS0_SM_IN_TRAP_MODE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_STATUS0_SM_IN_TRAP_MODE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_STATUS0_LOCKED_DOWN 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_STATUS0_LOCKED_DOWN_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_STATUS0_LOCKED_DOWN_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0 0x00419e84 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_DEBUGGER_MODE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_DEBUGGER_MODE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_SINGLE_STEP_MODE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_SINGLE_STEP_MODE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_SINGLE_STEP_MODE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW 10:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW_256 0x8 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW 14:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT 29:29 /* -WIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_INIT 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_RUN_TRIGGER 30:30 /* -WIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_RUN_TRIGGER_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_RUN_TRIGGER_TASK_INIT 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_STOP_TRIGGER 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_WARP_VALID_MASK_0 0x00419e88 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_WARP_VALID_MASK_0_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_WARP_VALID_MASK_1 0x00419e8c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_WARP_VALID_MASK_1_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK_0 0x00419e90 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK_0_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK_1 0x00419e94 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK_1_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_TRAP_MASK_0 0x00419e98 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_TRAP_MASK_0_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_TRAP_MASK_1 0x00419e9c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_TRAP_MASK_1_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_0 0x00419ea0 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_0_LO_VALUE 31:0 /* R-IUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_0_LO_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_0_TEX_IDX 19:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_0_COMPONENTS 26:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_0_VA_IN_PAGE 24:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_0_REQ_TYPE 27:27 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_0_REQ_TYPE_SURFTEX 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_0_REQ_TYPE_LG 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_1 0x00419ea4 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_1_HI_VALUE 31:0 /* R-IUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_1_HI_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_1_D_SLOT_ID 9:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_1_MASK_ROTATE_RIGHT 11:10 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_1_MEMORY_LAYOUT 12:12 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_1_SZ_SWAP 15:13 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_1_KIND 23:16 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_ADDR_1_APERTURE 25:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK 0x00419ea8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_NACK 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_ARRIVE 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_ARRIVE_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK_ARRIVE_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK 0x00419eac /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR 0x00419eb0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_NONE 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_API_STACK_ERROR 0x0002 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_MISALIGNED_PC 0x0005 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_PC_OVERFLOW 0x0006 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_MISALIGNED_REG 0x0008 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_ENCODING 0x0009 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_PARAM 0x000b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_OOR_REG 0x000d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_OOR_ADDR 0x000e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_MISALIGNED_ADDR 0x000f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_INVALID_ADDR_SPACE 0x0010 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_INVALID_CONST_ADDR_LDC 0x0012 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_MMU_FAULT 0x0017 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_TEX_FORMAT 0x0018 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_TEX_LAYOUT 0x0019 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_MMU_NACK 0x0020 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ERROR_ARRIVE 0x0021 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_WARP_ID 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_WARP_ID_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE 27:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_NONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_OVERFLOW_ADDR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_OVERFLOW_ADDR 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_WINDOW_BTWN_HI_LO 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_LOCAL_WINDOW_BTWN_HI_LO 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_GLOBAL_MISALIGN_ADDR 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_LOCAL_MISALIGN_ADDR 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_SURF_OOR_ADDR 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_FAULT 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_FORMAT 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_LAYOUT 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_NACK 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_SHARED_OVERFLOW_ADDR 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_SHARED_MISALIGN_ADDR 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR 0x00419eb4 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_BPT_INT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_BPT_INT_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_BPT_INT_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_BPT_PAUSE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_BPT_PAUSE_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_ERROR_IN_TRAP_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_ERROR_IN_TRAP_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_POISON_DATA 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_POISON_DATA_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_POISON_DATA_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_PC 0x00419eb8 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_PC_VALUE 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_PC_HI 0x00419ebc /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_PC_HI_VALUE 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_PM_SAMP_STATE 0x00419ec0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_PM_SAMP_STATE_SUBP0 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_PM_SAMP_STATE_SUBP0_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_PM_SAMP_STATE_SUBP1 11:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_PM_SAMP_STATE_SUBP1_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_PM_SAMP_STATE_SUBP2 17:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_PM_SAMP_STATE_SUBP2_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_PM_SAMP_STATE_SUBP3 23:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_PM_SAMP_STATE_SUBP3_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_PM_SAMP_STATE_CORE 25:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_PM_SAMP_STATE_CORE_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET 0x00419ee0 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET_SR64_PREEMPTION_SAVE 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET_SR64_PREEMPTION_RESTORE 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET_OBSERVE_CYA_0 24:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET_OBSERVE_CYA_1 25:25 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET_OBSERVE_CYA_2 26:26 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET_OBSERVE_CYA_3 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET_OBSERVE_CYA_4 28:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET_OBSERVE_CYA_5 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET_OBSERVE_CYA_6 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET_OBSERVE_CYA_7 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET_OBSERVE_CYA_8 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_ESR_FET_OBSERVE_CYA_9 23:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS 0x00419ee4 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTUALLY_QUIESCENT 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS 0x00419ee8 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_HALTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_FAULTEDED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_INFO 0x00419eec /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_INFO_VEID 5:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_ESR_INFO_VEID_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_STATUS0 0x00419f00 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_STATUS0_SM_IN_TRAP_MODE_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_STATUS0_SM_IN_TRAP_MODE_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_STATUS0_LOCKED_DOWN 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_STATUS0_LOCKED_DOWN_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_STATUS0_LOCKED_DOWN_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0 0x00419f04 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_DEBUGGER_MODE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_DEBUGGER_MODE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_SINGLE_STEP_MODE 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_SINGLE_STEP_MODE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_SINGLE_STEP_MODE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW 10:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW_256 0x8 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW 14:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW_INIT 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT 29:29 /* -WIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_INIT 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_RUN_TRIGGER 30:30 /* -WIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_RUN_TRIGGER_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_RUN_TRIGGER_TASK_INIT 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_STOP_TRIGGER 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_WARP_VALID_MASK_0 0x00419f08 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_WARP_VALID_MASK_0_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_WARP_VALID_MASK_1 0x00419f0c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_WARP_VALID_MASK_1_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_BPT_PAUSE_MASK_0 0x00419f10 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_BPT_PAUSE_MASK_0_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_BPT_PAUSE_MASK_1 0x00419f14 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_BPT_PAUSE_MASK_1_V 31:0 /* RWXVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_BPT_TRAP_MASK_0 0x00419f18 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_BPT_TRAP_MASK_0_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_BPT_TRAP_MASK_1 0x00419f1c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_DBGR_BPT_TRAP_MASK_1_V 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_0 0x00419f20 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_0_LO_VALUE 31:0 /* R-IUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_0_LO_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_0_TEX_IDX 19:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_0_COMPONENTS 26:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_0_VA_IN_PAGE 24:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_0_REQ_TYPE 27:27 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_0_REQ_TYPE_SURFTEX 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_0_REQ_TYPE_LG 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_1 0x00419f24 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_1_HI_VALUE 31:0 /* R-IUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_1_HI_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_1_D_SLOT_ID 9:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_1_MASK_ROTATE_RIGHT 11:10 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_1_MEMORY_LAYOUT 12:12 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_1_SZ_SWAP 15:13 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_1_KIND 23:16 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_ADDR_1_APERTURE 25:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK 0x00419f28 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_NACK 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_ARRIVE 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_ARRIVE_REPORT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_REPORT_MASK_ARRIVE_NO_REPORT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK 0x00419f2c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_NO_REPORT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_REPORT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR 0x00419f30 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_NONE 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_API_STACK_ERROR 0x0002 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_MISALIGNED_PC 0x0005 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_PC_OVERFLOW 0x0006 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_MISALIGNED_REG 0x0008 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_ENCODING 0x0009 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_PARAM 0x000b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_OOR_REG 0x000d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_OOR_ADDR 0x000e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_MISALIGNED_ADDR 0x000f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_INVALID_ADDR_SPACE 0x0010 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_INVALID_CONST_ADDR_LDC 0x0012 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_MMU_FAULT 0x0017 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_TEX_FORMAT 0x0018 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_TEX_LAYOUT 0x0019 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_MMU_NACK 0x0020 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ERROR_ARRIVE 0x0021 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_WARP_ID 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_WARP_ID_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE 27:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_NONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_OVERFLOW_ADDR 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_OVERFLOW_ADDR 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_WINDOW_BTWN_HI_LO 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_LOCAL_WINDOW_BTWN_HI_LO 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_GLOBAL_MISALIGN_ADDR 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_LOCAL_MISALIGN_ADDR 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_SURF_OOR_ADDR 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_FAULT 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_FORMAT 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_LAYOUT 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_NACK 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_SHARED_OVERFLOW_ADDR 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_SHARED_MISALIGN_ADDR 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR 0x00419f34 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_BPT_INT 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_BPT_INT_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_BPT_INT_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_BPT_PAUSE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_BPT_PAUSE_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_ERROR_IN_TRAP_NOT_PENDING 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_ERROR_IN_TRAP_PENDING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_POISON_DATA 12:12 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_POISON_DATA_NOT_PENDING 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_GLOBAL_ESR_POISON_DATA_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_PC 0x00419f38 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_PC_VALUE 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_PC_HI 0x00419f3c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_WARP_ESR_PC_HI_VALUE 31:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_PM_SAMP_STATE 0x00419f40 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_PM_SAMP_STATE_SUBP0 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_PM_SAMP_STATE_SUBP0_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_PM_SAMP_STATE_SUBP1 11:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_PM_SAMP_STATE_SUBP1_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_PM_SAMP_STATE_SUBP2 17:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_PM_SAMP_STATE_SUBP2_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_PM_SAMP_STATE_SUBP3 23:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_PM_SAMP_STATE_SUBP3_INIT 0x00 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_PM_SAMP_STATE_CORE 25:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_PM_SAMP_STATE_CORE_INIT 0x0 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET 0x00419f60 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET_SR64_PREEMPTION_SAVE 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET_SR64_PREEMPTION_RESTORE 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET_OBSERVE_CYA_0 24:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET_OBSERVE_CYA_1 25:25 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET_OBSERVE_CYA_2 26:26 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET_OBSERVE_CYA_3 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET_OBSERVE_CYA_4 28:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET_OBSERVE_CYA_5 29:29 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET_OBSERVE_CYA_6 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET_OBSERVE_CYA_7 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET_OBSERVE_CYA_8 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_ESR_FET_OBSERVE_CYA_9 23:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS 0x00419f64 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTUALLY_QUIESCENT 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS 0x00419f68 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_HAULTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_HALTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_FAULTEDED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_INFO 0x00419f6c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_INFO_VEID 5:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_SM0_HWW_ESR_INFO_VEID_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG 0x00419a00 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_HEADER_TAGMODE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_HEADER_TAGMODE_AUTO 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_HEADER_TAGMODE_MISS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_SAMPLER_TAGMODE 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_SAMPLER_TAGMODE_AUTO 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_SAMPLER_TAGMODE_MISS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FORCE_INVALIDATE 10:10 /* -WIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FORCE_INVALIDATE_RESET 0x0 /* -WI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FORCE_INVALIDATE_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_TSL1_ENTRIES 15:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_TSL1_ENTRIES_FULL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_ZERO_OFFSET_OPT 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_ZERO_OFFSET_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_ZERO_OFFSET_OPT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_INVAL_3D_TSL1_ON_TEX_IN_2D 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_INVAL_3D_TSL1_ON_TEX_IN_2D_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_INVAL_3D_TSL1_ON_TEX_IN_2D_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_TSL1_RVCH_INVALIDATE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_TSL1_RVCH_INVALIDATE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_TSL1_RVCH_INVALIDATE__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_SURFACE_USE_FAST_POINT_SAMPLE_PATH 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_SURFACE_USE_FAST_POINT_SAMPLE_PATH_ENABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_SURFACE_USE_FAST_POINT_SAMPLE_PATH_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_SNORM 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_SNORM_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_SNORM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_FP16_RETURN 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_FP16_RETURN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_FP16_RETURN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_ARRAY 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_ARRAY_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_ARRAY_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_MIP_FILTER 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_MIP_FILTER_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_MIP_FILTER_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_BORDER_COLOR 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_BORDER_COLOR_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_BORDER_COLOR_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_CACHE_LAYOUT 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_CACHE_LAYOUT_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_CACHE_LAYOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_1D_BUFFER 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_1D_BUFFER_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_1D_BUFFER_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_COLOR_KEY_OP 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_COLOR_KEY_OP_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_COLOR_KEY_OP_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG 0x00419a04 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_CUBEMAP_ANISO 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_CUBEMAP_ANISO_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_CUBEMAP_ANISO_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_CUBESEAM_ANISO 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_CUBESEAM_ANISO_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_CUBESEAM_ANISO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_UNOPT_LOD_CLAMP 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_UNOPT_LOD_CLAMP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_UNOPT_LOD_CLAMP_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_SERIALIZE_TXL 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_SERIALIZE_TXL_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_SERIALIZE_TXL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_SERIALIZE_TXB 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_SERIALIZE_TXB_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_SERIALIZE_TXB_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_SERIALIZE_LC 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_SERIALIZE_LC_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_LOD_DBG_SERIALIZE_LC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG 0x00419a08 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_NOP_OPT 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_NOP_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_NOP_OPT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_SAMPSTAT 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_SAMPSTAT_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_SAMPSTAT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_UNOPT_LOD_SPREAD 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_UNOPT_LOD_SPREAD_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_UNOPT_LOD_SPREAD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_COMPATIBILITY_PRECISION 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_COMPATIBILITY_PRECISION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_COMPATIBILITY_PRECISION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_FILTER_64B 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_FILTER_64B_FULL_SPEED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_FILTER_64B_HALF_SPEED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_FILTER_64B_ANISO_HALF_SPEED 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_W_WEIGHT_CG_OPT 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_W_WEIGHT_CG_OPT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_DBG_W_WEIGHT_CG_OPT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL 0x00419ab0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL 6:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP0 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_SINGLE_PASS0 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_SINGLE_PASS_COMPUTE 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_STATIC_PATTERN0 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_STATIC_PATTERN1 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_SINGLE_PASS1 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_GRP28 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_APM_GROUP_7 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_APM_GROUP_6 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_APM_GROUP_5 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_APM_GROUP_4 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_APM_GROUP_3 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_APM_GROUP_2 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_APM_GROUP_1 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_APM_GROUP_0 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_ENABLE 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG 0x00419a0c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SUBSET_PICK 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SUBSET_PICK_AUTO 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SUBSET_PICK_ZERO 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SUBSET_PICK_ZERO_TO_ONE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_1B 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_1B_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_2B 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_2B_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_4B 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_4B_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_8B 11:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_8B_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_12B 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_12B_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_16B 15:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_16B_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_DXT1 17:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_DXT1_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_DXT2 19:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_SETFUNC_DXT2_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_T2D_COMPRESSION 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_T2D_COMPRESSION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_T2D_COMPRESSION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_RLAT_DEPTH_DIV8 26:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_DBG_RLAT_DEPTH_DIV8_FULL 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_DBG 0x00419a10 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_DBG_LATFIFO_DEPTH_DIV4 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_DBG_LATFIFO_DEPTH_DIV4_FULL 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG 0x00419a1c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_ROWCOL_SERIAL 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_ROWCOL_SERIAL_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_ROWCOL_SERIAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_BANK_SERIAL 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_BANK_SERIAL_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_BANK_SERIAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_CONVERT_NEAREST_AS_TLD 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_CONVERT_NEAREST_AS_TLD_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_CONVERT_NEAREST_AS_TLD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_CONVERT_NEAREST_AS_TLD__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_FILTER_64B 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_FILTER_64B_FULL_SPEED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_FILTER_64B_HALF_SPEED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_FILTER_64B_ANISO_HALF_SPEED 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_COMPUTE_CONVERT_NEAREST_AS_TLD 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_COMPUTE_CONVERT_NEAREST_AS_TLD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_COMPUTE_CONVERT_NEAREST_AS_TLD_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_CACHE_QUIET_READ 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_CACHE_QUIET_READ_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_CACHE_QUIET_READ_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_SLCG_OVERRIDE 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_SLCG_OVERRIDE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_SLCG_OVERRIDE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_SLCG_IDLE_EN 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_SLCG_IDLE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_SLCG_IDLE_EN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_SLCG_STALL_EN 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_SLCG_STALL_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_SLCG_STALL_EN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_LG_EXPAND_BILERP 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_LG_EXPAND_BILERP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_DBG_LG_EXPAND_BILERP_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00419acc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG 0x00419a20 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_DRN_SUBP_OLDEST_BLOCK 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_DRN_SUBP_OLDEST_BLOCK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_DRN_SUBP_OLDEST_BLOCK_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_CP_DRNLOCK 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_CP_DRNLOCK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_CP_DRNLOCK_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_CP2_BOOST 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_CP2_BOOST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_CP2_BOOST_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_CP3_BOOST 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_CP3_BOOST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_CP3_BOOST_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_CP4_RECYCLE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_CP4_RECYCLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_CP4_RECYCLE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_NONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_2 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_8 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_16 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_24 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_32 0x5 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_64 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_128 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_FB_SECTOR_SERIAL 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_FB_SECTOR_SERIAL_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_FB_SECTOR_SERIAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_MIW_READ_PACKING_EN 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_MIW_READ_PACKING_EN_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_MIW_READ_PACKING_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_ONLY_ONE_FB_REQ 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_ONLY_ONE_FB_REQ_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_ONLY_ONE_FB_REQ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_L1TAG_DESC_EVICT_LAST 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_L1TAG_DESC_EVICT_LAST_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_L1TAG_DESC_EVICT_LAST_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_INJECT_MEMBAR_PRIORITY 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_INJECT_MEMBAR_PRIORITY_HIGH 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_INJECT_MEMBAR_PRIORITY_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_FB_STENCIL_SERIAL 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_FB_STENCIL_SERIAL_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_FB_STENCIL_SERIAL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_L1TAG_CTRL_CACHE_TTU 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_L1TAG_CTRL_CACHE_TTU_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_L1TAG_CTRL_CACHE_TTU_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_MIW_WRITE_CONCAT_EN 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_MIW_WRITE_CONCAT_EN_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_MIW_WRITE_CONCAT_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_MEMBAR_SYNC_IN_L1MISS 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_MEMBAR_SYNC_IN_L1MISS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_MEMBAR_SYNC_IN_L1MISS_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_NACK_RESP 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_NACK_RESP_KILL_ALL_BUT_MEMBAR_CORRECT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_NACK_RESP_KILL_ALL_CORRECT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_SCO_GPU_AS_STRONG 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_SCO_GPU_AS_STRONG_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_SCO_GPU_AS_STRONG_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE 20:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE_OUT_OF_ORD 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE_TEXLG_LH 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE_TEXLG_TQ01 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE_IN_ORDER 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_FPS_TEXTLD_AS_SURF 21:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_FPS_TEXTLD_AS_SURF_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_FPS_TEXTLD_AS_SURF_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_GNIC_POISON_IGNORE 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_GNIC_POISON_IGNORE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_GNIC_POISON_IGNORE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_SLCG_OVERRIDE 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_SLCG_OVERRIDE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_SLCG_OVERRIDE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_SLCG_IDLE_EN 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_SLCG_IDLE_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_SLCG_IDLE_EN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_SLCG_STALL_EN 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_SLCG_STALL_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_SLCG_STALL_EN_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_MIW_READ_CMD_HOLDOFF 30:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_MIW_READ_CMD_HOLDOFF_ZERO 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG_MIW_READ_CMD_HOLDOFF_INIT 0x07 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG2 0x00419a3c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG2_L1TAG_DESC_INVERT_MASK 23:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG2_L1TAG_DESC_INVERT_MASK_DEFAULT 0x3718d /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG2_L1TAG_DESC_INVERT_MASK_GA100 0x3718d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG2_MIW_PAUSED_OVERRIDE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG2_MIW_PAUSED_OVERRIDE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_DBG2_MIW_PAUSED_OVERRIDE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_ROUTING 0x00419ac4 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_ROUTING_SEL 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_ROUTING_SEL_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_ROUTING_SEL_PIPE0 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_ROUTING_SEL_PIPE1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_ROUTING_SEL__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE 0x00419ac8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE_LG 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE_LG_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE_LG_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE_TEX 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE_TEX_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE_TEX_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE_RESET_L1 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE_RESET_L1_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE_RESET_L1_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE_CBUF_FLUSH 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE_CBUF_FLUSH_DEFAULT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_T_DBG2_L1_DATA_INVALIDATE_CBUF_FLUSH_ENABLE 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_DBG 0x00419a30 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_DBG_MADD_64B_LANA_CYA 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_DBG_MADD_64B_LANA_CYA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_DBG_MADD_64B_LANA_CYA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_DBG_FP16_ROUNDING_MODE 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_DBG_FP16_ROUNDING_MODE_INSTR 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_DBG_FP16_ROUNDING_MODE_FORCE_RTZ 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_DBG_FP16_ROUNDING_MODE_FORCE_RTNE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_DBG_PS_BYPASS 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_DBG_PS_BYPASS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_DBG_PS_BYPASS_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS 0x00419a38 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TEXIN 10:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_F 13:11 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_F_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_F_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_F_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_F_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_F_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_D 16:14 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_D_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_D_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_D_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_D_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_D_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TM 19:17 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TM_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TM_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TM_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TM_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TM_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_X 22:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_X_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_X_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_X_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_X_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_X_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TEXIO 25:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_W 28:26 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_W_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_W_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_W_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_W_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_W_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_MIPB 31:29 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_MIPB_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_MIPB_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_MIPB_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_MIPB_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_TEX_SUBUNITS_STATUS_MIPB_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACT_INDEX 0x00419aa8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACT_INDEX__PRIV_LEVEL_MASK 0x00419acc /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACT_INDEX_INDEX 7:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACT_INDEX_INDEX_ZERO 0x00 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACT_INDEX_INDEX_MIN 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACT_INDEX_INDEX_MAX 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACT_DATA 0x00419aac /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACT_DATA__PRIV_LEVEL_MASK 0x00419acc /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACT_DATA__APERTURE_INDEX_OFFSET 0xfffffffc /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACT_DATA_DATA 27:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_M_BLK_ACT_DATA_DATA_INIT 0x0000000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_0 0x00419e00 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_0_BASE_ADDR_43_12 31:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_0_BASE_ADDR_43_12_INIT 0x00000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_1 0x00419e04 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_1_SIZE_DIV_128B 20:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_1_SIZE_DIV_128B_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_1_SIZE_DIV_128B_GRANULARITY 0x000080 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_1_BASE_ADDR_48_44 28:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_1_BASE_ADDR_48_44_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_1_LTC_CLASS 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_1_LTC_CLASS_PASS_THRU 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_1_LTC_CLASS_EVICT_LAST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_1_VALID 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_1_VALID_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_RM_CB_1_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG 0x00419a40 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG1 0x00419a44 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG1_SLCG 3:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG1_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG1_SLCG_DISABLED 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IN_CG1_SLCG__PROD 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG 0x00419a48 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG1 0x00419a4c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_SAMP_CG1_SLCG__PROD 0xfc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG 0x00419a50 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG1 0x00419a54 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG1_SLCG 5:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG1_SLCG_DISABLED 0x1f /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_X_CG1_SLCG__PROD 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG 0x00419a58 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG1 0x00419a5c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG1_SLCG 3:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG1_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG1_SLCG_DISABLED 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_W_CG1_SLCG__PROD 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG 0x00419a60 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG1 0x00419a64 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_D_CG1_SLCG__PROD 0xd3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG 0x00419a68 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG1 0x00419a6c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_IO_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG 0x00419a78 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG1 0x00419a7c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG1_SLCG 5:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG1_SLCG_DISABLED 0x1f /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_F_CG1_SLCG__PROD 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG 0x00419a80 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG1 0x00419a84 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG1_SLCG 3:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG1_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG1_SLCG_DISABLED 0x7 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_MIPB_CG1_SLCG__PROD 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG 0x00419a70 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_IDLE_CG_DLY_CNT__PROD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_STALL_CG_DLY_CNT__PROD 0x05 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG1 0x00419a74 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_AM_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG 0x00419a88 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_IDLE_CG_DLY_CNT__PROD 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_STALL_CG_DLY_CNT__PROD 0x05 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG1 0x00419a8c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_TEX_DF_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC 0x00419c7f:0x00419c00 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x00419c00 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_SINGLE_ISBE_ALLOC 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_SINGLE_ISBE_ALLOC_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_SINGLE_ISBE_ALLOC_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_BUNDLE_FILTER 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_BUNDLE_FILTER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_BUNDLE_FILTER_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_SET_COUNTERS 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_SET_COUNTERS_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_SET_COUNTERS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_VSB_ISBE_SHARED 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_VSB_ISBE_SHARED_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_VSB_ISBE_SHARED_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_CYA_RESET_ISBE_BASE 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_CYA_RESET_ISBE_BASE_ENABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_CYA_RESET_ISBE_BASE_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_FORCE_GLOBAL_CACHE 7:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_FORCE_GLOBAL_CACHE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_FORCE_GLOBAL_CACHE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_FORCE_GLOBAL_CACHE_USE_SPH 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_OCCUPANCY_SEL 10:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_OCCUPANCY_SEL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_OCCUPANCY_SEL_PIX_QUADS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_OCCUPANCY_SEL_PIX_DRAIN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_OCCUPANCY_SEL_OVERALL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_OCCUPANCY_SEL_UNDEFINED 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_SPARE 31:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_SPARE_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG 0x00419c04 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SINGLE_CTA 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SINGLE_CTA_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SINGLE_CTA_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_PIXOUT_FPW_ILOCK 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_PIXOUT_FPW_ILOCK_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_PIXOUT_FPW_ILOCK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_COMP_BUNDLE_HOLD 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_COMP_BUNDLE_HOLD_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_COMP_BUNDLE_HOLD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_PIX_BUNDLE_HOLD 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_PIX_BUNDLE_HOLD_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_PIX_BUNDLE_HOLD_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_ISC_INSTRUCTION 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_ISC_INSTRUCTION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_ISC_INSTRUCTION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_ISC_DATA 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_ISC_DATA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_ISC_DATA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_ISC_CONSTANT 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_ISC_CONSTANT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SCG_ISC_CONSTANT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_CTA_STEERING 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_CTA_STEERING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_CTA_STEERING_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_FORCE_GLOBAL_CACHE 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_FORCE_GLOBAL_CACHE_OFF 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_FORCE_GLOBAL_CACHE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_FORCE_GLOBAL_CACHE_USE_SPH 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_CTA_QUAD_SKEW 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_CTA_QUAD_SKEW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_CTA_QUAD_SKEW_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_FIRST_SAMP_CENTROID 12:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_FIRST_SAMP_CENTROID_COVERED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_FIRST_SAMP_CENTROID_ALIASED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_FIRST_SAMP_CENTROID_ALWAYS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_CTA_SUBPARTITION_SKEW 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_CTA_SUBPARTITION_SKEW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_CTA_SUBPARTITION_SKEW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_FORCE_PFM_PFC_WORK_TO_ONE_SM 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_FORCE_PFM_PFC_WORK_TO_ONE_SM_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_FORCE_PFM_PFC_WORK_TO_ONE_SM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_2D_3DPFM_SUBTILES_MAX_IN_FLIGHT 21:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_2D_3DPFM_SUBTILES_MAX_IN_FLIGHT_DISABLE 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SPARE 31:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_DEBUG_SPARE_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG 0x00419c08 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_USE_HALF_SM 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_USE_HALF_SM_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_USE_HALF_SM_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_PIX_VTG_ARB_POLICY 5:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_PIX_VTG_ARB_POLICY_PIX_HIGHEST 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_PIX_VTG_ARB_POLICY_VTG_CREDIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_PIX_VTG_ARB_POLICY_LOOSE_PS_TILE_LOCK 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_BUG1693549_FIX 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_BUG1693549_FIX_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_BUG1693549_FIX_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_BUG1693549_STALL_COUNTER 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_BUG1693549_STALL_COUNTER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_BUG1693549_STALL_COUNTER_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING 9:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING_WINDOW_SIZE_15 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING_WINDOW_SIZE_63 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING_WINDOW_SIZE_1023 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_VTG_WINDOW_ADJUST 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_VTG_WINDOW_ADJUST_AGGRESSIVE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_VTG_WINDOW_ADJUST_CONSERVATIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_PIX_WINDOW_ADJUST 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_PIX_WINDOW_ADJUST_AGGRESSIVE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_PIX_WINDOW_ADJUST_CONSERVATIVE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_CNT_SAT_POLICY 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_CNT_SAT_POLICY_STALL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_CNT_SAT_POLICY_NO_SQUASH_ONCE_SAT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_OPEN_2D_BLOCKS_COMP 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_OPEN_2D_BLOCKS_COMP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_OPEN_2D_BLOCKS_COMP_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_2D_COMP_MUTEX_IN_SM 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_2D_COMP_MUTEX_IN_SM_ENABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_2D_COMP_MUTEX_IN_SM_DISABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_SPARE 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_DEBUG_SPARE_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL 0x00419c0c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_STATUS_BLOCK 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_STATUS_SUBUNIT_0 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_STATUS_SUBUNIT_1 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PRI_PIX_OUTSTANDING 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PRI_VTG_OUTSTANDING_0 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PRI_VTG_OUTSTANDING_1 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_STATUS_CG_PG_WAKEUP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_EXT_IFC_0 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_EXT_IFC_1 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_EXT_IFC_2 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_EXT_IFC_3 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_FULL_FIFOS_0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_FULL_FIFOS_1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_FULL_FIFOS_2 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_INTERNAL_PVLD_PRDY_0 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_INTERNAL_PVLD_PRDY_1 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_3 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_4 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_5 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_ATTRIBUTES_REQUESTED_DIV4 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIXEL_RF_ALLOCATIONS 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_NUMBER_OF_SUBTILES_PRIMS_PIXEL_WARPS 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_VTG_THROUGHPUT_0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_VTG_THROUGHPUT_1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_WARP_LAUNCHES_0 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_WARP_LAUNCHES_1 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_WARP_LAUNCHES_2 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_COMPUTE_LAUNCHES 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_COMPUTE_RF_DIV8_ALLOCATED 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_ACTIVE_QUADS_IN_PIX_WARPS 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_0 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_1 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_2 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_3 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_WORK_REMOVAL_0 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_STALL_LIMIT_0 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_STALL_LIMIT_1 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_STALL_LIMIT_2 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_STALL_LIMIT_3 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIX_PIPE_STALL_WLU 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIX_PIPE_STALL_LAUNCH 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIX_PIPE_STALL_INPUT 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIX_PIPE_STALL_TRAM 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIX_DRAIN_OUTSTANDING_0 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIX_DRAIN_OUTSTANDING_1 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIX_DRAIN_OUTSTANDING_2 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIX_DRAIN_OUTSTANDING_3 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIX_STARTXY_OUTSTANDING 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIX_TRAMFILL_OUTSTANDING 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_RESOURCE_LIMIT_0 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_RESOURCE_LIMIT_1 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_INTERNAL_EVENTS_0 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_LATENCY_TRACKING_INTERNAL 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_0 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SM_RESOURCES_1 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_2 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SM_RESOURCES_3 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_4 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_5 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_6 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_7 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_8 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_9 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_10 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SM_RESOURCES_11 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_12 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_13 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_14 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_15 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_16 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SM_SHADER_TYPE_ACTIVE 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_ALPHA_BETA_CLOCKS 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_FIFOS_STALL_0 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_FIFOS_STALL_1 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_FIFOS_STALL_2 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_FIFOS_STALL_3 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_TPC_RESOURCES_0 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_TPC_RESOURCES_1 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_TPC_RESOURCES_3 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_TPC_RESOURCES_4 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_COMPUTE_PIPE_DEBUG_0_2XMIO 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_COMPUTE_PIPE_DEBUG_1_2XMIO 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_COMPUTE_PIPE_DEBUG_2_2XMIO 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_EXTERNAL_SCG_EVENTS 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_ACTIVE_WARP_OCCUPANCY_0 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_ACTIVE_WARP_OCCUPANCY_1 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_ACTIVE_WARP_OCCUPANCY_2 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_ACTIVE_WARP_OCCUPANCY_3 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_VTG_ISBE_OCCUPANCY 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIX_TRAM_OCCUPANCY 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_COMP_FSM_BLOCK_0 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_COMP_FSM_BLOCK_1 0x5e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_COMP_LAUNCH 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_STATIC_PATTERN_123_12_GROUP 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_STATIC_PATTERN_EDC_12_GROUP 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_CILP 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PREFUNC_LATENCIES_0 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PREFUNC_LATENCIES_1 0x64 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PREFUNC_LATENCIES_2 0x65 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PREFUNC_LATENCIES_3 0x66 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_MPC_SCG_DRAIN_GRAPHICS_PROTOCOL 0x67 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIXOUT_IF 0x68 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIXOUT_CANT_DRAIN_REASONS 0x69 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_PIX_COMP_ARB 0x6a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SCG_OCCUPANCY_0 0x6b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SCG_OCCUPANCY_1 0x6c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SCG_OCCUPANCY_2 0x6d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_ENHANCED_L1_0 0x6e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_ENHANCED_L1_1 0x6f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_INTERNAL_EVENTS_1 0x70 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_ARB 0x71 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_0 0x72 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_1 0x73 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_0 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_1 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_2 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_3 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_4 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_5 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_6 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_7 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_8 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_9 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_10 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_11 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_12 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_13 0x81 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_MESHLET_1 0x82 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_MESHLET_2 0x83 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_RMGR_DEBUG_1 0x84 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_RMGR_DEBUG_2 0x85 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_RMGR_DEBUG_3 0x86 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_WLU_ARB_DEBUG 0x87 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_COMPUTE_PERF_TRIAGE_0 0x88 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_COMPUTE_PERF_TRIAGE_1 0x89 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_COMPUTE_PERF_TRIAGE_2 0x8a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SM_PERF_RELATED 0x8b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_0 0x8c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_1 0x8d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_2 0x8e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_3 0x8f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_4 0x90 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_5 0x91 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_6 0x92 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_7 0x93 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_8 0x94 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_9 0x95 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_10 0x96 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_11 0x97 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_12 0x98 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_13 0x99 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_14 0x9a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_15 0x9b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_16 0x9c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_17 0x9d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_18 0x9e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_19 0x9f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_20 0xa0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_14 0xa1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_21 0xa2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_SPASS_0 0xa3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_SPASS_1 0xa4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_SMSCC_SPASS_2 0xa5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_2 0xa6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_3 0xa7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_4 0xa8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_5 0xa9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_APM_GRP_0 0xff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_APM_GRP_1 0xfe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_APM_GRP_2 0xfd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_APM_GRP_3 0xfc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_APM_GRP_4 0xfb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_APM_GRP_5 0xfa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_APM_GRP_6 0xf9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_APM_GRP_7 0xf8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_APM_GRP_8 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_APM_GRP_9 0xf6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_APM_GRP_10 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_APM_GRP_11 0xf4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_STATUS_BLOCK 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_STATUS_SUBUNIT_0 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_STATUS_SUBUNIT_1 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PRI_PIX_OUTSTANDING 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PRI_VTG_OUTSTANDING_0 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PRI_VTG_OUTSTANDING_1 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_STATUS_CG_PG_WAKEUP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_EXT_IFC_0 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_EXT_IFC_1 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_EXT_IFC_2 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_EXT_IFC_3 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_FULL_FIFOS_0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_FULL_FIFOS_1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_FULL_FIFOS_2 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_INTERNAL_PVLD_PRDY_0 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_INTERNAL_PVLD_PRDY_1 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_3 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_4 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_5 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_ATTRIBUTES_REQUESTED_DIV4 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIXEL_RF_ALLOCATIONS 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_NUMBER_OF_SUBTILES_PRIMS_PIXEL_WARPS 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_VTG_THROUGHPUT_0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_VTG_THROUGHPUT_1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_WARP_LAUNCHES_0 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_WARP_LAUNCHES_1 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_WARP_LAUNCHES_2 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_COMPUTE_LAUNCHES 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_COMPUTE_RF_DIV8_ALLOCATED 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_ACTIVE_QUADS_IN_PIX_WARPS 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_0 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_1 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_2 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_3 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_WORK_REMOVAL_0 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_STALL_LIMIT_0 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_STALL_LIMIT_1 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_STALL_LIMIT_2 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_STALL_LIMIT_3 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIX_PIPE_STALL_WLU 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIX_PIPE_STALL_LAUNCH 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIX_PIPE_STALL_INPUT 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIX_PIPE_STALL_TRAM 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIX_DRAIN_OUTSTANDING_0 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIX_DRAIN_OUTSTANDING_1 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIX_DRAIN_OUTSTANDING_2 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIX_DRAIN_OUTSTANDING_3 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIX_STARTXY_OUTSTANDING 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIX_TRAMFILL_OUTSTANDING 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_RESOURCE_LIMIT_0 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_RESOURCE_LIMIT_1 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_INTERNAL_EVENTS_0 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_LATENCY_TRACKING_INTERNAL 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_0 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SM_RESOURCES_1 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_2 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SM_RESOURCES_3 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_4 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_5 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_6 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_7 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_8 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_9 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_10 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SM_RESOURCES_11 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_12 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_13 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_14 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_15 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_16 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SM_SHADER_TYPE_ACTIVE 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_ALPHA_BETA_CLOCKS 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_FIFOS_STALL_0 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_FIFOS_STALL_1 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_FIFOS_STALL_2 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_FIFOS_STALL_3 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_TPC_RESOURCES_0 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_TPC_RESOURCES_1 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_TPC_RESOURCES_3 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_TPC_RESOURCES_4 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_COMPUTE_PIPE_DEBUG_0_2XMIO 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_COMPUTE_PIPE_DEBUG_1_2XMIO 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_COMPUTE_PIPE_DEBUG_2_2XMIO 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_EXTERNAL_SCG_EVENTS 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_ACTIVE_WARP_OCCUPANCY_0 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_ACTIVE_WARP_OCCUPANCY_1 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_ACTIVE_WARP_OCCUPANCY_2 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_ACTIVE_WARP_OCCUPANCY_3 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_VTG_ISBE_OCCUPANCY 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIX_TRAM_OCCUPANCY 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_COMP_FSM_BLOCK_0 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_COMP_FSM_BLOCK_1 0x5e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_COMP_LAUNCH 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_STATIC_PATTERN_123_12_GROUP 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_STATIC_PATTERN_EDC_12_GROUP 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_CILP 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PREFUNC_LATENCIES_0 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PREFUNC_LATENCIES_1 0x64 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PREFUNC_LATENCIES_2 0x65 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PREFUNC_LATENCIES_3 0x66 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_MPC_SCG_DRAIN_GRAPHICS_PROTOCOL 0x67 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIXOUT_IF 0x68 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIXOUT_CANT_DRAIN_REASONS 0x69 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_PIX_COMP_ARB 0x6a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SCG_OCCUPANCY_0 0x6b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SCG_OCCUPANCY_1 0x6c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SCG_OCCUPANCY_2 0x6d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_ENHANCED_L1_0 0x6e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_ENHANCED_L1_1 0x6f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_INTERNAL_EVENTS_1 0x70 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_ARB 0x71 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_0 0x72 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_1 0x73 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_0 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_1 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_2 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_3 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_4 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_5 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_6 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_7 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_8 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_9 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_10 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_11 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_12 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_13 0x81 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_MESHLET_1 0x82 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_MESHLET_2 0x83 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_RMGR_DEBUG_1 0x84 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_RMGR_DEBUG_2 0x85 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_RMGR_DEBUG_3 0x86 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_WLU_ARB_DEBUG 0x87 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_COMPUTE_PERF_TRIAGE_0 0x88 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_COMPUTE_PERF_TRIAGE_1 0x89 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_COMPUTE_PERF_TRIAGE_2 0x8a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SM_PERF_RELATED 0x8b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_0 0x8c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_1 0x8d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_2 0x8e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_3 0x8f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_4 0x90 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_5 0x91 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_6 0x92 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_7 0x93 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_8 0x94 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_9 0x95 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_10 0x96 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_11 0x97 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_12 0x98 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_13 0x99 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_14 0x9a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_15 0x9b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_16 0x9c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_17 0x9d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_18 0x9e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_19 0x9f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_20 0xa0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_14 0xa1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_21 0xa2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_SPASS_0 0xa3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_SPASS_1 0xa4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_SMSCC_SPASS_2 0xa5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_2 0xa6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_3 0xa7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_4 0xa8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_5 0xa9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_APM_GRP_0 0xff /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_APM_GRP_1 0xfe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_APM_GRP_2 0xfd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_APM_GRP_3 0xfc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_APM_GRP_4 0xfb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_APM_GRP_5 0xfa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_APM_GRP_6 0xf9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_APM_GRP_7 0xf8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_APM_GRP_8 0xf7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_APM_GRP_9 0xf6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_APM_GRP_10 0xf5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_APM_GRP_11 0xf4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_STATUS_BLOCK 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_STATUS_SUBUNIT_0 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_STATUS_SUBUNIT_1 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PRI_PIX_OUTSTANDING 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PRI_VTG_OUTSTANDING_0 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PRI_VTG_OUTSTANDING_1 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_STATUS_CG_PG_WAKEUP 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_EXT_IFC_0 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_EXT_IFC_1 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_EXT_IFC_2 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_EXT_IFC_3 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_FULL_FIFOS_0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_FULL_FIFOS_1 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_FULL_FIFOS_2 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_INTERNAL_PVLD_PRDY_0 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_INTERNAL_PVLD_PRDY_1 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_3 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_4 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_5 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_ATTRIBUTES_REQUESTED_DIV4 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIXEL_RF_ALLOCATIONS 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_NUMBER_OF_SUBTILES_PRIMS_PIXEL_WARPS 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_VTG_THROUGHPUT_0 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_VTG_THROUGHPUT_1 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_WARP_LAUNCHES_0 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_WARP_LAUNCHES_1 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_WARP_LAUNCHES_2 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_COMPUTE_LAUNCHES 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_COMPUTE_RF_DIV8_ALLOCATED 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_ACTIVE_QUADS_IN_PIX_WARPS 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_0 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_1 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_2 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_3 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_WORK_REMOVAL_0 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_STALL_LIMIT_0 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_STALL_LIMIT_1 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_STALL_LIMIT_2 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_STALL_LIMIT_3 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIX_PIPE_STALL_WLU 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIX_PIPE_STALL_LAUNCH 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIX_PIPE_STALL_INPUT 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIX_PIPE_STALL_TRAM 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIX_DRAIN_OUTSTANDING_0 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIX_DRAIN_OUTSTANDING_1 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIX_DRAIN_OUTSTANDING_2 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIX_DRAIN_OUTSTANDING_3 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIX_STARTXY_OUTSTANDING 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIX_TRAMFILL_OUTSTANDING 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_RESOURCE_LIMIT_0 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_RESOURCE_LIMIT_1 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_INTERNAL_EVENTS_0 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_LATENCY_TRACKING_INTERNAL 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_0 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SM_RESOURCES_1 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_2 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SM_RESOURCES_3 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_4 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_5 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_6 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_7 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_8 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_9 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_10 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SM_RESOURCES_11 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_12 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_13 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_14 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_15 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_16 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SM_SHADER_TYPE_ACTIVE 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_ALPHA_BETA_CLOCKS 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_FIFOS_STALL_0 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_FIFOS_STALL_1 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_FIFOS_STALL_2 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_FIFOS_STALL_3 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_TPC_RESOURCES_0 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_TPC_RESOURCES_1 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_TPC_RESOURCES_3 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_TPC_RESOURCES_4 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_COMPUTE_PIPE_DEBUG_0_2XMIO 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_COMPUTE_PIPE_DEBUG_1_2XMIO 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_COMPUTE_PIPE_DEBUG_2_2XMIO 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_EXTERNAL_SCG_EVENTS 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_ACTIVE_WARP_OCCUPANCY_0 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_ACTIVE_WARP_OCCUPANCY_1 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_ACTIVE_WARP_OCCUPANCY_2 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_ACTIVE_WARP_OCCUPANCY_3 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_VTG_ISBE_OCCUPANCY 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIX_TRAM_OCCUPANCY 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_COMP_FSM_BLOCK_0 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_COMP_FSM_BLOCK_1 0x5e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_COMP_LAUNCH 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_STATIC_PATTERN_123_12_GROUP 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_STATIC_PATTERN_EDC_12_GROUP 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_CILP 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PREFUNC_LATENCIES_0 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PREFUNC_LATENCIES_1 0x64 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PREFUNC_LATENCIES_2 0x65 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PREFUNC_LATENCIES_3 0x66 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_MPC_SCG_DRAIN_GRAPHICS_PROTOCOL 0x67 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIXOUT_IF 0x68 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIXOUT_CANT_DRAIN_REASONS 0x69 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_PIX_COMP_ARB 0x6a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SCG_OCCUPANCY_0 0x6b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SCG_OCCUPANCY_1 0x6c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SCG_OCCUPANCY_2 0x6d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_ENHANCED_L1_0 0x6e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_ENHANCED_L1_1 0x6f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_INTERNAL_EVENTS_1 0x70 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_ARB 0x71 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_GENERAL_PERF_TRIAGE_0 0x72 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_GENERAL_PERF_TRIAGE_1 0x73 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_0 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_1 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_2 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_3 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_4 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_5 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_6 0x7a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_7 0x7b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_8 0x7c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_9 0x7d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_10 0x7e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_11 0x7f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_12 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_13 0x81 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_MESHLET_1 0x82 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_MESHLET_2 0x83 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_RMGR_DEBUG_1 0x84 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_RMGR_DEBUG_2 0x85 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_RMGR_DEBUG_3 0x86 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_WLU_ARB_DEBUG 0x87 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_COMPUTE_PERF_TRIAGE_0 0x88 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_SM_PERF_RELATED 0x89 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_SEL_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_ENABLE 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM0_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_ENABLE 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_SM1_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_ENABLE 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_TPC_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PM_CTRL_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_STATUS 0x00419c10 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_STATUS_TOP_STATUS 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_STATUS_VTG_STATUS 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_STATUS_PIX_STATUS 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_STATUS_WLU_STATUS 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_STATUS_COMP_STATUS 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_STATUS_RMGR_STATUS 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS 0x00419c14 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_ALPHA_STATUS 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_BETA_STATUS 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_ISBMGR0_STATUS 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_ISBMGR1_STATUS 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_SMIO_STATUS 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_MODE 15:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_MODE_ALPHA 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_MODE_BETA 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_VAFA_OUTSTANDING 16:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_VAFB_OUTSTANDING 17:17 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_VSC_ALPHA_OUTSTANDING 20:20 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_VAF_BETA_OUTSTANDING 21:21 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_TGBFILL_OUTSTANDING 22:22 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_GSPILL_OUTSTANDING 23:23 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_VSC_BETA_OUTSTANDING 24:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_VSA_WARP_OUTSTANDING 25:25 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_VSB_WARP_OUTSTANDING 26:26 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_TI_WARP_OUTSTANDING 27:27 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_TS_WARP_OUTSTANDING 28:28 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_GS_WARP_OUTSTANDING 29:29 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_CBMGR_OUTSTANDING 30:30 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS 0x00419c18 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_TRAM_STATUS 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_INPUT_STATUS 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_LAUNCH_STATUS 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_OUTPUT_STATUS 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_UNEXPECTED_TRAM_DEALLOC 14:14 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_TRAMFILL_OUTSTANDING 15:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_START_XY_OUTSTANDING 16:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_PS_WARP_OUTSTANDING 17:17 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_DQUAD_UNLOAD_OUTSTANDING 18:18 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_TRAM_STATE 23:19 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_INPUT_STATE 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_2D_PIXOUT_CMD_DONE_OUTSTANDING 27:27 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_STATUS_RCVD_3D_AFTER_CONTEXT_SWITCH 29:28 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_STATUS 0x00419c1c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_STATUS_VTG_STATUS 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_STATUS_PIX_STATUS 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_WLU_STATUS_COMP_STATUS 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CYA_BUNDLE_FILTER 0x00419c20 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CYA_BUNDLE_FILTER_START_ADDR 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CYA_BUNDLE_FILTER_START_ADDR_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CYA_BUNDLE_FILTER_END_ADDR 31:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CYA_BUNDLE_FILTER_END_ADDR_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_PREFUNC_WATERMARK 0x00419c24 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_PREFUNC_WATERMARK_ALPHA_VSA 4:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_PREFUNC_WATERMARK_ALPHA_VSA_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_PREFUNC_WATERMARK_ALPHA_VSB 9:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_PREFUNC_WATERMARK_ALPHA_VSB_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_PREFUNC_WATERMARK_BETA_VAF 14:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_PREFUNC_WATERMARK_BETA_VAF_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_PREFUNC_WATERMARK_BETA_TS 19:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_PREFUNC_WATERMARK_BETA_TS_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_MAINFUNC_WATERMARK 0x00419c28 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_MAINFUNC_WATERMARK_VSA 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_MAINFUNC_WATERMARK_VSA_INIT 0x3e /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_MAINFUNC_WATERMARK_VSB 11:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_MAINFUNC_WATERMARK_VSB_INIT 0x3e /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_MAINFUNC_WATERMARK_TI 17:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_MAINFUNC_WATERMARK_TI_INIT 0x3e /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_MAINFUNC_WATERMARK_TS 23:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_MAINFUNC_WATERMARK_TS_INIT 0x3e /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_MAINFUNC_WATERMARK_GS 29:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_MAINFUNC_WATERMARK_GS_INIT 0x3e /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR 0x00419c2c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_V 27:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_V_INIT 0x0000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID_FALSE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR 0x00419c30 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_VTG_ERR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_VTG_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_VTG_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_SKEDCHECK34_OOB_SHARED_MEM_CONFIG 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_SKEDCHECK34_OOB_SHARED_MEM_CONFIG_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_SKEDCHECK34_OOB_SHARED_MEM_CONFIG_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_VTG_ERR_EN 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_VTG_ERR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_VTG_ERR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_EN 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_EN 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_EN 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_SKEDCHECK19_EN 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_SKEDCHECK19_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_SKEDCHECK19_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_SKEDCHECK34_EN 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_SKEDCHECK34_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_SKEDCHECK34_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_RESET 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_RESET_IDLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_RESET_TRIGGER 0x1 /* RW--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_INFO 0x00419c34 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_INFO_VEID 5:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_HWW_ESR_INFO_VEID_INIT 0x00 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_WTC 0x00419c38 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_WTC_ALPHA 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_WTC_ALPHA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_WTC_ALPHA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_WTC_BETA 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_WTC_BETA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_WTC_BETA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_WTC_WATERMARK_ALPHA 12:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_WTC_WATERMARK_ALPHA_INIT 0x1ff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_WTC_WATERMARK_BETA 24:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_WTC_WATERMARK_BETA_INIT 0x1ff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_HOLD_CNT 0x00419c3c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_HOLD_CNT_3D_WARPS 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_HOLD_CNT_3D_WARPS_INIT 0x19 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_HOLD_CNT_3DPFM_SUBTILES 13:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_PIX_HOLD_CNT_3DPFM_SUBTILES_INIT 0x19 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS 0x00419c4c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_INPUT_STATUS 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_LAUNCH_STATUS 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_OUTPUT_STATUS 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_INPUT_STATE 12:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_CTA_IN_PROG 13:13 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_GOT_ALPHA_DRAIN 14:14 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_GOT_BETA_DRAIN 15:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_GOT_PIX_DRAIN 16:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_SHM_CONFIG 20:17 /* R-IVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_SHM_CONFIG_0KB 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_SHM_CONFIG_8KB 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_SHM_CONFIG_16KB 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_SHM_CONFIG_32KB 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_SHM_CONFIG_64KB 0x4 /* R-I-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_SHM_CONFIG_96KB 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_SHM_CONFIG_100KB 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_SHM_CONFIG_132KB 0x8 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_STATUS_SHM_CONFIG_164KB 0x9 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG 0x00419c50 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SCG_ISC_INSTRUCTION 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SCG_ISC_INSTRUCTION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SCG_ISC_INSTRUCTION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SCG_ISC_DATA 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SCG_ISC_DATA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SCG_ISC_DATA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SCG_ISC_CONSTANT 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SCG_ISC_CONSTANT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SCG_ISC_CONSTANT_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SMSCG_RR_ARB 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SMSCG_RR_ARB_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SMSCG_RR_ARB_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_CTA_REQ_WARP_DONE 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_CTA_REQ_WARP_DONE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_CTA_REQ_WARP_DONE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_16 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_32 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_64 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_128 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_256 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_512 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_1K 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_DIS 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SPARE 31:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_COMP_DEBUG_SPARE_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM 0x00419c54 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_ALPHA_MPIPEFE 3:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_STAGE0_PREFUNC 4:4 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_STAGE0_MAINFUNC 5:5 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_STAGE1_PREFUNC 6:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_STAGE1_MAINFUNC 7:7 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_STAGE2_PREFUNC 8:8 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_STAGE2_MAINFUNC 9:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_BETA_MPIPEFE 13:10 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_STAGE3_TGB 14:14 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_STAGE3_PREFUNC 16:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_STAGE3_MAINFUNC 17:17 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_STAGE4_TGB 18:18 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_STAGE4_PREFUNC 20:19 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_STAGE4_MAINFUNC 21:21 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_ISBMGR0 24:22 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_ISBMGR1 27:25 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_SMIO 30:28 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_STATUS_FSM_SMIO_FGS_ILOCK 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_OCCUPANCY 0x00419c40 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_OCCUPANCY_GFX_DENOMINATOR 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_OCCUPANCY_COMPUTE_DENOMINATOR 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL 0x00419c44 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_AVG_WINDOW 5:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_AVG_WINDOW_MIN 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_AVG_WINDOW_MAX 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_AVG_WINDOW_INIT 0x06 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_SAMPLE_DURATION 11:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_SAMPLE_DURATION_MIN 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_SAMPLE_DURATION_MAX 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_SAMPLE_DURATION_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_IDLE_DETECT_HYS 17:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_IDLE_DETECT_HYS_MAX 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_IDLE_DETECT_HYS_MIN 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_IDLE_DETECT_HYS_INIT 0x08 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_VTG_WARP_PRIORITY_CYA 19:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_VTG_WARP_PRIORITY_CYA_DIS 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_PIX_WARP_PRIORITY_CYA 21:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_PIX_WARP_PRIORITY_CYA_DIS 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_COMP_WARP_PRIORITY_CYA 23:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_COMP_WARP_PRIORITY_CYA_DIS 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_CTA_BYPASS_SUBTILE 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_CTA_BYPASS_SUBTILE_EN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_CTA_BYPASS_SUBTILE_DIS 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_STATS_MODE 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_STATS_MODE_AVG 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_STATS_MODE_INST 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_IGNORE_SMSCC_QMD_FIELDS 27:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_IGNORE_SMSCC_QMD_FIELDS_DIS 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_IGNORE_SMSCC_QMD_FIELDS_EN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_STALL_FOR_LAUNCH_INPROG_CYA 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_STALL_FOR_LAUNCH_INPROG_CYA_DIS 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_STALL_FOR_LAUNCH_INPROG_CYA_EN 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_SPARE 31:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SMSCG_CNTRL_SPARE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_PARAM 0x00419c48 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_PARAM_DATA 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_PARAM_DATA_INIT 0x000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_PARAM_INDEX 29:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_PARAM_INDEX_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_PARAM_READ 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_PARAM_READ_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_PARAM_READ_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_PARAM_WRITE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_PARAM_WRITE_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_PARAM_WRITE_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_CLOCK_SEL 0x00419c58 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_CLOCK_SEL_V 2:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_CLOCK_SEL_V_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_CLOCK_DATA_HI 0x00419c5c /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_CLOCK_DATA_HI_V 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_CLOCK_DATA_HI_V_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_CLOCK_DATA_LO 0x00419c60 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_CLOCK_DATA_LO_V 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_SCG_CLOCK_DATA_LO_V_INIT 0x00000000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG 0x00419c70 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG1 0x00419c74 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG1_SLCG 4:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG1_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG1_SLCG_DISABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_MPC_CG1_SLCG__PROD 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU 0x004199ff:0x00419980 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL(i) (0x00419980+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_MODE 0:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_MODE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_MODE_STREAMING 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_AGGREGATE_SCTL 2:2 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_AGGREGATE_SCTL_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_AGGREGATE_SCTL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TRIGGER_ENABLE_T_PULSE 4:4 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TRIGGER_ENABLE_T_PULSE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TRIGGER_ENABLE_T_PULSE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES 8:5 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_1K 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_2K 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_4K 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_8K 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_16K 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_32K 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_64K 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_128K 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_256K 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_512K 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_1024K 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_2048K 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_4096K 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_8192K 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TIMEBASE_CYCLES_16384K 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TRIGGER_ENABLE_PMA_TRIGGER 9:9 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TRIGGER_ENABLE_PMA_TRIGGER_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TRIGGER_ENABLE_PMA_TRIGGER_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES 14:12 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_1K 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_4K 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_16K 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_64K 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_256K 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_1024K 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_4096K 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_QUIESCENT_KEEP_RECORD 15:15 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_QUIESCENT_KEEP_RECORD_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_QUIESCENT_KEEP_RECORD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_COREMIO 16:16 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_COREMIO_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_COREMIO_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_SCTL0 17:17 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_SCTL0_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_SCTL0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_SCTL1 18:18 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_SCTL1_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_SCTL1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_SCTL2 19:19 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_SCTL2_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_SCTL2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_SCTL3 20:20 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_SCTL3_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_INPUT_SCTL3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TRIG_SKIP_COUNT 31:22 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROL_TRIG_SKIP_COUNT_ZERO 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CTXSW(i) (0x00419984+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CTXSW__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CTXSW_MODE 0:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CTXSW_MODE_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CTXSW_MODE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CTXSW_TIMER 1:1 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CTXSW_TIMER_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CTXSW_TIMER_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PERFMONID(i) (0x00419988+(i)*64) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PERFMONID__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PERFMONID_PERFMONID 10:0 /* RWXUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PERFMONID_PERFMONID_INIT 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CYCLECNT_LSB(i) (0x0041998c+(i)*64) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CYCLECNT_LSB__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CYCLECNT_LSB_COUNT 31:0 /* RWXUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CYCLECNT_MSB(i) (0x00419990+(i)*64) /* RW-4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CYCLECNT_MSB__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CYCLECNT_MSB_COUNT 7:0 /* RWXUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_TOTAL_TRIG_RCV(i) (0x00419994+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_TOTAL_TRIG_RCV__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_TRIG_STATE(i) (0x004199b8+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_TRIG_STATE__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_TRIG_STATE_INCR_COUNT 9:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_TRIG_STATE_INCR_COUNT_ZERO 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_STATE(i) (0x00419998+(i)*64) /* R--4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_STATE__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_STATE_SAMPLECNT 8:0 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_STATE_DELAY 9:9 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_STATE_PER_SMPC_OVERFLOW 14:10 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_STATE_PER_SMPC_QUIESCENT_TIMEOUT 19:15 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_STATE_PER_SMPC_SPURIOUS_SM_DATA 24:20 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_ENGINESTATUS(i) (0x0041999c+(i)*64) /* R--4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_ENGINESTATUS__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_ENGINESTATUS_STATUS_EMPTY 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_ENGINESTATUS_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_ENGINESTATUS_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_ENGINESTATUS_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_ENGINESTATUS_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_ENGINESTATUS_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_ENGINESTATUS_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CG2_SLCG(i) (0x004199a0+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CG2_SLCG__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CG2_SLCG_ENABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CG2_SLCG_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CG2_SLCG_ENABLE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CG2_SLCG_ENABLE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROLB(i) (0x004199a4+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROLB__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROLB_FLUSH_RECORD 0:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROLB_FLUSH_RECORD_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROLB_FLUSH_RECORD_DOIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROLB_SOFT_RESET 1:1 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROLB_SOFT_RESET_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_CONTROLB_SOFT_RESET_DOIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN(i) (0x004199a8+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_ENABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_SINGLE_DP 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_SINGLE_DP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_TRIGGER_MODE 3:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_TRIGGER_MODE_IGNORE_PMA_TRIGGER 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_TRIGGER_MODE_ONLY_PMA_TRIGGER 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_TRIGGER_MODE_ONLY_TPULSE_TRIGGER 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_TRIGGER_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_MODE 6:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_MODE_ZEROS 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_MODE_COUNT_UP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_MODE_COUNT_DOWN 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_MODE_RANDOM 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_MODE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_OVERFLOW_ENABLE 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_OVERFLOW_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_MODE_SEED 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_MODE_SEED_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_NUM_TRIGGERS 22:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_NUM_TRIGGERS_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_DWORDS 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_DWORDS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_TRIGGER_DELAY 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DATA_GEN_TRIGGER_DELAY_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM(i) (0x004199ac+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM__SIZE_1 1 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE0_STATUS 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE0_SM_GRP0 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE0_SM_GRP1 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE0_SM_GRP2 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE0_SM_GRP3 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE0_SM_GRP4 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE0_SM_GRP5 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE0_SM_GRP6 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE0_SM_GRP7 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE0_SM_GRP8 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE0_SM_GRP9 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE0_PMM_GRP0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE1_STATUS 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE1_SM_GRP0 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE1_SM_GRP1 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE1_SM_GRP2 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE1_SM_GRP3 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE1_SM_GRP4 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE1_SM_GRP5 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE1_SM_GRP6 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE1_SM_GRP7 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE1_SM_GRP8 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE1_SM_GRP9 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_SLICE1_PMM_GRP0 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_CTL_EN 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_CTL_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_CTL_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_PM_SELECT_CTL_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG(i) (0x004199b0+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG_TOTAL_RECORDS_SENT 31:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG_TOTAL_RECORDS_SENT_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG2(i) (0x004199b4+(i)*64) /* RWE4A */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG2__SIZE_1 2 /* */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG2_TOTAL_DROPPED_TRIGGERS 3:0 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG2_TOTAL_DROPPED_TRIGGERS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG2_TOTAL_T_PULSE_TRIGGERS 7:4 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG2_TOTAL_T_PULSE_TRIGGERS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG2_TOTAL_OVERFLOW 11:8 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG2_TOTAL_OVERFLOW_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG2_TOTAL_CTXSW_FREEZE 15:12 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG2_TOTAL_CTXSW_FREEZE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG2_CYA_REGS 31:16 /* RWEUF */ #define NV_PGRAPH_PRI_GPCS_TPCS_CAU_DEBUG2_CYA_REGS_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPC0 0x0041b000 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_PPC1 0x0041b200 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_PPC2 0x0041b400 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_PPCS 0x0041be00 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES 0x0041be7f:0x0041be00 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x0041be50 /* RWB4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLKCG_CG 0x0041be00 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLKCG_CG__PRIV_LEVEL_MASK 0x0041be50 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLKCG_CG_BLKACTIVITY_ENABLE 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLKCG_CG_BLKACTIVITY_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLKCG_CG_BLKACTIVITY_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLKCG_CG_BLKACTIVITY_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLKCG_CG_BLKACTIVITY_ERR 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLKCG_CG_BLKACTIVITY_ERR_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLKCG_CG_BLKACTIVITY_ERR_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLKCG_CG_BLKACTIVITY_ERR_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP 0x0041be04 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_STIPPLE_DISABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_STIPPLE_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_STIPPLE_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_STIPPLE_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_FETCH_REPACK 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_FETCH_REPACK_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_FETCH_REPACK_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_FETCH_REPACK_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_DISABLE_LFO 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_DISABLE_LFO_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_DISABLE_LFO_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_DISABLE_LFO_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_DISABLE_NODEN 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_DISABLE_NODEN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_DISABLE_NODEN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_DISABLE_NODEN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_DISABLE_NAN_DEL 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_DISABLE_NAN_DEL_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_DISABLE_NAN_DEL_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_DISABLE_NAN_DEL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_SPARE5 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_SPARE5_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_SPARE5_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_SPARE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_SPARE6 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_SPARE6_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_SPARE6_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_SPARE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_SPARE7 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_SPARE7_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_SPARE7_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CLIP_SPARE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x0041be08 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CULL_DISABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CULL_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CULL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_CULL_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_MPC_CULL_DISABLE 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_MPC_CULL_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_MPC_CULL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_MPC_CULL_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_TIER_1_STYLE_LINES_AND_POINTS 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_TIER_1_STYLE_LINES_AND_POINTS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_TIER_1_STYLE_LINES_AND_POINTS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_TIER_1_STYLE_LINES_AND_POINTS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_MAX_VIEWPORT_BBOX_FOR_CLAMPED_PRIMS 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_MAX_VIEWPORT_BBOX_FOR_CLAMPED_PRIMS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_MAX_VIEWPORT_BBOX_FOR_CLAMPED_PRIMS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_MAX_VIEWPORT_BBOX_FOR_CLAMPED_PRIMS_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_WID_RECTS_CULL 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_WID_RECTS_CULL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_WID_RECTS_CULL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_WID_RECTS_CULL_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_L1 0x0041be0c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_L1_DM_CACHE_DISABLE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_L1_DM_CACHE_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_L1_DM_CACHE_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_L1_DM_CACHE_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_L1_SWITCH_SM_LIMIT 4:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_L1_SWITCH_SM_LIMIT_INIT 0x4 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG 0x0041be10 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_CULL_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_CULL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_CULL_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_CULL_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_DIAMOND_CULL_EN 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_DIAMOND_CULL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_DIAMOND_CULL_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_DIAMOND_CULL_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SMALL_LINE_CULL_EN 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SMALL_LINE_CULL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SMALL_LINE_CULL_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SMALL_LINE_CULL_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FLIP_BBOX_CULL 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FLIP_BBOX_CULL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FLIP_BBOX_CULL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FLIP_BBOX_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FLIP_DIAMOND_CULL 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FLIP_DIAMOND_CULL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FLIP_DIAMOND_CULL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FLIP_DIAMOND_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FLIP_SMALL_LINE_CULL 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FLIP_SMALL_LINE_CULL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FLIP_SMALL_LINE_CULL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FLIP_SMALL_LINE_CULL_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_CULL_VC_MODES 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_CULL_VC_MODES_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_CULL_VC_MODES_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_CULL_VC_MODES_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_CLIP_SINGLE_TRI 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_CLIP_SINGLE_TRI_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_CLIP_SINGLE_TRI_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_CLIP_SINGLE_TRI_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SURFACE_CULL_EN 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SURFACE_CULL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SURFACE_CULL_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SURFACE_CULL_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SCISSOR_CULL_EN 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SCISSOR_CULL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SCISSOR_CULL_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SCISSOR_CULL_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_SHRINK_DISABLE 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_SHRINK_DISABLE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_SHRINK_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_SHRINK_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BACKFACE_CULL_EN 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BACKFACE_CULL_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BACKFACE_CULL_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BACKFACE_CULL_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BROADCAST_STIPPLE_EN 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BROADCAST_STIPPLE_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BROADCAST_STIPPLE_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BROADCAST_STIPPLE_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SET_COUNTERS 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SET_COUNTERS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SET_COUNTERS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SET_COUNTERS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SEND_CULLED_POLYGONS 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SEND_CULLED_POLYGONS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SEND_CULLED_POLYGONS_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SEND_CULLED_POLYGONS_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_BLOAT_AA_POINT 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_BLOAT_AA_POINT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_BLOAT_AA_POINT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_BLOAT_AA_POINT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SCOUNT_EMAX_EN 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SCOUNT_EMAX_EN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SCOUNT_EMAX_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SCOUNT_EMAX_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SCISSOR_CULL_BLOAT 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SCISSOR_CULL_BLOAT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SCISSOR_CULL_BLOAT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_SCISSOR_CULL_BLOAT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_24_BIT_STIPPLE_PHASE 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_24_BIT_STIPPLE_PHASE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_24_BIT_STIPPLE_PHASE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_24_BIT_STIPPLE_PHASE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_DIAMOND_EXIT 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_DIAMOND_EXIT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_DIAMOND_EXIT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_DIAMOND_EXIT_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_SMOOTH_LINES 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_SMOOTH_LINES_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_SMOOTH_LINES_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_SMOOTH_LINES_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_ROTATED_GRID 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_ROTATED_GRID_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_ROTATED_GRID_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_ROTATED_GRID_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_SM_LINE_DIAMOND 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_SM_LINE_DIAMOND_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_SM_LINE_DIAMOND_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_BBOX_SM_LINE_DIAMOND_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_CBE_WRITE_SLOWDOWN 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_CBE_WRITE_SLOWDOWN_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_CBE_WRITE_SLOWDOWN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_CBE_WRITE_SLOWDOWN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_DISABLE_NIC_CG_FIX 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_DISABLE_NIC_CG_FIX_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_DISABLE_NIC_CG_FIX_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_DISABLE_NIC_CG_FIX_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_CLIP_BBOX_TO_SCISSOR 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_CLIP_BBOX_TO_SCISSOR_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_CLIP_BBOX_TO_SCISSOR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_CLIP_BBOX_TO_SCISSOR_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_TIGHTEN_SCISSOR_BBOX 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_TIGHTEN_SCISSOR_BBOX_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_TIGHTEN_SCISSOR_BBOX_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_TIGHTEN_SCISSOR_BBOX_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FIX_BMAP_COUNTER 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FIX_BMAP_COUNTER_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FIX_BMAP_COUNTER_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FIX_BMAP_COUNTER_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_PE2MPCDONE_ORDER_DISABLE 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_PE2MPCDONE_ORDER_DISABLE_DISABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_PE2MPCDONE_ORDER_DISABLE_ENABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_PE2MPCDONE_ORDER_DISABLE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FGS_PROV_LOOKAHEAD 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FGS_PROV_LOOKAHEAD_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FGS_PROV_LOOKAHEAD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FGS_PROV_LOOKAHEAD_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FGS_2BATCH_CBE_OPT 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FGS_2BATCH_CBE_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FGS_2BATCH_CBE_OPT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FGS_2BATCH_CBE_OPT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FGS_2BATCH_VCACHE_OPT 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FGS_2BATCH_VCACHE_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FGS_2BATCH_VCACHE_OPT_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_DEBUG_FGS_2BATCH_VCACHE_OPT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM 0x0041be14 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_TG 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_VSC 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_PEM 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_CG_STATUS_TG 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_CG_STATUS_VSC 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_CG_STATUS 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_BLK_ACTIVITY 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_WAKEUP 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_CPO_GRP_0 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_CPO_GRP_1 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_SSYNC_GRP_0 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STREAM_GRP_0 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STREAM_GRP_1 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STREAM_GRP_2 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STREAM_GRP_3 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_0 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_1 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_2 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_3 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_4 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_5 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_6 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_7 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_8 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_9 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_10 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_11 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_12 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_13 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_14 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_15 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_16 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_17 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_TG_GRP_18 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_0 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_1 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_2 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_3 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_4 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_5 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_6 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_7 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_8 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PVLDRDY1 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PVLDRDY2 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PVLDRDY3 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PVLDRDY4 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VALID1 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VALID2 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VALID3 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PVLDRDY5 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PVLDRDY6 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_9 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_10 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_11 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PG_STATUS 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_1 0x40 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_2 0x41 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_3 0x42 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_4 0x43 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_5 0x44 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_6 0x45 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_7 0x46 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_8 0x47 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_9 0x48 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_10 0x49 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_11 0x4a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_12 0x4b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_13 0x4c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_14 0x4d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_15 0x4e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_16 0x4f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_17 0x50 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_18 0x51 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_19 0x52 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_20 0x53 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_21 0x54 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_22 0x55 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_23 0x56 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_24 0x57 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_25 0x58 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_26 0x59 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_27 0x5a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_28 0x5b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_29 0x5c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_30 0x5d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_31 0x5e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_32 0x5f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_33 0x60 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_34 0x61 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_35 0x62 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_36 0x63 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_37 0x64 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_38 0x65 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_39 0x66 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_40 0x67 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_41 0x68 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_42 0x69 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_43 0x6a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_44 0x6b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_45 0x6c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_46 0x6d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_PEM_GRP_47 0x6e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_12 0x70 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_13 0x71 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_14 0x72 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_15 0x73 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_16 0x74 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_17 0x75 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_18 0x76 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_19 0x77 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_20 0x78 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_VPC_GRP_21 0x79 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_GRP_19 0x80 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_GRP_20 0x81 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_GRP_21 0x82 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_GRP_22 0x83 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_GRP_23 0x84 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_GRP_24 0x85 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_GRP_25 0x86 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_GRP_26 0x87 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_GRP_27 0x88 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATUS_GRP_28 0x89 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_BA_GRP_1 0x90 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_BA_GRP_2 0x91 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_BA_GRP_3 0x92 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_SINGLE_PASS_GRP1 0x93 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATIC_PATTERN_2A_6_GROUP 0xa0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_STATIC_PATTERN_15_6_GROUP 0xa1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_CTL_EN 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_CTL_EN_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_CTL_EN_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_PM_SELECT_CTL_EN_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STREAM 0x0041be18 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STREAM_MASTER_PE 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STREAM_MASTER_PE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STREAM_MASTER_PE_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STREAM_MASTER_PE_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS 0x0041be1c /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS_PES 2:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS_PES_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS_TGA 5:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS_TGA_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS_VSC 8:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS_VSC_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS_TGB 11:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS_TGB_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS_PEM 14:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS_PEM_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS_CACHE 17:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_STATUS_CACHE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS 0x0041be20 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_IFACE 2:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_IFACE_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_SYNC 5:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_SYNC_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_SCOUNT 8:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_SCOUNT_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_PFETCH 11:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_PFETCH_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_CLIP 14:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_CLIP_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_CULL 17:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_CULL_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_CBMGR 20:18 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_CBMGR_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_WWDX 23:21 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_WWDX_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_DOUT 26:24 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_DOUT_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_NIC 29:27 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_STATUS_NIC_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG 0x0041be24 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_USE_SW_COMPUTED_GS_CONSTRAINT_V 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_USE_SW_COMPUTED_GS_CONSTRAINT_V_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_CONSTRAINT_BALANCE_LOAD 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_CONSTRAINT_BALANCE_LOAD_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_CONSTRAINT_BALANCE_LOAD_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_CONSTRAINT_BALANCE_LOAD_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_SCAN_INTERIOR_HORIZONTALLY 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_SCAN_INTERIOR_HORIZONTALLY_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_VERTEX_REORDERING 3:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_VERTEX_REORDERING_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_VERTEX_REORDERING_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_VERTEX_REORDERING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_WINDING_SWAP 4:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_WINDING_SWAP_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_WINDING_SWAP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_TG_WINDING_SWAP_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_MODES 0x0041be54 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_MODES_FORCE_SWIZZLE_NEG_W_TO_ONE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_MODES_FORCE_SWIZZLE_NEG_W_TO_ONE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_MODES_FORCE_SWIZZLE_NEG_W_TO_ONE_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_MODES_FORCE_SWIZZLE_NEG_W_TO_ONE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_MODES_PROVOKING_FIRST_DX_MODE 2:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_MODES_PROVOKING_FIRST_DX_MODE_NO_ROTATE_DEFAULT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_MODES_PROVOKING_FIRST_DX_MODE_ROTATE_DEPENDS_ON_BARYCENTRICS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_MODES_PROVOKING_FIRST_DX_MODE_ROTATE_LEGACY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_MODES_PROVOKING_FIRST_DX_MODE_ROTATE_RESERVED 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_MODES_PROVOKING_FIRST_DX_MODE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG 0x0041be28 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG1 0x0041be2c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_CG1_SLCG__PROD 0x0208afe0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR 0x0041be38 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P01_ERR 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P02_ERR 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P12_ERR 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_BD_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P01_ERR 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P02_ERR 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P12_ERR 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_TK_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P01_ERR 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P02_ERR 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P12_ERR 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_ALPHA_WK_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_BD_P01_ERR 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_BD_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_BD_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_BD_P02_ERR 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_BD_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_BD_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_BD_P12_ERR 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_BD_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_BD_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_TK_P01_ERR 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_TK_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_TK_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_TK_P02_ERR 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_TK_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_TK_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_TK_P12_ERR 14:14 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_TK_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_TK_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_WK_P01_ERR 15:15 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_WK_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_WK_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_WK_P02_ERR 16:16 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_WK_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_WK_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_WK_P12_ERR 17:17 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_WK_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_VSC_BETA_WK_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_BD_P01_ERR 18:18 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_BD_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_BD_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_BD_P02_ERR 19:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_BD_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_BD_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_BD_P12_ERR 20:20 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_BD_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_BD_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_TK_P01_ERR 21:21 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_TK_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_TK_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_TK_P02_ERR 22:22 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_TK_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_TK_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_TK_P12_ERR 23:23 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_TK_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_TK_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_WK_P01_ERR 24:24 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_WK_P01_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_WK_P01_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_WK_P02_ERR 25:25 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_WK_P02_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_WK_P02_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_WK_P12_ERR 26:26 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_WK_P12_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_PEM_TGB_FILL_WK_P12_ERR_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_RESET_TASK 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_RESET_INIT 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_EN_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_HWW_ESR_EN_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_A 0x0041be3c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_A__PRIV_LEVEL_MASK 0x0041be50 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_A_1 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_A_1_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_A_2 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_A_2_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_A_3 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_A_3_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_B 0x0041be40 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_B__PRIV_LEVEL_MASK 0x0041be50 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_B_4 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_B_4_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_B_5 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_B_5_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_B_6 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_B_6_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_C 0x0041be44 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_C__PRIV_LEVEL_MASK 0x0041be50 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_C_7 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_C_7_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_C_8 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_C_8_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_C_9 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_C_9_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_D 0x0041be48 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_D__PRIV_LEVEL_MASK 0x0041be50 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_D_10 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_D_10_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_D_11 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_D_11_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_D_12 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_D_12_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_E 0x0041be4c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_E__PRIV_LEVEL_MASK 0x0041be50 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_E_13 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_E_13_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_E_14 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_E_14_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_E_15 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_PES_BLK_ACTIVITY_WEIGHTS_E_15_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX 0x0041bfff:0x0041bf00 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP(i) (0x0041bf00+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP__SIZE_1 43 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP_TILE0 4:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP_TILE0_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP_TILE1 9:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP_TILE1_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP_TILE2 14:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP_TILE2_INIT 0x02 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP_TILE3 19:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP_TILE3_INIT 0x03 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP_TILE4 24:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP_TILE4_INIT 0x04 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP_TILE5 29:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP_TILE5_INIT 0x05 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x0041bfd0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET_INIT 0x03 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES_INIT 0x01 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES_INIT 0x10 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE_INIT 0x4 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x0041bfd4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE_MAX 0x800000 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE_INIT 0x800000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM 0x0041bfdc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_DEBUG_SIGNAL_GPC_INSTANCE_ID_GROUP 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_DEBUG_SIGNAL_TPC_INSTANCE_ID_GROUP 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_STATIC_PATTERN_2AAA_15_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_STATIC_PATTERN_5555_15_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_SELECT_MAX 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG 0x0041bfe0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_CACHETILE_COVERAGE_BBOX 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_CACHETILE_COVERAGE_BBOX_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_CACHETILE_COVERAGE_BBOX_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_RESERVED 21:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_RESERVED_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_FORCE_CBE_ADDR_TO_ALL_GPCS 22:22 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_FORCE_CBE_ADDR_TO_ALL_GPCS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_FORCE_CBE_ADDR_TO_ALL_GPCS_FALSE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_FORCE_CBE_ADDR_TO_ALL_GPCS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_FORCE_PRIMS_TO_ALL_GPCS 23:23 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_FORCE_PRIMS_TO_ALL_GPCS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_FORCE_PRIMS_TO_ALL_GPCS_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_PRIORITIZE_ALPHA_CBES 24:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_PRIORITIZE_ALPHA_CBES_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_PRIORITIZE_ALPHA_CBES_TRUE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_TASK_FIFO_REDUCE_DIV32 28:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_TASK_FIFO_REDUCE_DIV32_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_TASK_FIFO_REDUCE_DIV32_FULLSIZE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_PRIM_FIFO_REDUCE_DIV32 30:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_PRIM_FIFO_REDUCE_DIV32_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_PRIM_FIFO_REDUCE_DIV32_FULLSIZE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_TILED_CACHING 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_TILED_CACHING_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_TILED_CACHING_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CONFIG_TILED_CACHING_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF(i) (0x0041bfb0+(i)*4) /* RWI4A */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF__SIZE_1 5 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF_0_MOD_VALUE 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF_0_MOD_VALUE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF_1_MOD_VALUE 15:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF_1_MOD_VALUE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF_2_MOD_VALUE 23:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF_2_MOD_VALUE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF_3_MOD_VALUE 31:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF_3_MOD_VALUE_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG 0x0041bfe8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG1 0x0041bfec /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_CG1_SLCG__PROD 0x7ffffff8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM 0x0041beff:0x0041bec0 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_SIZE 0x0041bec0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_SIZE_V 21:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_SIZE_V_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_SIZE_V_DEFAULT 0x000480 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_SIZE_V_GFXP 0x000d28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_SIZE_V_GRANULARITY 0x000020 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_ALPHA_CB_SIZE 0x0041bee4 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_ALPHA_CB_SIZE_V 15:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_ALPHA_CB_SIZE_V_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_ALPHA_CB_SIZE_V_DEFAULT 0x0800 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_ALPHA_CB_SIZE_V_GRANULARITY 0x0020 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_OFFSET 0x0041bef4 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_OFFSET_V 21:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_OFFSET_V_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_ALPHA_CB_OFFSET 0x0041bef8 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_ALPHA_CB_OFFSET_V 21:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_ALPHA_CB_OFFSET_V_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_STEADY_STATE_CB_SIZE 0x0041bef0 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_STEADY_STATE_CB_SIZE_V 21:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_STEADY_STATE_CB_SIZE_V_INIT 0x000000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_STEADY_STATE_CB_SIZE_V_DEFAULT 0x000480 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_STEADY_STATE_CB_SIZE_V_GRANULARITY 0x000020 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_CTRL 0x0041befc /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_CTRL_CBES_RESERVE 11:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_CTRL_CBES_RESERVE_NON_GFXP 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_BETA_CB_CTRL_CBES_RESERVE_GFXP 0x100 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG 0x0041bec4 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_INVALIDATE_ALPHA 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_INVALIDATE_ALPHA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_INVALIDATE_ALPHA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_INVALIDATE_BETA 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_INVALIDATE_BETA_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_INVALIDATE_BETA_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_DELETE_ARB 26:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_DELETE_ARB_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_DELETE_ARB_ROUND_ROBIN 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_DELETE_ARB_PRIM_PRIORITY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_DELETE_ARB_TASK_PRIORITY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_RESERVED 31:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_DEBUG_RESERVED_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_INDEX 0x0041bec8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_INDEX_INDEX 2:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_INDEX_INDEX_MIN 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_INDEX_INDEX_MAX 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_INDEX_READINCR 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_INDEX_READINCR_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_INDEX_READINCR_ENABLED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE 0x0041bedc /* R--4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE__APERTURE_INDEX 0x0041bec8 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_VAL 31:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_0_ALPHA_FSM 21:18 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_0_BETA_FSM 25:22 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_0_WWDX2CBMGR 28:26 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_0_AB_MERGE 31:29 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_1_ALPHA_COUNT 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_1_BETA_COUNT 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_ALPHA_ALLOC 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_ALPHA_ALLOC_ALLOC 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_ALPHA_ALLOC_INVFIFO 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_BETA_ALLOC 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_BETA_ALLOC_ALLOC 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_BETA_ALLOC_INVFIFO 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_PE2CBMGR_VSC 20:18 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_CBMGR2PE_VSC 23:21 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_CBMGR2PE_PIN 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_PE2CBMGR_INVACK 29:27 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_ALPHA_SIZE_GT_MAX_HANG 30:30 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_ALPHA_SIZE_GT_MAX_HANG_NOT_HUNG 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_ALPHA_SIZE_GT_MAX_HANG_HUNG 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_BETA_SIZE_GT_MAX_HANG 31:31 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_BETA_SIZE_GT_MAX_HANG_NOT_HUNG 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_2_BETA_SIZE_GT_MAX_HANG_HUNG 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_3_MPC2CBMGR0 2:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_3_CBMGR2MPC0 5:3 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_3_MPC2CBMGR1 8:6 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_3_CBMGR2MPC1 11:9 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_3_MPC2CBMGR2 14:12 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_3_CBMGR2MPC2 17:15 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_3_MPC2CBMGR3 20:18 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_3_CBMGR2MPC3 23:21 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_3_MPC2CBMGR4 26:24 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_3_CBMGR2MPC4 29:27 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_4_ALPHA_ALLOC_SPACE 15:0 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_STATUS_APERTURE_4_BETA_ALLOC_SPACE 31:16 /* R--VF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM 0x0041becc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_DEBUG_SIGNAL_GPC_INSTANCE_ID_GROUP 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_DEBUG_SIGNAL_TPC_INSTANCE_ID_GROUP 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_STATIC_PATTERN_2AAA_14_GROUP 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_STATIC_PATTERN_1555_14_GROUP 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_SELECT_MAX 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_ENABLE_OFF 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_PM_ENABLE_ON 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG 0x0041bed0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_STALL_CG_DLY_CNT__PROD 0x04 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG1 0x0041bed4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG1_SLCG_DISABLED 0x7fffffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CG1_SLCG__PROD 0x7ffffffc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0 0x0041b800 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP 0x0041b85f:0x0041b800 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1 0x0041b800 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZRD_NO_COND_READ 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZRD_NO_COND_READ_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZRD_NO_COND_READ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZRD_NO_COND_READ_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_CLEAR 11:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_CLEAR_ALL_BUNDLES_ALL_GLOBAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_CLEAR_FLUSHBUNDLES_ALL_GLOBAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_CLEAR_LITE_FLUSHBUNDLES_PERGPC 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_CLEAR_NO_BUNDLES 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_CLEAR_INIT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_Z 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_Z_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_Z_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_Z_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_FORCE_L2_WAKE 31:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_FORCE_L2_WAKE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_FORCE_L2_WAKE_ON_NONIDLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_FORCE_L2_WAKE_ALWAYS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG1_FORCE_L2_WAKE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2 0x0041b804 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_FORCE_VISIBLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_FORCE_VISIBLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_FORCE_VISIBLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_FORCE_VISIBLE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_RTL_KNOBS 27:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_RTL_KNOBS_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_WRITE_FULL_BE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_WRITE_FULL_BE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_WRITE_FULL_BE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_WRITE_FULL_BE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_DISABLE_FULL_WE_OPT 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG2_ZWR_DISABLE_FULL_WE_OPT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3 0x0041b808 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_INNER_IL_COVG_AWARE 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_INNER_IL_COVG_AWARE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_INNER_IL_COVG_AWARE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_INNER_IL_COVG_AWARE_ONLY_1_STAGE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_INNER_IL_COVG_AWARE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8 7:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8_NOREDUCE 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8_FULLSIZE 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_HASHENTRIES_REDUCE_DIV8 12:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_HASHENTRIES_REDUCE_DIV8_FULLSIZE 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_HASHENTRIES_REDUCE_DIV8_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_RTL_KNOBS 27:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_RTL_KNOBS_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_COALESCE_WRITES 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_COALESCE_WRITES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_COALESCE_WRITES_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG3_COALESCE_WRITES_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4 0x0041b80c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_PM_LOCAL_TRIGGER_GPC 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_PM_LOCAL_TRIGGER_GPC_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_S8_COALESCER_LIMIT 11:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_S8_COALESCER_LIMIT_MAX 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_S8_COALESCER_LIMIT_ZERO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_S8_COALESCER_LIMIT_INIT 0x7 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_S8_COALESCER_TIMEOUT 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_S8_COALESCER_TIMEOUT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_S8_COALESCER_TIMEOUT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_BURSTY_MIN_GEAR 18:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_BURSTY_MIN_GEAR_DISABLE_BURSTING 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_BURSTY_MIN_GEAR_FULL_RANGE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_BURSTY_MIN_GEAR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_RTL_KNOBS 26:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_RTL_KNOBS_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW 28:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW_NONE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW_S8_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW_ALL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_SPARE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG4_SPARE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5 0x0041b810 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5_SRCPKTFIFO_REDUCE_DIV256 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5_SRCPKTFIFO_REDUCE_DIV256_FULLSIZE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5_HASHENTRIES_REDUCE_DIV256 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5_HASHENTRIES_REDUCE_DIV256_FULLSIZE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT0 17:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT0_ORIGINAL_GALOIS 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT0_AVOID_ROPSLICE_MAP_A 0x255 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT0_AVOID_ROPSLICE_MAP_B 0x015 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT1 27:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT1_ORIGINAL_GALOIS 0x2f6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT1_AVOID_ROPSLICE_MAP_A 0x2c4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG5_TAGBANK_TAPS_BIT1_AVOID_ROPSLICE_MAP_B 0x0c4 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM 0x0041b814 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_STATIC_PATTERN_25_6_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_STATIC_PATTERN_1A_6_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2 13:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_STATIC_PATTERN_25_6_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_STATIC_PATTERN_1A_6_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_GROUP_SEL2_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP10 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP11 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP12 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP13 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP14 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_STATIC_PATTERN_25_6_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_GRP15 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_STATIC_PATTERN_1A_6_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2 25:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP10 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP11 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP12 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP13 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP14 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_STATIC_PATTERN_25_6_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_GRP15 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_STATIC_PATTERN_1A_6_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_COUNT_SEL2_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PPM_ENABLE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG 0x0041b818 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG1 0x0041b81c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS 0x0041b820 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_DECODER_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_DECODER_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_DECODER_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_DECODER_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_DECODER_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_DECODER_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_DECODER_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_DECODER_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZRDPIPE_STATUS 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZRDPIPE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_LTCTRACK_STATUS 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_LTCTRACK_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_LTCTRACK_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_LTCTRACK_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_LTCTRACK_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_LTCTRACK_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_LTCTRACK_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_LTCTRACK_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZSUB_STATUS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZSUB_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZSUB_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZSUB_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZSUB_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZSUB_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZSUB_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZSUB_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_BPC_STATUS 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_BPC_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_BPC_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_BPC_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_BPC_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_BPC_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_BPC_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_BPC_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PACKETIZER_STATUS 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PACKETIZER_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PACKETIZER_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PACKETIZER_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PACKETIZER_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PACKETIZER_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PACKETIZER_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PACKETIZER_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PIPE_STATUS 20:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PIPE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PIPE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PIPE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PIPE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PIPE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PIPE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_PIPE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZWR_STATUS 23:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZWR_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZWR_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZWR_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZWR_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZWR_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZWR_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZWR_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_RETIRE_STATUS 26:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_RETIRE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_RETIRE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_RETIRE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_RETIRE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_RETIRE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_RETIRE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_RETIRE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZCULL_STATUS 29:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZCULL_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZCULL_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZCULL_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZCULL_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZCULL_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZCULL_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_ZCULL_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_WACKFIFO_STATE 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_WACKFIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS_WACKFIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2 0x0041b824 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2_TOP 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2_TOP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2_TOP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2_TOP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2_TOP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2_TOP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2_TOP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2_TOP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2_TAGS_IN_USE_COUNT 11:3 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2_ILQUEUE_ENTRY_COUNT 18:12 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2_ZSUB_ENTRY_COUNT 27:19 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_STATUS2_VALID_CACHETILES_COUNT 31:28 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG_COUNT_REQUESTS 0x0041b828 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG_COUNT_REQUESTS_ZRD2RRH_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG_COUNT_REQUESTS_ZRD2RRH_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG_COUNT_REQUESTS_ZWR2RRH_PACKETS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG_COUNT_REQUESTS_ZWR2RRH_PACKETS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG_COUNT_RESPONSES 0x0041b82c /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZRD_RDAT_PACKETS_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZRD_RDAT_PACKETS_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZWR_ACKS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZWR_ACKS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR 0x0041b838 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_DEAD_TAGS 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_DEAD_TAGS_NOT_PRESENT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_DEAD_TAGS_PRESENT 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_DEAD_TAGS_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_RDAT_ORPHANS 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_RDAT_ORPHANS_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_RDAT_ORPHANS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_RDAT_ORPHANS_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_EOZP_MISMATCH 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_EOZP_MISMATCH_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_EOZP_MISMATCH_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_EOZP_MISMATCH_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_ZWRRAM_ORPHANS 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_ZWRRAM_ORPHANS_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_ZWRRAM_ORPHANS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_ZWRRAM_ORPHANS_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_BLKACTIVITY_ERROR 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_BLKACTIVITY_ERROR_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_BLKACTIVITY_ERROR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_BLKACTIVITY_ERROR_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_HWW_ESR_EN_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF 0x0041b854 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_FULLSPEED 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_03125 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_06250 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_09375 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_12500 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_15625 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_18750 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_21875 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_25000 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_28125 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_31250 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_34375 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_37500 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_40625 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_43750 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_46875 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_50000 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_53125 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_56250 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_59375 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_62500 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_65625 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_68750 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_71875 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_75000 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_78125 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_81250 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_84375 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_87500 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_90625 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_93750 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_PERF_THROTTLE_PIPE_0_96875 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x0041b840 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_A 0x0041b844 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_A__PRIV_LEVEL_MASK 0x0041b840 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_A_INTERCEPT 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_A_INTERCEPT_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_A_WEIGHT_1 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_A_WEIGHT_1_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_A_WEIGHT_2 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_A_WEIGHT_2_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_B 0x0041b848 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_B__PRIV_LEVEL_MASK 0x0041b840 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_B_WEIGHT_3 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_B_WEIGHT_3_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_B_WEIGHT_4 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_B_WEIGHT_4_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_B_WEIGHT_5 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_B_WEIGHT_5_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_C 0x0041b84c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_C__PRIV_LEVEL_MASK 0x0041b840 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_C_WEIGHT_6 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_C_WEIGHT_6_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_C_WEIGHT_7 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_C_WEIGHT_7_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_C_WEIGHT_8 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_C_WEIGHT_8_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_D 0x0041b850 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_D__PRIV_LEVEL_MASK 0x0041b840 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_D_WEIGHT_9 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_D_WEIGHT_9_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_D_WEIGHT_10 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_D_WEIGHT_10_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_D_WEIGHT_11 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_ZROP_BLK_ACTIVITY_D_WEIGHT_11_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH 0x0041b87f:0x0041b860 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0 0x0041b860 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RRA_FAVOR_IL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RRA_FAVOR_IL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RRA_FAVOR_IL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RRA_FAVOR_Z 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RRA_FAVOR_Z_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RRA_FAVOR_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RRA_IL_DELAY 5:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RRA_IL_DELAY_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RC_FAVOR_IL 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RC_FAVOR_IL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RC_FAVOR_IL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RC_FAVOR_Z 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RC_FAVOR_Z_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RC_FAVOR_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_WRA_FAVOR_Z 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_WRA_FAVOR_Z_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_WRA_FAVOR_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RW_ARB_BURST_SIZE 12:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RW_ARB_BURST_SIZE_ONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_RW_ARB_BURST_SIZE_INIT 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA_4TO1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA_8TO1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_CONCAT_WRITE_COMP 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_CONCAT_WRITE_COMP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_CONCAT_WRITE_COMP_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_CONCAT_WRITE_UNCOMP 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_CONCAT_WRITE_UNCOMP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_CONCAT_WRITE_UNCOMP_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_CONCAT_WRITE_FCLR 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_CONCAT_WRITE_FCLR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_CONCAT_WRITE_FCLR_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_C 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_C_WARM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_C_NONE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_Z 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_Z_WARM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_Z_NONE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_FE_MSG_FIFO_REDUCE 25:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_FE_MSG_FIFO_REDUCE_FULLSIZE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_WRITE_REQ_SB_REDUCE_DIV8 31:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG0_WRITE_REQ_SB_REDUCE_DIV8_FULLSIZE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1 0x0041b864 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_TOTAL_SLOTS_REDUCE_DIV8 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_TOTAL_SLOTS_REDUCE_DIV8_FULLSIZE 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_TOTAL_SLOTS_REDUCE_DIV8_LOW_CLAMP 0x030 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_TOTAL_SUBREQS_REDUCE_DIV8 16:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_TOTAL_SUBREQS_REDUCE_DIV8_FULLSIZE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_TOTAL_SUBREQS_REDUCE_DIV8_LOW_CLAMP 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_RESERVED_SLOTS_DIV4 22:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_RESERVED_SLOTS_DIV4_INIT 0x02 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_RESERVED_SLOTS_DIV4_LOW_CLAMP 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_RESERVED_SUBREQS_DIV4 27:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_RESERVED_SUBREQS_DIV4_INIT 0x02 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_RESERVED_SUBREQS_DIV4_LOW_CLAMP 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_SLOTMAN_ALLOCATION 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_SLOTMAN_ALLOCATION_NORMAL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_SLOTMAN_ALLOCATION_OVERRIDE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_SAFEGUARDS 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_SAFEGUARDS_ALLOW_NORMAL_OPERATION 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_SAFEGUARDS_SUPPRESS_MEMORY_ACCESS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_SAFEGUARDS_SUPPRESS_ALL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_Z_SYNC 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_Z_SYNC_COUPLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_Z_SYNC_DECOUPLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG1_Z_SYNC__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS 0x0041b868 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_TOP_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_TOP_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_TOP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_TOP_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_TOP_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_TOP_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_TOP_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_TOP_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_FAULTING_OR_HALTING 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_FAULTING_OR_HALTING_NOT_IN_PROGRESS 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_FAULTING_OR_HALTING_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_SYNCHRONIZING_C_SIDE 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_SYNCHRONIZING_C_SIDE_NOT_IN_PROGRESS 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_SYNCHRONIZING_C_SIDE_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_SYNCHRONIZING_Z_SIDE 5:5 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_SYNCHRONIZING_Z_SIDE_NOT_IN_PROGRESS 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_SYNCHRONIZING_Z_SIDE_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CNIL 6:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CIL 7:7 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZNIL 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZIL 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_WRA_STATUS_SHORT 11:10 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_WRA_STATUS_SHORT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_WRA_STATUS_SHORT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_WRA_STATUS_SHORT_STALLED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_WRA_STATUS_SHORT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_WRS_STATUS_SHORT 13:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_WRS_STATUS_SHORT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_WRS_STATUS_SHORT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_WRS_STATUS_SHORT_STALLED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_WRS_STATUS_SHORT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_RWA_STATUS 16:14 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_RWA_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_RWA_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_RWA_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_RWA_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_RWA_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_RWA_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_RRH_RWA_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_ACK 17:17 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_ACK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_ACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_CREDIT 18:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_CREDIT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_CREDIT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_MSG_FIFO 19:19 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_MSG_FIFO_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_FE_MSG_FIFO_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_MEMBAR_ACK 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_MEMBAR_ACK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_MEMBAR_ACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_SCOREBOARD_ID 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_SCOREBOARD_ID_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_SCOREBOARD_ID_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_WDAT 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_WDAT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_WAIT_FOR_WDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_SCOREBOARD_NONEMPTY 23:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_SCOREBOARD_NONEMPTY_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_WRS_SCOREBOARD_NONEMPTY_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CIL 24:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CNIL 25:25 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZIL 26:26 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZNIL 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READPIPE_STATE 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READPIPE_STATE_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READPIPE_STATE_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READPIPE_STATE_STALLED_BY_RWA 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READPIPE_STATE_AWAITING_MEMSYS_RESPONSE 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READPIPE_STATE_STALLED_RRH2CRD_CNIL 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READPIPE_STATE_STALLED_RRH2CRD_CIL 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READPIPE_STATE_STALLED_RRH2ZRD_ZNIL 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READPIPE_STATE_STALLED_RRH2ZRD_ZIL 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READPIPE_STATE_SYNC_STALL 0x8 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_STATUS_READPIPE_STATE_OTHER 0x9 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0 0x0041b86c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_RD 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_WR 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_RD 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_WR 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_MEMBAR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_MEMBAR_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_RD 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_WR 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_MEMBAR 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_MEMBAR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_BACK_END_COPY_E_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_RD 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_WR 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_RD 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_WR 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_RD 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_WR 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD_FORCE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR_FORCE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_MEMBAR 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_MEMBAR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_MEMBAR_FORCE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_BLOCK_RD 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_MEMBAR 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_MEMBAR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_RD 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_WR 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_MEMBAR 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_MEMBAR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM 0x0041b870 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL_GRP_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2 13:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_GROUP_SEL2_GRP_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_PPM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG 0x0041b874 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG1 0x0041b878 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG3 0x0041b87c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_256 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_1024 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_4096 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_16384 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP 0x0041b8ff:0x0041b880 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1 0x0041b880 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CRD_COND_READ 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CRD_COND_READ_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CRD_COND_READ_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CRD_CREAD 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CRD_CREAD_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CRD_CREAD_FORCE_CREAD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CRD_CREAD_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_KNOBS 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_KNOBS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_RDSUPPRESS 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_RDSUPPRESS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_RDSUPPRESS_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_RDSUPPRESS_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_WRSUPPRESS 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_WRSUPPRESS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_WRSUPPRESS_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_WRSUPPRESS_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_CLEAR 16:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_CLEAR_ALL_BUNDLES_ALL_GLOBAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_CLEAR_FLUSHBUNDLES_ALL_GLOBAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_CACHE_CLEAR_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_WRITE_FULL_BE 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_WRITE_FULL_BE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_WRITE_FULL_BE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG1_WRITE_FULL_BE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2 0x0041b884 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_CACHE_ENTRY_ID_LIMIT 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_CACHE_ENTRY_ID_LIMIT_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT 17:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_ONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_TWO 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_THREE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_FOUR 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_FIVE 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_SIX 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_SEVEN 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_DISABLE 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_INIT 0x7 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_WR_OPT 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_WR_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_WR_OPT_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG2_WR_OPT_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3 0x0041b888 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_BLENDOPT_KILL 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_BLENDOPT_KILL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_BLENDOPT_KILL_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_BLENDOPT_FILL_OVERRIDE 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_BLENDOPT_FILL_OVERRIDE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_BLENDOPT_FILL_OVERRIDE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_C8_C16_DISABLE_COND_READ 4:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_NEVER 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_FOR_C8_1XAA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_FOR_CLEAR 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_ALWAYS 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_ARITHMETIC_SUCCESS 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_ARITHMETIC_SUCCESS_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_ARITHMETIC_SUCCESS_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_REDUCTION_SUCCESS 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_REDUCTION_SUCCESS_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_REDUCTION_SUCCESS_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_ARITHMETIC_DISABLE 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_ARITHMETIC_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_ARITHMETIC_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_REDUCTION_DISABLE 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_REDUCTION_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_REDUCTION_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_PROCESS_REDUCED_DISABLE 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_PROCESS_REDUCED_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_PROCESS_REDUCED_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_BOTH_DISABLE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_BOTH_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_BOTH_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_TIE_UP 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_TIE_UP_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_TIE_UP_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_ZBC_DISABLE 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_ZBC_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_ZBC_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_CC_DISABLE 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_CC_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_CC_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_UCOMP_MIXED_DISABLE 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_UCOMP_MIXED_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_UCOMP_MIXED_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT 23:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_128K 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_512K 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_2M 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_8M 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_32M 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_64M 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_128M 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_256M 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_512M 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_768M 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_1024M 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_1536M 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_2048M 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_NEVER 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_INIT 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA 25:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA_4TO1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA_8TO1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_TAG_FLUSH_CTL 27:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_TAG_FLUSH_CTL_ENTER_DECOMP_IN_PLACE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_TAG_FLUSH_CTL_CHANGE_DECOMP_IN_PLACE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_TAG_FLUSH_CTL_CHANGE_CLEAR_MODE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_TAG_FLUSH_CTL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4 0x0041b88c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_SRCPKTFIFO_REDUCE_DIV8 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_SRCPKTFIFO_REDUCE_DIV8_FULLSIZE 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_SRCPKTFIFO_REDUCE_DIV8_INIT 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_HASHENTRIES_REDUCE_DIV8 17:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_HASHENTRIES_REDUCE_DIV8_FULLSIZE 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_HASHENTRIES_REDUCE_DIV8_INIT 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_CLAMP_FP_BLEND 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_RMW_DISABLE_FORCE_ZERO 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_RMW_DISABLE_FORCE_ZERO_NO_FORCE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_RMW_DISABLE_FORCE_ZERO_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_PITCH_FORCE_DISALLOW_PLC 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_PITCH_FORCE_DISALLOW_PLC_NO_FORCE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_PITCH_FORCE_DISALLOW_PLC_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM 0x0041b894 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_STATIC_PATTERN_A55A_16_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_STATIC_PATTERN_5AA5_16_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2 13:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_STATIC_PATTERN_A55A_16_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_STATIC_PATTERN_5AA5_16_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_GROUP_SEL2_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PPM_ENABLE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG 0x0041b898 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG1 0x0041b89c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1 0x0041b8a0 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_RETIRE_STATUS 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_RETIRE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_RETIRE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_RETIRE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_RETIRE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_RETIRE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_RETIRE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_RETIRE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CSUB_STATUS 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CSUB_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CSUB_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CSUB_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CSUB_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CSUB_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CSUB_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CSUB_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_PIPE_STATUS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_PIPE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_PIPE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_PIPE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_PIPE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_PIPE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_PIPE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_PIPE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CWR_STATUS 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CWR_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CWR_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CWR_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CWR_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CWR_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CWR_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CWR_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_DECOMP_STATUS 16:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_DECOMP_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_DECOMP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_DECOMP_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_DECOMP_STATUS_STALLED 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_COMP_STATUS 18:17 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_COMP_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_COMP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_COMP_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_COMP_STATUS_STALLED 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_BLEND_STATUS 19:19 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_BLEND_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_BLEND_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_IL_NIL_FIFO_STATE 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_IL_NIL_FIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_IL_NIL_FIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_SEMAACK_FIFO_STATE 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_SEMAACK_FIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_SEMAACK_FIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_WACKFIFO_STATE 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_WACKFIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_WACKFIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_CC_STATE 26:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_CC_STATE_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_CC_STATE_GLOBAL_FLUSH_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_CC_STATE_PASS_PKTS 0xa /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_CC_STATE_PASS_BUNDLES 0xb /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_CC_STATE_PASS_EARLY_QUADS 0xc /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_TILE_IN_FLIGHT 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_TILE_IN_FLIGHT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_TILE_IN_FLIGHT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION 30:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRNL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRNL_1 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRNM 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRTM 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRNL 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRNL_1 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRNM 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRTM 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_WAITING_FOR_FLUSH 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_WAITING_FOR_FLUSH_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS1_CRD_WAITING_FOR_FLUSH_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS2 0x0041b8a4 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS2_TOP 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS2_TOP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS2_TOP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS2_TOP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS2_TOP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS2_TOP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS2_TOP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS2_TOP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS2_TAGS_IN_USE_COUNT 12:3 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS2_ILQUEUE_ENTRY_COUNT 22:13 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS2_CSUB_ENTRY_COUNT 31:23 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3 0x0041b8a8 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_RED_PREFETCH_ILOCK 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_RED_PREFETCH_ILOCK_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_RED_PREFETCH_ILOCK_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_WAIT_FOR_RDAT 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_WAIT_FOR_RDAT_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_WAIT_FOR_RDAT_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_SAMPLE_CONFLICT_ILOCK 2:2 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_SAMPLE_CONFLICT_ILOCK_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_SAMPLE_CONFLICT_ILOCK_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_SURFACE_KIND 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_SURFACE_KIND_BL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_SURFACE_KIND_PITCH 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_S0_STATE 5:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_S0_STATE_FIRST_OF_TILE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_S0_STATE_FIRST_OF_QUAD 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_S0_STATE_EXPAND_QUAD 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_S0_STATE_CUM_FILL 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CWR_RETIRE_QUEUE 7:7 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CWR_RETIRE_QUEUE_HASROOM 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CWR_RETIRE_QUEUE_FULL 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_INT_COMPUTE_ILOCK 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_INT_COMPUTE_ILOCK_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_CPROC_INT_COMPUTE_ILOCK_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_VALID_CACHETILES_COUNT 14:9 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_SPARE 31:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_STATUS3_SPARE_DEFAULT 0x00000 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG_COUNT_REQUESTS 0x0041b8ac /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG_COUNT_REQUESTS_CRD2RRH_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG_COUNT_REQUESTS_CRD2RRH_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG_COUNT_REQUESTS_CWR2RRH_PACKETS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG_COUNT_REQUESTS_CWR2RRH_PACKETS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG_COUNT_RESPONSES 0x0041b8b0 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG_COUNT_RESPONSES_RRH2CRD_RDAT_PACKETS_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG_COUNT_RESPONSES_RRH2CRD_RDAT_PACKETS_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG_COUNT_RESPONSES_RRH2CWR_ACKS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUG_COUNT_RESPONSES_RRH2CWR_ACKS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR 0x0041b8bc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_DEAD_TAGS 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_DEAD_TAGS_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_DEAD_TAGS_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_CACHE_HIT_FROM_OTHER_GPC 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_CACHE_HIT_FROM_OTHER_GPC_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_CACHE_HIT_FROM_OTHER_GPC_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_LONG_WAIT_ON_FREE_TAGS 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_LONG_WAIT_ON_FREE_TAGS_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_LONG_WAIT_ON_FREE_TAGS_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_LONG_WAIT_ON_WRITEACK 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_LONG_WAIT_ON_WRITEACK_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_LONG_WAIT_ON_WRITEACK_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_NO_FREE_CLEAN_CACHE_ENTRY 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_NO_FREE_CLEAN_CACHE_ENTRY_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_NO_FREE_CLEAN_CACHE_ENTRY_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_L2ACK_BUT_WACKFIFO_EMPTY 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_L2ACK_BUT_WACKFIFO_EMPTY_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CRD_L2ACK_BUT_WACKFIFO_EMPTY_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CPROC_LONG_WAIT_ON_RDAT 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CPROC_LONG_WAIT_ON_RDAT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CPROC_LONG_WAIT_ON_RDAT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_BLEND_FP32_NO_CHANNEL_EN 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_BLEND_FP32_NO_CHANNEL_EN_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_BLEND_FP32_NO_CHANNEL_EN_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_BLEND_SKID 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_BLEND_SKID_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_BLEND_SKID_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CWR_NO_EOCP_BW_TILES 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CWR_NO_EOCP_BW_TILES_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_CWR_NO_EOCP_BW_TILES_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_BLKACTIVITY_ERROR 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_BLKACTIVITY_ERROR_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_BLKACTIVITY_ERROR_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_HWW_ESR_EN_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF 0x0041b8c0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_FULLSPEED 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_03125 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_06250 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_09375 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_12500 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_15625 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_18750 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_21875 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_25000 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_28125 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_31250 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_34375 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_37500 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_40625 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_43750 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_46875 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_50000 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_53125 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_56250 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_59375 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_62500 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_65625 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_68750 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_71875 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_75000 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_78125 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_81250 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_84375 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_87500 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_90625 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_93750 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_PERF_THROTTLE_PIPE_0_96875 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x0041b8c4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_A 0x0041b8c8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_A__PRIV_LEVEL_MASK 0x0041b8c4 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_A_INTERCEPT 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_A_INTERCEPT_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_A_WT_1 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_A_WT_1_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_A_WT_2 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_A_WT_2_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_B 0x0041b8cc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_B__PRIV_LEVEL_MASK 0x0041b8c4 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_B_WT_3 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_B_WT_3_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_B_WT_4 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_B_WT_4_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_B_WT_5 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_B_WT_5_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_C 0x0041b8d0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_C__PRIV_LEVEL_MASK 0x0041b8c4 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_C_WT_6 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_C_WT_6_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_C_WT_7 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_C_WT_7_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_C_WT_8 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_C_WT_8_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_D 0x0041b8d4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_D__PRIV_LEVEL_MASK 0x0041b8c4 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_D_WT_9 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_D_WT_9_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_D_WT_10 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_D_WT_10_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_D_WT_11 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_D_WT_11_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_E 0x0041b8d8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_E__PRIV_LEVEL_MASK 0x0041b8c4 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_E_WT_12 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_E_WT_12_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_E_WT_13 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_E_WT_13_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_E_WT_14 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_E_WT_14_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_F 0x0041b8dc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_F__PRIV_LEVEL_MASK 0x0041b8c4 /* */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_F_WT_15 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_F_WT_15_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_F_WT_16 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_BLK_ACT_F_WT_16_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP 0x0041b8e0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_PART2_SEL 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_PART2_SEL_DECOMP 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_PART2_SEL_COMP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_SPARE 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_PM_SEL_SPARE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL 12:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_PART2_SEL 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_PART2_SEL_DECOMP 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_PART2_SEL_COMP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_SPARE 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_SPARE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL 18:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_CRD 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_CRD_CACHE_CTRL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_PIPE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_PIPE_BLEND 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_CWR 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_COMP_DECOMP 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_SPARE 31:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_GROUP_SPARE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_TRIGGER 0x0041b8e4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_TRIGGER_MASK 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_TRIGGER_MASK_NONE 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_TRIGGER_VALUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_DEBUGPORT_TRIGGER_VALUE_ZERO 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_SETTINGS 0x0041b8e8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_SETTINGS_BLENDER_LANA_OPT 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_SETTINGS_BLENDER_LANA_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_SETTINGS_BLENDER_LANA_OPT_ONE_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_SETTINGS_BLENDER_LANA_OPT_TWO_ONLY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_SETTINGS_BLENDER_LANA_OPT_ENABLED 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_INDEX 0x0041b8b4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_INDEX_ADDRESS 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_INDEX_ADDRESS_RESERVED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_INDEX_ADDRESS_MIN 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_INDEX_ADDRESS_MAX 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_INDEX_ADDRESS_NUM_LEGAL_INDICES_MINUS_ONE 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_0 0x0041b8ec /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_0_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_0_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_1 0x0041b8f0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_1_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_1_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_2 0x0041b8f4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_2_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_2_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_3 0x0041b8f8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_3_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_COLOR_CLEAR_VALUE_3_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_VALID_FLAGS 0x0041b8fc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_VALID_FLAGS_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROP0_CROP_ZBC_VALID_FLAGS_V_ALL_INVALID 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROP1 0x0041ba00 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_ROPS 0x0041bc00 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP 0x0041bc5f:0x0041bc00 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1 0x0041bc00 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZRD_NO_COND_READ 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZRD_NO_COND_READ_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZRD_NO_COND_READ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZRD_NO_COND_READ_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_CLEAR 11:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_CLEAR_ALL_BUNDLES_ALL_GLOBAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_CLEAR_FLUSHBUNDLES_ALL_GLOBAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_CLEAR_LITE_FLUSHBUNDLES_PERGPC 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_CLEAR_NO_BUNDLES 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_CLEAR_INIT 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_Z 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_Z_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_Z_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_Z_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_STENCIL_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND 16:16 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_DEPTHBOUND_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR 17:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_NEARFAR_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX_DISABLED 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_IGNORE_ZMINMAX_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_CACHE_HIT_FROM_OTHER_GPC_IGNORE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZRD_RDAT_SCRUBBER_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_ZCULL_TWO_Z_1XAA_UPDATES_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_FORCE_L2_WAKE 31:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_FORCE_L2_WAKE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_FORCE_L2_WAKE_ON_NONIDLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_FORCE_L2_WAKE_ALWAYS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG1_FORCE_L2_WAKE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2 0x0041bc04 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_FORCE_VISIBLE 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_FORCE_VISIBLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_FORCE_VISIBLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_FORCE_VISIBLE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_COMPRESS_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ 5:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_INHIBIT_SKIP_WR_EQ_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_RTL_KNOBS 27:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_RTL_KNOBS_INIT 0x0000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_WRITE_FULL_BE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_WRITE_FULL_BE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_WRITE_FULL_BE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_WRITE_FULL_BE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_DISABLE_FULL_WE_OPT 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG2_ZWR_DISABLE_FULL_WE_OPT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3 0x0041bc08 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_INNER_IL_COVG_AWARE 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_INNER_IL_COVG_AWARE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_INNER_IL_COVG_AWARE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_INNER_IL_COVG_AWARE_ONLY_1_STAGE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_INNER_IL_COVG_AWARE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_TWO_SUBPACKET_COMPRESSION_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8 7:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8_NOREDUCE 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8_FULLSIZE 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_SRCPKTFIFO_REDUCE_DIV8_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_HASHENTRIES_REDUCE_DIV8 12:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_HASHENTRIES_REDUCE_DIV8_FULLSIZE 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_HASHENTRIES_REDUCE_DIV8_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_RTL_KNOBS 27:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_RTL_KNOBS_INIT 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_COALESCE_WRITES 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_COALESCE_WRITES_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_COALESCE_WRITES_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG3_COALESCE_WRITES_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4 0x0041bc0c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_PM_LOCAL_TRIGGER_GPC 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_PM_LOCAL_TRIGGER_GPC_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_S8_COALESCER_LIMIT 11:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_S8_COALESCER_LIMIT_MAX 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_S8_COALESCER_LIMIT_ZERO 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_S8_COALESCER_LIMIT_INIT 0x7 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_S8_COALESCER_TIMEOUT 13:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_S8_COALESCER_TIMEOUT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_S8_COALESCER_TIMEOUT_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_BURSTY_MIN_GEAR 18:17 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_BURSTY_MIN_GEAR_DISABLE_BURSTING 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_BURSTY_MIN_GEAR_FULL_RANGE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_BURSTY_MIN_GEAR_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_RTL_KNOBS 26:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_RTL_KNOBS_INIT 0x00 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW 28:27 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW_NONE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW_S8_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_IGNORE_RDATCHECK_HWW_ALL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW 30:30 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_SPARE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG4_SPARE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5 0x0041bc10 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5_SRCPKTFIFO_REDUCE_DIV256 3:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5_SRCPKTFIFO_REDUCE_DIV256_FULLSIZE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5_HASHENTRIES_REDUCE_DIV256 7:4 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5_HASHENTRIES_REDUCE_DIV256_FULLSIZE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT0 17:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT0_ORIGINAL_GALOIS 0x1ad /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT0_AVOID_ROPSLICE_MAP_A 0x255 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT0_AVOID_ROPSLICE_MAP_B 0x015 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT1 27:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT1_ORIGINAL_GALOIS 0x2f6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT1_AVOID_ROPSLICE_MAP_A 0x2c4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG5_TAGBANK_TAPS_BIT1_AVOID_ROPSLICE_MAP_B 0x0c4 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM 0x0041bc14 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_STATIC_PATTERN_25_6_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_STATIC_PATTERN_1A_6_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2 13:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_STATIC_PATTERN_25_6_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_STATIC_PATTERN_1A_6_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_GROUP_SEL2_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP10 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP11 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP12 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP13 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP14 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_STATIC_PATTERN_25_6_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_GRP15 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_STATIC_PATTERN_1A_6_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2 25:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP0 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP2 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP3 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP4 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP5 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP6 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP7 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP8 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP9 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP10 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP11 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP12 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP13 0xd /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP14 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_STATIC_PATTERN_25_6_GROUP 0xe /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_GRP15 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_STATIC_PATTERN_1A_6_GROUP 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_COUNT_SEL2_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PPM_ENABLE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG 0x0041bc18 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG1 0x0041bc1c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS 0x0041bc20 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_DECODER_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_DECODER_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_DECODER_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_DECODER_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_DECODER_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_DECODER_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_DECODER_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_DECODER_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZRDPIPE_STATUS 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZRDPIPE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_LTCTRACK_STATUS 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_LTCTRACK_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_LTCTRACK_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_LTCTRACK_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_LTCTRACK_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_LTCTRACK_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_LTCTRACK_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_LTCTRACK_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZSUB_STATUS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZSUB_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZSUB_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZSUB_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZSUB_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZSUB_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZSUB_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZSUB_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_BPC_STATUS 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_BPC_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_BPC_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_BPC_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_BPC_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_BPC_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_BPC_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_BPC_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PACKETIZER_STATUS 17:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PACKETIZER_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PACKETIZER_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PACKETIZER_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PACKETIZER_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PACKETIZER_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PACKETIZER_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PACKETIZER_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PIPE_STATUS 20:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PIPE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PIPE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PIPE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PIPE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PIPE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PIPE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_PIPE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZWR_STATUS 23:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZWR_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZWR_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZWR_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZWR_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZWR_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZWR_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZWR_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_RETIRE_STATUS 26:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_RETIRE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_RETIRE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_RETIRE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_RETIRE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_RETIRE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_RETIRE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_RETIRE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZCULL_STATUS 29:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZCULL_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZCULL_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZCULL_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZCULL_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZCULL_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZCULL_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_ZCULL_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_WACKFIFO_STATE 30:30 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_WACKFIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS_WACKFIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2 0x0041bc24 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2_TOP 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2_TOP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2_TOP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2_TOP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2_TOP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2_TOP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2_TOP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2_TOP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2_TAGS_IN_USE_COUNT 11:3 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2_ILQUEUE_ENTRY_COUNT 18:12 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2_ZSUB_ENTRY_COUNT 27:19 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_STATUS2_VALID_CACHETILES_COUNT 31:28 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG_COUNT_REQUESTS 0x0041bc28 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG_COUNT_REQUESTS_ZRD2RRH_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG_COUNT_REQUESTS_ZRD2RRH_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG_COUNT_REQUESTS_ZWR2RRH_PACKETS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG_COUNT_REQUESTS_ZWR2RRH_PACKETS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG_COUNT_RESPONSES 0x0041bc2c /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZRD_RDAT_PACKETS_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZRD_RDAT_PACKETS_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZWR_ACKS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_DEBUG_COUNT_RESPONSES_RRH2ZWR_ACKS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR 0x0041bc38 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_DEAD_TAGS 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_DEAD_TAGS_NOT_PRESENT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_DEAD_TAGS_PRESENT 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_DEAD_TAGS_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_CACHE_HIT_FROM_OTHER_GPC_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_RDAT_ORPHANS 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_RDAT_ORPHANS_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_RDAT_ORPHANS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_RDAT_ORPHANS_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_EOZP_MISMATCH 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_EOZP_MISMATCH_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_EOZP_MISMATCH_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_EOZP_MISMATCH_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_ZWRRAM_ORPHANS 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_ZWRRAM_ORPHANS_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_ZWRRAM_ORPHANS_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_ZWRRAM_ORPHANS_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_RDAT_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_LONG_WAIT_ON_WRITEACK_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_HUNG_ON_IL_THREAD_RDAT_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_HUNG_ON_NIL_THREAD_RDAT_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_BLKACTIVITY_ERROR 11:11 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_BLKACTIVITY_ERROR_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_BLKACTIVITY_ERROR_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_BLKACTIVITY_ERROR_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN 12:12 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_Z_DATA_RETURN_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN 13:13 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN_FALSE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_L2_ILLEGAL_STENCIL_DATA_RETURN_INIT 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_HWW_ESR_EN_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF 0x0041bc54 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_FULLSPEED 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_03125 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_06250 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_09375 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_12500 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_15625 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_18750 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_21875 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_25000 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_28125 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_31250 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_34375 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_37500 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_40625 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_43750 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_46875 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_50000 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_53125 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_56250 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_59375 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_62500 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_65625 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_68750 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_71875 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_75000 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_78125 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_81250 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_84375 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_87500 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_90625 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_93750 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_PERF_THROTTLE_PIPE_0_96875 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x0041bc40 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_A 0x0041bc44 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_A__PRIV_LEVEL_MASK 0x0041bc40 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_A_INTERCEPT 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_A_INTERCEPT_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_A_WEIGHT_1 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_A_WEIGHT_1_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_A_WEIGHT_2 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_A_WEIGHT_2_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_B 0x0041bc48 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_B__PRIV_LEVEL_MASK 0x0041bc40 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_B_WEIGHT_3 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_B_WEIGHT_3_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_B_WEIGHT_4 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_B_WEIGHT_4_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_B_WEIGHT_5 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_B_WEIGHT_5_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_C 0x0041bc4c /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_C__PRIV_LEVEL_MASK 0x0041bc40 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_C_WEIGHT_6 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_C_WEIGHT_6_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_C_WEIGHT_7 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_C_WEIGHT_7_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_C_WEIGHT_8 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_C_WEIGHT_8_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_D 0x0041bc50 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_D__PRIV_LEVEL_MASK 0x0041bc40 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_D_WEIGHT_9 8:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_D_WEIGHT_9_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_D_WEIGHT_10 17:9 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_D_WEIGHT_10_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_D_WEIGHT_11 26:18 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_ZROP_BLK_ACTIVITY_D_WEIGHT_11_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH 0x0041bc7f:0x0041bc60 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0 0x0041bc60 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RRA_FAVOR_IL 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RRA_FAVOR_IL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RRA_FAVOR_IL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RRA_FAVOR_Z 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RRA_FAVOR_Z_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RRA_FAVOR_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RRA_IL_DELAY 5:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RRA_IL_DELAY_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RC_FAVOR_IL 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RC_FAVOR_IL_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RC_FAVOR_IL_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RC_FAVOR_Z 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RC_FAVOR_Z_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RC_FAVOR_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_WRA_FAVOR_Z 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_WRA_FAVOR_Z_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_WRA_FAVOR_Z_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RW_ARB_BURST_SIZE 12:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RW_ARB_BURST_SIZE_ONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_RW_ARB_BURST_SIZE_INIT 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA_4TO1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA_8TO1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_REDUCTION_RATIO_IN_1XAA_INIT 0x2 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_CONCAT_WRITE_COMP 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_CONCAT_WRITE_COMP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_CONCAT_WRITE_COMP_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_CONCAT_WRITE_UNCOMP 16:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_CONCAT_WRITE_UNCOMP_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_CONCAT_WRITE_UNCOMP_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_CONCAT_WRITE_FCLR 17:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_CONCAT_WRITE_FCLR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_CONCAT_WRITE_FCLR_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_C 18:18 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_C_WARM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_C_NONE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_Z 19:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_Z_WARM 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_WARMING_REQ_ISSUE_CONTROL_Z_NONE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_FE_MSG_FIFO_REDUCE 25:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_FE_MSG_FIFO_REDUCE_FULLSIZE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_WRITE_REQ_SB_REDUCE_DIV8 31:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG0_WRITE_REQ_SB_REDUCE_DIV8_FULLSIZE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1 0x0041bc64 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_TOTAL_SLOTS_REDUCE_DIV8 8:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_TOTAL_SLOTS_REDUCE_DIV8_FULLSIZE 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_TOTAL_SLOTS_REDUCE_DIV8_LOW_CLAMP 0x030 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_TOTAL_SUBREQS_REDUCE_DIV8 16:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_TOTAL_SUBREQS_REDUCE_DIV8_FULLSIZE 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_TOTAL_SUBREQS_REDUCE_DIV8_LOW_CLAMP 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_RESERVED_SLOTS_DIV4 22:17 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_RESERVED_SLOTS_DIV4_INIT 0x02 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_RESERVED_SLOTS_DIV4_LOW_CLAMP 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_RESERVED_SUBREQS_DIV4 27:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_RESERVED_SUBREQS_DIV4_INIT 0x02 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_RESERVED_SUBREQS_DIV4_LOW_CLAMP 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_SLOTMAN_ALLOCATION 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_SLOTMAN_ALLOCATION_NORMAL 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_SLOTMAN_ALLOCATION_OVERRIDE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_SAFEGUARDS 30:29 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_SAFEGUARDS_ALLOW_NORMAL_OPERATION 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_SAFEGUARDS_SUPPRESS_MEMORY_ACCESS 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_SAFEGUARDS_SUPPRESS_ALL 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_Z_SYNC 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_Z_SYNC_COUPLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_Z_SYNC_DECOUPLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG1_Z_SYNC__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS 0x0041bc68 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_TOP_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_TOP_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_TOP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_TOP_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_TOP_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_TOP_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_TOP_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_TOP_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_FAULTING_OR_HALTING 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_FAULTING_OR_HALTING_NOT_IN_PROGRESS 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_FAULTING_OR_HALTING_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_SYNCHRONIZING_C_SIDE 4:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_SYNCHRONIZING_C_SIDE_NOT_IN_PROGRESS 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_SYNCHRONIZING_C_SIDE_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_SYNCHRONIZING_Z_SIDE 5:5 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_SYNCHRONIZING_Z_SIDE_NOT_IN_PROGRESS 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_SYNCHRONIZING_Z_SIDE_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CNIL 6:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CIL 7:7 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_CIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZNIL 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZIL 9:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_NO_AVAIL_SLOTS_OR_SUBREQS_ZIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_WRA_STATUS_SHORT 11:10 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_WRA_STATUS_SHORT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_WRA_STATUS_SHORT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_WRA_STATUS_SHORT_STALLED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_WRA_STATUS_SHORT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_WRS_STATUS_SHORT 13:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_WRS_STATUS_SHORT_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_WRS_STATUS_SHORT_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_WRS_STATUS_SHORT_STALLED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_WRS_STATUS_SHORT_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_RWA_STATUS 16:14 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_RWA_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_RWA_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_RWA_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_RWA_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_RWA_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_RWA_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_RRH_RWA_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_ACK 17:17 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_ACK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_ACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_CREDIT 18:18 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_CREDIT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_CREDIT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_MSG_FIFO 19:19 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_MSG_FIFO_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_FE_MSG_FIFO_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_MEMBAR_ACK 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_MEMBAR_ACK_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_MEMBAR_ACK_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_SCOREBOARD_ID 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_SCOREBOARD_ID_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_SCOREBOARD_ID_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_WDAT 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_WDAT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_WAIT_FOR_WDAT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_SCOREBOARD_NONEMPTY 23:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_SCOREBOARD_NONEMPTY_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_WRS_SCOREBOARD_NONEMPTY_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CIL 24:24 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CNIL 25:25 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_CNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZIL 26:26 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZNIL 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZNIL_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READ_THREAD_ENTIRELY_STALLED_ZNIL_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READPIPE_STATE 31:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READPIPE_STATE_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READPIPE_STATE_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READPIPE_STATE_STALLED_BY_RWA 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READPIPE_STATE_AWAITING_MEMSYS_RESPONSE 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READPIPE_STATE_STALLED_RRH2CRD_CNIL 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READPIPE_STATE_STALLED_RRH2CRD_CIL 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READPIPE_STATE_STALLED_RRH2ZRD_ZNIL 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READPIPE_STATE_STALLED_RRH2ZRD_ZIL 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READPIPE_STATE_SYNC_STALL 0x8 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_STATUS_READPIPE_STATE_OTHER 0x9 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0 0x0041bc6c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_RD 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_WR 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_PENDING_WRITES_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_RD 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_WR 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_MEMBAR 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_MEMBAR_DEFAULT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_REPORT_SEMAPHORE_D_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_RD 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_WR 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_MEMBAR 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_MEMBAR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_BACK_END_COPY_E_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_RD 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_WR 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_PM_TRIGGER_END_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_RD 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_WR 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLITFINISHED_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_RD 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_WR 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_PIXEL_SHADER_BARRIER_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD 20:20 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD_FORCE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_RD__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR 21:21 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR_FORCE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BLOCK_WR__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_MEMBAR 22:22 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_MEMBAR_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_MEMBAR_FORCE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_BLOCK_RD 23:23 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_MEMBAR 24:24 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_MEMBAR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_RSTR2D_BLIT_CORRAL_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_RD 25:25 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_RD_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_RD_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_WR 26:26 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_WR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_BLOCK_WR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_MEMBAR 27:27 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_MEMBAR_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_SYNC_CTRL0_TWOD_MAPPING_SYNC_MEMBAR_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM 0x0041bc70 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL_GRP_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2 13:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_GROUP_SEL2_GRP_31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_PPM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG 0x0041bc74 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG1 0x0041bc78 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG3 0x0041bc7c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_256 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_1024 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_4096 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_16384 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_RRH_DEBUG3_HWW_SEMAACK_HOLDOFF_CYCLES_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP 0x0041bcff:0x0041bc80 /* RW--L */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1 0x0041bc80 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CRD_COND_READ 1:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CRD_COND_READ_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CRD_COND_READ_DISABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CRD_CREAD 3:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CRD_CREAD_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CRD_CREAD_FORCE_CREAD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CRD_CREAD_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_KNOBS 7:5 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_KNOBS_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_RDSUPPRESS 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_RDSUPPRESS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_RDSUPPRESS_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_RDSUPPRESS_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_WRSUPPRESS 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_WRSUPPRESS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_WRSUPPRESS_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_WRSUPPRESS_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_CLEAR 16:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_CLEAR_ALL_BUNDLES_ALL_GLOBAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_CLEAR_FLUSHBUNDLES_ALL_GLOBAL 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_CACHE_CLEAR_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_WRITE_FULL_BE 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_WRITE_FULL_BE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_WRITE_FULL_BE_ENABLE 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG1_WRITE_FULL_BE_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2 0x0041bc84 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_CACHE_ENTRY_ID_LIMIT 7:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_CACHE_ENTRY_ID_LIMIT_INIT 0xff /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT 17:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_ONE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_TWO 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_THREE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_FOUR 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_FIVE 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_SIX 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_SEVEN 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_DISABLE 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_ITERATED_BLEND_LOOP_LIMIT_INIT 0x7 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_WR_OPT 29:29 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_WR_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_WR_OPT_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG2_WR_OPT_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3 0x0041bc88 /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_BLENDOPT_KILL 0:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_BLENDOPT_KILL_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_BLENDOPT_KILL_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS 1:1 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_BLENDOPT_FILL_OVERRIDE 2:2 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_BLENDOPT_FILL_OVERRIDE_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_BLENDOPT_FILL_OVERRIDE_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_C8_C16_DISABLE_COND_READ 4:3 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_NEVER 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_FOR_C8_1XAA 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_FOR_CLEAR 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_C8_C16_DISABLE_COND_READ_ALWAYS 0x3 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_ARITHMETIC_SUCCESS 6:6 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_ARITHMETIC_SUCCESS_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_ARITHMETIC_SUCCESS_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_REDUCTION_SUCCESS 7:7 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_REDUCTION_SUCCESS_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_REDUCTION_SUCCESS_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_ARITHMETIC_DISABLE 8:8 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_ARITHMETIC_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_ARITHMETIC_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_REDUCTION_DISABLE 9:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_REDUCTION_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_REDUCTION_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_PROCESS_REDUCED_DISABLE 10:10 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_PROCESS_REDUCED_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_PROCESS_REDUCED_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_BOTH_DISABLE 11:11 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_BOTH_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_BOTH_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_TIE_UP 12:12 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_TIE_UP_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_BLENDOPT_READ_SUPPRESS_TIE_UP_ENABLED 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_ZBC_DISABLE 13:13 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_ZBC_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_ZBC_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_CC_DISABLE 14:14 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_CC_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_CC_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_UCOMP_MIXED_DISABLE 15:15 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_UCOMP_MIXED_DISABLE_NORMAL 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_UCOMP_MIXED_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT 23:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_128K 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_512K 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_2M 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_8M 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_32M 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_64M 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_128M 0x6 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_256M 0x7 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_512M 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_768M 0x9 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_1024M 0xa /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_1536M 0xb /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_2048M 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_NEVER 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CROP_CC_TAGREL_TIMEOUT_INIT 0xc /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA 25:24 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA_4TO1 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA_8TO1 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_REDUCTION_RATIO_IN_1XAA_INIT 0x2 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_TAG_FLUSH_CTL 27:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_TAG_FLUSH_CTL_ENTER_DECOMP_IN_PLACE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_TAG_FLUSH_CTL_CHANGE_DECOMP_IN_PLACE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_TAG_FLUSH_CTL_CHANGE_CLEAR_MODE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_TAG_FLUSH_CTL_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE 28:28 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_CACHE_HIT_FROM_OTHER_GPC_IGNORE_INIT 0x1 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE 31:31 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_NORMAL 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4 0x0041bc8c /* RWI4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_SRCPKTFIFO_REDUCE_DIV8 8:0 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_SRCPKTFIFO_REDUCE_DIV8_FULLSIZE 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_SRCPKTFIFO_REDUCE_DIV8_INIT 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_HASHENTRIES_REDUCE_DIV8 17:9 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_HASHENTRIES_REDUCE_DIV8_FULLSIZE 0x000 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_HASHENTRIES_REDUCE_DIV8_INIT 0x000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_CLAMP_FP_BLEND 18:18 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_RMW_DISABLE_FORCE_ZERO 19:19 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_RMW_DISABLE_FORCE_ZERO_NO_FORCE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_RMW_DISABLE_FORCE_ZERO_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_PITCH_FORCE_DISALLOW_PLC 20:20 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_PITCH_FORCE_DISALLOW_PLC_NO_FORCE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_PITCH_FORCE_DISALLOW_PLC_FORCE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE 25:25 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_GOIDLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW 26:26 /* RWIVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_DISABLE 0x0 /* RWI-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG4_RESET_DEBUG_COUNTERS_ON_FPW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM 0x0041bc94 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_STATIC_PATTERN_A55A_16_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_STATIC_PATTERN_5AA5_16_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2 13:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP32 0x20 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP33 0x21 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP34 0x22 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP35 0x23 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP36 0x24 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP37 0x25 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP38 0x26 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP39 0x27 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP40 0x28 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP41 0x29 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP42 0x2a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP43 0x2b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP44 0x2c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP45 0x2d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP46 0x2e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP47 0x2f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP48 0x30 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP49 0x31 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP50 0x32 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP51 0x33 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP52 0x34 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP53 0x35 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP54 0x36 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP55 0x37 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP56 0x38 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP57 0x39 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP58 0x3a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP59 0x3b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP60 0x3c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP61 0x3d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP62 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_STATIC_PATTERN_A55A_16_GROUP 0x3e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_GRP63 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_STATIC_PATTERN_5AA5_16_GROUP 0x3f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_GROUP_SEL2_INIT 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_ENABLE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_ENABLE_DISABLE 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PPM_ENABLE_INIT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG 0x0041bc98 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_QUIESCENT_CG_EN__PROD 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG1 0x0041bc9c /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG1_SLCG_ENABLED 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG1_SLCG_DISABLED 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_CG1_SLCG__PROD 0x0000 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1 0x0041bca0 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_STATUS 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_RETIRE_STATUS 5:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_RETIRE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_RETIRE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_RETIRE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_RETIRE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_RETIRE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_RETIRE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_RETIRE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CSUB_STATUS 8:6 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CSUB_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CSUB_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CSUB_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CSUB_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CSUB_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CSUB_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CSUB_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_PIPE_STATUS 11:9 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_PIPE_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_PIPE_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_PIPE_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_PIPE_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_PIPE_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_PIPE_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_PIPE_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CWR_STATUS 14:12 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CWR_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CWR_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CWR_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CWR_STATUS_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CWR_STATUS_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CWR_STATUS_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CWR_STATUS_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_DECOMP_STATUS 16:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_DECOMP_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_DECOMP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_DECOMP_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_DECOMP_STATUS_STALLED 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_COMP_STATUS 18:17 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_COMP_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_COMP_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_COMP_STATUS_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_COMP_STATUS_STALLED 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_BLEND_STATUS 19:19 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_BLEND_STATUS_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_BLEND_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_IL_NIL_FIFO_STATE 20:20 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_IL_NIL_FIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_IL_NIL_FIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_SEMAACK_FIFO_STATE 21:21 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_SEMAACK_FIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_SEMAACK_FIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_WACKFIFO_STATE 22:22 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_WACKFIFO_STATE_FULL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_WACKFIFO_STATE_HASROOM 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_CC_STATE 26:23 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_CC_STATE_IDLE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_CC_STATE_GLOBAL_FLUSH_IN_PROGRESS 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_CC_STATE_PASS_PKTS 0xa /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_CC_STATE_PASS_BUNDLES 0xb /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_CC_STATE_PASS_EARLY_QUADS 0xc /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_TILE_IN_FLIGHT 27:27 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_TILE_IN_FLIGHT_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_TILE_IN_FLIGHT_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION 30:28 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRNL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRNL_1 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRNM 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_NRTM 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRNL 0x4 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRNL_1 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRNM 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_TAG_TABLE_ACTION_TRTM 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_WAITING_FOR_FLUSH 31:31 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_WAITING_FOR_FLUSH_FALSE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS1_CRD_WAITING_FOR_FLUSH_TRUE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS2 0x0041bca4 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS2_TOP 2:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS2_TOP_EMPTY 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS2_TOP_ACTIVE 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS2_TOP_PAUSED 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS2_TOP_QUIESCENT 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS2_TOP_STALLED 0x5 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS2_TOP_FAULTED 0x6 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS2_TOP_HALTED 0x7 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS2_TAGS_IN_USE_COUNT 12:3 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS2_ILQUEUE_ENTRY_COUNT 22:13 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS2_CSUB_ENTRY_COUNT 31:23 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3 0x0041bca8 /* R--4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_RED_PREFETCH_ILOCK 0:0 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_RED_PREFETCH_ILOCK_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_RED_PREFETCH_ILOCK_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_WAIT_FOR_RDAT 1:1 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_WAIT_FOR_RDAT_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_WAIT_FOR_RDAT_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_SAMPLE_CONFLICT_ILOCK 2:2 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_SAMPLE_CONFLICT_ILOCK_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_SAMPLE_CONFLICT_ILOCK_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_SURFACE_KIND 3:3 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_SURFACE_KIND_BL 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_SURFACE_KIND_PITCH 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_S0_STATE 5:4 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_S0_STATE_FIRST_OF_TILE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_S0_STATE_FIRST_OF_QUAD 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_S0_STATE_EXPAND_QUAD 0x2 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_S0_STATE_CUM_FILL 0x3 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CWR_RETIRE_QUEUE 7:7 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CWR_RETIRE_QUEUE_HASROOM 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CWR_RETIRE_QUEUE_FULL 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_INT_COMPUTE_ILOCK 8:8 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_INT_COMPUTE_ILOCK_NONE 0x0 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_CPROC_INT_COMPUTE_ILOCK_STALLED 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_VALID_CACHETILES_COUNT 14:9 /* R-XUF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_SPARE 31:15 /* R-XVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_STATUS3_SPARE_DEFAULT 0x00000 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG_COUNT_REQUESTS 0x0041bcac /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG_COUNT_REQUESTS_CRD2RRH_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG_COUNT_REQUESTS_CRD2RRH_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG_COUNT_REQUESTS_CWR2RRH_PACKETS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG_COUNT_REQUESTS_CWR2RRH_PACKETS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG_COUNT_RESPONSES 0x0041bcb0 /* R-E4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG_COUNT_RESPONSES_RRH2CRD_RDAT_PACKETS_V 18:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG_COUNT_RESPONSES_RRH2CRD_RDAT_PACKETS_V_NONE 0x00000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG_COUNT_RESPONSES_RRH2CWR_ACKS_V 31:19 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUG_COUNT_RESPONSES_RRH2CWR_ACKS_V_NONE 0x0000 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR 0x0041bcbc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_DEAD_TAGS 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_DEAD_TAGS_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_DEAD_TAGS_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_CACHE_HIT_FROM_OTHER_GPC 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_CACHE_HIT_FROM_OTHER_GPC_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_CACHE_HIT_FROM_OTHER_GPC_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_LONG_WAIT_ON_FREE_TAGS 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_LONG_WAIT_ON_FREE_TAGS_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_LONG_WAIT_ON_FREE_TAGS_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_LONG_WAIT_ON_WRITEACK 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_LONG_WAIT_ON_WRITEACK_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_LONG_WAIT_ON_WRITEACK_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_NO_FREE_CLEAN_CACHE_ENTRY 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_NO_FREE_CLEAN_CACHE_ENTRY_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_NO_FREE_CLEAN_CACHE_ENTRY_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_L2ACK_BUT_WACKFIFO_EMPTY 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_L2ACK_BUT_WACKFIFO_EMPTY_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CRD_L2ACK_BUT_WACKFIFO_EMPTY_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CPROC_LONG_WAIT_ON_RDAT 6:6 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CPROC_LONG_WAIT_ON_RDAT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CPROC_LONG_WAIT_ON_RDAT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_BLEND_FP32_NO_CHANNEL_EN 7:7 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_BLEND_FP32_NO_CHANNEL_EN_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_BLEND_FP32_NO_CHANNEL_EN_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_BLEND_SKID 8:8 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_BLEND_SKID_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_BLEND_SKID_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CWR_NO_EOCP_BW_TILES 9:9 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CWR_NO_EOCP_BW_TILES_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_CWR_NO_EOCP_BW_TILES_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_BLKACTIVITY_ERROR 10:10 /* R-EVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_BLKACTIVITY_ERROR_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_BLKACTIVITY_ERROR_VIOL_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_HWW_ESR_EN_INIT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF 0x0041bcc0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_FULLSPEED 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_03125 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_06250 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_09375 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_12500 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_15625 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_18750 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_21875 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_25000 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_28125 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_31250 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_34375 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_37500 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_40625 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_43750 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_46875 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_50000 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_53125 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_56250 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_59375 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_62500 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_65625 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_68750 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_71875 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_75000 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_78125 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_81250 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_84375 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_87500 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_90625 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_93750 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_PERF_THROTTLE_PIPE_0_96875 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x0041bcc4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_A 0x0041bcc8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_A__PRIV_LEVEL_MASK 0x0041bcc4 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_A_INTERCEPT 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_A_INTERCEPT_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_A_WT_1 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_A_WT_1_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_A_WT_2 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_A_WT_2_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_B 0x0041bccc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_B__PRIV_LEVEL_MASK 0x0041bcc4 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_B_WT_3 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_B_WT_3_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_B_WT_4 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_B_WT_4_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_B_WT_5 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_B_WT_5_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_C 0x0041bcd0 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_C__PRIV_LEVEL_MASK 0x0041bcc4 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_C_WT_6 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_C_WT_6_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_C_WT_7 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_C_WT_7_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_C_WT_8 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_C_WT_8_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_D 0x0041bcd4 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_D__PRIV_LEVEL_MASK 0x0041bcc4 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_D_WT_9 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_D_WT_9_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_D_WT_10 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_D_WT_10_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_D_WT_11 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_D_WT_11_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_E 0x0041bcd8 /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_E__PRIV_LEVEL_MASK 0x0041bcc4 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_E_WT_12 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_E_WT_12_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_E_WT_13 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_E_WT_13_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_E_WT_14 29:20 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_E_WT_14_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_F 0x0041bcdc /* RW-4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_F__PRIV_LEVEL_MASK 0x0041bcc4 /* */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_F_WT_15 9:0 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_F_WT_15_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_F_WT_16 19:10 /* RWBVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_BLK_ACT_F_WT_16_INIT 0x000 /* RWB-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP 0x0041bce0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_PART2_SEL 5:5 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_PART2_SEL_DECOMP 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_PART2_SEL_COMP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_SPARE 7:6 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_PM_SEL_SPARE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL 12:8 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP0 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP1 0x01 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP2 0x02 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP3 0x03 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP4 0x04 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP5 0x05 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP6 0x06 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP7 0x07 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP8 0x08 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP9 0x09 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP10 0x0a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP11 0x0b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP12 0x0c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP13 0x0d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP14 0x0e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP15 0x0f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP16 0x10 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP17 0x11 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP18 0x12 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP19 0x13 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP20 0x14 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP21 0x15 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP22 0x16 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP23 0x17 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP24 0x18 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP25 0x19 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP26 0x1a /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP27 0x1b /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP28 0x1c /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP29 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP30 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_GRP31 0x1f /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_PART2_SEL 13:13 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_PART2_SEL_DECOMP 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_PART2_SEL_COMP 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_SPARE 15:14 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_TRIGGER_SEL_SPARE_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL 18:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_CRD 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_CRD_CACHE_CTRL 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_PIPE 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_PIPE_BLEND 0x3 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_CWR 0x4 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_SUBUNIT_SEL_COMP_DECOMP 0x5 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_SPARE 31:19 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_GROUP_SPARE_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_TRIGGER 0x0041bce4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_TRIGGER_MASK 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_TRIGGER_MASK_NONE 0xffff /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_TRIGGER_VALUE 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_DEBUGPORT_TRIGGER_VALUE_ZERO 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_SETTINGS 0x0041bce8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_SETTINGS_BLENDER_LANA_OPT 5:4 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_SETTINGS_BLENDER_LANA_OPT_DISABLED 0x0 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_SETTINGS_BLENDER_LANA_OPT_ONE_ONLY 0x1 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_SETTINGS_BLENDER_LANA_OPT_TWO_ONLY 0x2 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_SETTINGS_BLENDER_LANA_OPT_ENABLED 0x3 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_INDEX 0x0041bcb4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_INDEX_ADDRESS 4:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_INDEX_ADDRESS_RESERVED 0x00 /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_INDEX_ADDRESS_MIN 0x01 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_INDEX_ADDRESS_MAX 0x1e /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_INDEX_ADDRESS_NUM_LEGAL_INDICES_MINUS_ONE 0x1d /* RW--V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_0 0x0041bcec /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_0_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_0_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_1 0x0041bcf0 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_1_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_1_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_2 0x0041bcf4 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_2_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_2_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_3 0x0041bcf8 /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_3_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_COLOR_CLEAR_VALUE_3_V_ZERO 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_VALID_FLAGS 0x0041bcfc /* RWE4R */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_VALID_FLAGS_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_GPCS_ROPS_CROP_ZBC_VALID_FLAGS_V_ALL_INVALID 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0 0x00580000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC0_ETPC0 0x00584000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00584200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00584204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x00584208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x0058420c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x00584210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x00584214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x00584218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x0058421c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x00584220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x00584224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x00584228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x0058422c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x00584230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x00584234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x00584238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x0058423c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00584240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00584244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL 0x00584248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00584300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00584304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00584308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0058430c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1 0x00584310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER4 0x00584314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER5 0x00584318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER6 0x0058431c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER7 0x00584320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER0_S0 0x00584324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER1_S0 0x00584328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER2_S0 0x0058432c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER3_S0 0x00584330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER0_S1 0x00584334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER1_S1 0x00584338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER2_S1 0x0058433c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER3_S1 0x00584340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER0_S2 0x00584344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER1_S2 0x00584348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER2_S2 0x0058434c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER3_S2 0x00584350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER0_S3 0x00584354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER1_S3 0x00584358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER2_S3 0x0058435c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER3_S3 0x00584360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00584364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00584368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058436c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00584370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00584374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00584378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0058437c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00584380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00584384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00584388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058438c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00584390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00584394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00584398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058439c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005843a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005843a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005843a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005843ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005843b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005843b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005843b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005843bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005843c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005843c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00584600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00584604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00584608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0058460c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1 0x00584610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER4 0x00584614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER5 0x00584618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER6 0x0058461c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER7 0x00584620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER0_S0 0x00584624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER1_S0 0x00584628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER2_S0 0x0058462c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER3_S0 0x00584630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER0_S1 0x00584634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER1_S1 0x00584638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER2_S1 0x0058463c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER3_S1 0x00584640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER0_S2 0x00584644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER1_S2 0x00584648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER2_S2 0x0058464c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER3_S2 0x00584650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER0_S3 0x00584654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER1_S3 0x00584658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER2_S3 0x0058465c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER3_S3 0x00584660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00584664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00584668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058466c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00584670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00584674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00584678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0058467c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00584680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00584684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00584688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058468c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00584690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00584694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00584698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058469c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005846a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005846a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005846a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005846ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005846b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005846b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005846b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005846bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005846c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005846c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00584700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00584704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00584708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0058470c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1 0x00584710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER4 0x00584714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER5 0x00584718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER6 0x0058471c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER7 0x00584720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER0_S0 0x00584724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER1_S0 0x00584728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER2_S0 0x0058472c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER3_S0 0x00584730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER0_S1 0x00584734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER1_S1 0x00584738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER2_S1 0x0058473c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER3_S1 0x00584740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER0_S2 0x00584744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER1_S2 0x00584748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER2_S2 0x0058474c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER3_S2 0x00584750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER0_S3 0x00584754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER1_S3 0x00584758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER2_S3 0x0058475c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER3_S3 0x00584760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00584764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00584768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058476c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00584770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00584774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00584778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0058477c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00584780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00584784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00584788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058478c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00584790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00584794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00584798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058479c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005847a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005847a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005847a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005847ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005847b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005847b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005847b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005847bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005847c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005847c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1 0x00584800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00584a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00584a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0 0x00584a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5 0x00584a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1 0x00584a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2 0x00584a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3 0x00584a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4 0x00584a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL 0x00584a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL 0x00584a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL 0x00584a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL 0x00584a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL 0x00584a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL 0x00584a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL 0x00584a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL 0x00584a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00584a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00584a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL 0x00584a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00584b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00584b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00584b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00584b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1 0x00584b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER4 0x00584b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER5 0x00584b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER6 0x00584b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER7 0x00584b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER0_S0 0x00584b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER1_S0 0x00584b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER2_S0 0x00584b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER3_S0 0x00584b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER0_S1 0x00584b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER1_S1 0x00584b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER2_S1 0x00584b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER3_S1 0x00584b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER0_S2 0x00584b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER1_S2 0x00584b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER2_S2 0x00584b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER3_S2 0x00584b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER0_S3 0x00584b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER1_S3 0x00584b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER2_S3 0x00584b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER3_S3 0x00584b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00584b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00584b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00584b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00584b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00584b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00584b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00584b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00584b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00584b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00584b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00584b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00584b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00584b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00584b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00584b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00584ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00584ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00584ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00584bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00584bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00584bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00584bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00584bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00584bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00584bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00584e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00584e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00584e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00584e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1 0x00584e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER4 0x00584e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER5 0x00584e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER6 0x00584e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER7 0x00584e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER0_S0 0x00584e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER1_S0 0x00584e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER2_S0 0x00584e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER3_S0 0x00584e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER0_S1 0x00584e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER1_S1 0x00584e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER2_S1 0x00584e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER3_S1 0x00584e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER0_S2 0x00584e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER1_S2 0x00584e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER2_S2 0x00584e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER3_S2 0x00584e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER0_S3 0x00584e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER1_S3 0x00584e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER2_S3 0x00584e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER3_S3 0x00584e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00584e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00584e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00584e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00584e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00584e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00584e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00584e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00584e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00584e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00584e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00584e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00584e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00584e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00584e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00584e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00584ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00584ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00584ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00584eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00584eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00584eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00584eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00584ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00584ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00584ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00584f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00584f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00584f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00584f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1 0x00584f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER4 0x00584f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER5 0x00584f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER6 0x00584f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER7 0x00584f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER0_S0 0x00584f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER1_S0 0x00584f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER2_S0 0x00584f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER3_S0 0x00584f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER0_S1 0x00584f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER1_S1 0x00584f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER2_S1 0x00584f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER3_S1 0x00584f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER0_S2 0x00584f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER1_S2 0x00584f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER2_S2 0x00584f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER3_S2 0x00584f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER0_S3 0x00584f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER1_S3 0x00584f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER2_S3 0x00584f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER3_S3 0x00584f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00584f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00584f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00584f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00584f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00584f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00584f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00584f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00584f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00584f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00584f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00584f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00584f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00584f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00584f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00584f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00584fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00584fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00584fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00584fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00584fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00584fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00584fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00584fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00584fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00584fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2 0x00585000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00585200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00585204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0 0x00585208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5 0x0058520c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1 0x00585210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2 0x00585214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3 0x00585218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4 0x0058521c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL 0x00585220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL 0x00585224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL 0x00585228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL 0x0058522c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL 0x00585230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL 0x00585234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL 0x00585238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL 0x0058523c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00585240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00585244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL 0x00585248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00585300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00585304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00585308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0058530c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1 0x00585310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER4 0x00585314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER5 0x00585318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER6 0x0058531c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER7 0x00585320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER0_S0 0x00585324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER1_S0 0x00585328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER2_S0 0x0058532c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER3_S0 0x00585330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER0_S1 0x00585334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER1_S1 0x00585338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER2_S1 0x0058533c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER3_S1 0x00585340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER0_S2 0x00585344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER1_S2 0x00585348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER2_S2 0x0058534c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER3_S2 0x00585350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER0_S3 0x00585354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER1_S3 0x00585358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER2_S3 0x0058535c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER3_S3 0x00585360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00585364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00585368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058536c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00585370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00585374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00585378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0058537c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00585380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00585384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00585388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058538c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00585390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00585394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00585398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058539c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005853a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005853a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005853a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005853ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005853b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005853b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005853b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005853bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005853c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005853c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00585600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00585604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00585608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0058560c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1 0x00585610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER4 0x00585614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER5 0x00585618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER6 0x0058561c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER7 0x00585620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER0_S0 0x00585624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER1_S0 0x00585628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER2_S0 0x0058562c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER3_S0 0x00585630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER0_S1 0x00585634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER1_S1 0x00585638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER2_S1 0x0058563c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER3_S1 0x00585640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER0_S2 0x00585644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER1_S2 0x00585648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER2_S2 0x0058564c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER3_S2 0x00585650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER0_S3 0x00585654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER1_S3 0x00585658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER2_S3 0x0058565c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER3_S3 0x00585660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00585664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00585668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058566c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00585670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00585674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00585678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0058567c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00585680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00585684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00585688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058568c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00585690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00585694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00585698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058569c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005856a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005856a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005856a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005856ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005856b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005856b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005856b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005856bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005856c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005856c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00585700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00585704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00585708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0058570c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1 0x00585710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER4 0x00585714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER5 0x00585718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER6 0x0058571c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER7 0x00585720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER0_S0 0x00585724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER1_S0 0x00585728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER2_S0 0x0058572c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER3_S0 0x00585730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER0_S1 0x00585734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER1_S1 0x00585738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER2_S1 0x0058573c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER3_S1 0x00585740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER0_S2 0x00585744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER1_S2 0x00585748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER2_S2 0x0058574c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER3_S2 0x00585750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER0_S3 0x00585754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER1_S3 0x00585758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER2_S3 0x0058575c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER3_S3 0x00585760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00585764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00585768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058576c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00585770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00585774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00585778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0058577c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00585780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00585784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00585788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058578c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00585790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00585794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00585798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058579c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005857a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005857a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005857a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005857ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005857b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005857b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005857b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005857bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005857c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005857c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3 0x00585800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00585a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00585a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0 0x00585a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5 0x00585a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1 0x00585a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2 0x00585a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3 0x00585a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4 0x00585a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL 0x00585a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL 0x00585a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL 0x00585a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL 0x00585a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL 0x00585a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL 0x00585a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL 0x00585a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL 0x00585a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00585a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00585a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL 0x00585a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00585b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00585b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00585b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00585b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1 0x00585b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER4 0x00585b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER5 0x00585b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER6 0x00585b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER7 0x00585b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER0_S0 0x00585b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER1_S0 0x00585b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER2_S0 0x00585b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER3_S0 0x00585b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER0_S1 0x00585b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER1_S1 0x00585b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER2_S1 0x00585b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER3_S1 0x00585b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER0_S2 0x00585b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER1_S2 0x00585b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER2_S2 0x00585b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER3_S2 0x00585b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER0_S3 0x00585b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER1_S3 0x00585b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER2_S3 0x00585b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER3_S3 0x00585b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00585b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00585b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00585b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00585b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00585b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00585b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00585b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00585b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00585b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00585b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00585b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00585b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00585b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00585b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00585b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00585ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00585ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00585ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00585bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00585bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00585bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00585bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00585bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00585bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00585bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00585e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00585e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00585e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00585e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1 0x00585e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER4 0x00585e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER5 0x00585e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER6 0x00585e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER7 0x00585e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER0_S0 0x00585e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER1_S0 0x00585e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER2_S0 0x00585e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER3_S0 0x00585e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER0_S1 0x00585e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER1_S1 0x00585e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER2_S1 0x00585e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER3_S1 0x00585e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER0_S2 0x00585e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER1_S2 0x00585e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER2_S2 0x00585e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER3_S2 0x00585e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER0_S3 0x00585e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER1_S3 0x00585e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER2_S3 0x00585e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER3_S3 0x00585e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00585e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00585e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00585e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00585e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00585e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00585e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00585e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00585e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00585e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00585e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00585e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00585e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00585e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00585e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00585e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00585ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00585ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00585ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00585eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00585eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00585eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00585eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00585ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00585ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00585ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00585f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00585f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00585f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00585f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1 0x00585f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER4 0x00585f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER5 0x00585f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER6 0x00585f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER7 0x00585f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER0_S0 0x00585f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER1_S0 0x00585f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER2_S0 0x00585f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER3_S0 0x00585f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER0_S1 0x00585f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER1_S1 0x00585f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER2_S1 0x00585f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER3_S1 0x00585f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER0_S2 0x00585f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER1_S2 0x00585f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER2_S2 0x00585f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER3_S2 0x00585f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER0_S3 0x00585f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER1_S3 0x00585f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER2_S3 0x00585f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER3_S3 0x00585f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00585f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00585f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00585f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00585f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00585f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00585f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00585f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00585f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00585f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00585f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00585f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00585f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00585f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00585f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00585f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00585fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00585fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00585fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00585fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00585fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00585fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00585fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00585fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00585fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00585fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4 0x00586000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00586200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00586204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0 0x00586208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5 0x0058620c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1 0x00586210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2 0x00586214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3 0x00586218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4 0x0058621c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL 0x00586220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL 0x00586224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL 0x00586228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL 0x0058622c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL 0x00586230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL 0x00586234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL 0x00586238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL 0x0058623c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00586240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00586244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL 0x00586248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00586300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00586304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00586308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0058630c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1 0x00586310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER4 0x00586314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER5 0x00586318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER6 0x0058631c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER7 0x00586320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER0_S0 0x00586324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER1_S0 0x00586328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER2_S0 0x0058632c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER3_S0 0x00586330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER0_S1 0x00586334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER1_S1 0x00586338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER2_S1 0x0058633c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER3_S1 0x00586340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER0_S2 0x00586344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER1_S2 0x00586348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER2_S2 0x0058634c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER3_S2 0x00586350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER0_S3 0x00586354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER1_S3 0x00586358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER2_S3 0x0058635c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER3_S3 0x00586360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00586364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00586368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058636c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00586370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00586374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00586378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0058637c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00586380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00586384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00586388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058638c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00586390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00586394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00586398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058639c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005863a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005863a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005863a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005863ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005863b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005863b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005863b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005863bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005863c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005863c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00586600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00586604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00586608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0058660c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1 0x00586610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER4 0x00586614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER5 0x00586618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER6 0x0058661c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER7 0x00586620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER0_S0 0x00586624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER1_S0 0x00586628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER2_S0 0x0058662c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER3_S0 0x00586630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER0_S1 0x00586634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER1_S1 0x00586638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER2_S1 0x0058663c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER3_S1 0x00586640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER0_S2 0x00586644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER1_S2 0x00586648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER2_S2 0x0058664c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER3_S2 0x00586650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER0_S3 0x00586654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER1_S3 0x00586658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER2_S3 0x0058665c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER3_S3 0x00586660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00586664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00586668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058666c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00586670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00586674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00586678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0058667c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00586680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00586684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00586688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058668c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00586690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00586694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00586698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058669c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005866a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005866a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005866a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005866ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005866b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005866b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005866b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005866bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005866c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005866c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00586700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00586704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00586708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0058670c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1 0x00586710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER4 0x00586714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER5 0x00586718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER6 0x0058671c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER7 0x00586720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER0_S0 0x00586724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER1_S0 0x00586728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER2_S0 0x0058672c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER3_S0 0x00586730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER0_S1 0x00586734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER1_S1 0x00586738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER2_S1 0x0058673c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER3_S1 0x00586740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER0_S2 0x00586744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER1_S2 0x00586748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER2_S2 0x0058674c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER3_S2 0x00586750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER0_S3 0x00586754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER1_S3 0x00586758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER2_S3 0x0058675c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER3_S3 0x00586760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00586764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00586768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058676c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00586770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00586774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00586778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0058677c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00586780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00586784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00586788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058678c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00586790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00586794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00586798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058679c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005867a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005867a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005867a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005867ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005867b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005867b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005867b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005867bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005867c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005867c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5 0x00586800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00586a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00586a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0 0x00586a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5 0x00586a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1 0x00586a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2 0x00586a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3 0x00586a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4 0x00586a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL 0x00586a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL 0x00586a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL 0x00586a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL 0x00586a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL 0x00586a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL 0x00586a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL 0x00586a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL 0x00586a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00586a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00586a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL 0x00586a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00586b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00586b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00586b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00586b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1 0x00586b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER4 0x00586b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER5 0x00586b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER6 0x00586b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER7 0x00586b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER0_S0 0x00586b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER1_S0 0x00586b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER2_S0 0x00586b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER3_S0 0x00586b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER0_S1 0x00586b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER1_S1 0x00586b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER2_S1 0x00586b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER3_S1 0x00586b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER0_S2 0x00586b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER1_S2 0x00586b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER2_S2 0x00586b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER3_S2 0x00586b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER0_S3 0x00586b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER1_S3 0x00586b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER2_S3 0x00586b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER3_S3 0x00586b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00586b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00586b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00586b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00586b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00586b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00586b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00586b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00586b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00586b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00586b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00586b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00586b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00586b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00586b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00586b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00586ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00586ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00586ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00586bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00586bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00586bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00586bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00586bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00586bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00586bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00586e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00586e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00586e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00586e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1 0x00586e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER4 0x00586e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER5 0x00586e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER6 0x00586e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER7 0x00586e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER0_S0 0x00586e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER1_S0 0x00586e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER2_S0 0x00586e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER3_S0 0x00586e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER0_S1 0x00586e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER1_S1 0x00586e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER2_S1 0x00586e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER3_S1 0x00586e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER0_S2 0x00586e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER1_S2 0x00586e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER2_S2 0x00586e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER3_S2 0x00586e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER0_S3 0x00586e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER1_S3 0x00586e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER2_S3 0x00586e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER3_S3 0x00586e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00586e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00586e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00586e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00586e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00586e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00586e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00586e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00586e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00586e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00586e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00586e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00586e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00586e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00586e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00586e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00586ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00586ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00586ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00586eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00586eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00586eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00586eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00586ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00586ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00586ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00586f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00586f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00586f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00586f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1 0x00586f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER4 0x00586f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER5 0x00586f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER6 0x00586f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER7 0x00586f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER0_S0 0x00586f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER1_S0 0x00586f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER2_S0 0x00586f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER3_S0 0x00586f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER0_S1 0x00586f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER1_S1 0x00586f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER2_S1 0x00586f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER3_S1 0x00586f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER0_S2 0x00586f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER1_S2 0x00586f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER2_S2 0x00586f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER3_S2 0x00586f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER0_S3 0x00586f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER1_S3 0x00586f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER2_S3 0x00586f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER3_S3 0x00586f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00586f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00586f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00586f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00586f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00586f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00586f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00586f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00586f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00586f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00586f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00586f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00586f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00586f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00586f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00586f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00586fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00586fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00586fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00586fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00586fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00586fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00586fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00586fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00586fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00586fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS 0x00581800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00581a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00581a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0 0x00581a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5 0x00581a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1 0x00581a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2 0x00581a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3 0x00581a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4 0x00581a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL 0x00581a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL 0x00581a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL 0x00581a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL 0x00581a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL 0x00581a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL 0x00581a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL 0x00581a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL 0x00581a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00581a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00581a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL 0x00581a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00581b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00581b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00581b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00581b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1 0x00581b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER4 0x00581b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER5 0x00581b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER6 0x00581b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER7 0x00581b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER0_S0 0x00581b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER1_S0 0x00581b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER2_S0 0x00581b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER3_S0 0x00581b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER0_S1 0x00581b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER1_S1 0x00581b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER2_S1 0x00581b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER3_S1 0x00581b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER0_S2 0x00581b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER1_S2 0x00581b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER2_S2 0x00581b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER3_S2 0x00581b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER0_S3 0x00581b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER1_S3 0x00581b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER2_S3 0x00581b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER3_S3 0x00581b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00581b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00581b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00581b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00581b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00581b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00581b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00581b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00581b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00581b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00581b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00581b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00581b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00581b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00581b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00581b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00581ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00581ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00581ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00581bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00581bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00581bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00581bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00581bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00581bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00581bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00581e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00581e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00581e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00581e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1 0x00581e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER4 0x00581e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER5 0x00581e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER6 0x00581e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER7 0x00581e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER0_S0 0x00581e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER1_S0 0x00581e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER2_S0 0x00581e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER3_S0 0x00581e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER0_S1 0x00581e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER1_S1 0x00581e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER2_S1 0x00581e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER3_S1 0x00581e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER0_S2 0x00581e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER1_S2 0x00581e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER2_S2 0x00581e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER3_S2 0x00581e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER0_S3 0x00581e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER1_S3 0x00581e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER2_S3 0x00581e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER3_S3 0x00581e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00581e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00581e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00581e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00581e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00581e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00581e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00581e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00581e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00581e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00581e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00581e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00581e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00581e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00581e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00581e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00581ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00581ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00581ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00581eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00581eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00581eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00581eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00581ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00581ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00581ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00581f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00581f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00581f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00581f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1 0x00581f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER4 0x00581f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER5 0x00581f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER6 0x00581f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER7 0x00581f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER0_S0 0x00581f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER1_S0 0x00581f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER2_S0 0x00581f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER3_S0 0x00581f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER0_S1 0x00581f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER1_S1 0x00581f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER2_S1 0x00581f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER3_S1 0x00581f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER0_S2 0x00581f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER1_S2 0x00581f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER2_S2 0x00581f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER3_S2 0x00581f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER0_S3 0x00581f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER1_S3 0x00581f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER2_S3 0x00581f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER3_S3 0x00581f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00581f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00581f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00581f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00581f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00581f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00581f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00581f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00581f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00581f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00581f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00581f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00581f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00581f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00581f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00581f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00581fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00581fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00581fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00581fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00581fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00581fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00581fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00581fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00581fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00581fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC0_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1 0x00588000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC1_ETPC0 0x0058c000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x0058c200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x0058c204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x0058c208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x0058c20c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x0058c210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x0058c214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x0058c218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x0058c21c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x0058c220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x0058c224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x0058c228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x0058c22c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x0058c230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x0058c234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x0058c238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x0058c23c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x0058c240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x0058c244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL 0x0058c248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0 0x0058c300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1 0x0058c304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2 0x0058c308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0058c30c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1 0x0058c310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER4 0x0058c314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER5 0x0058c318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER6 0x0058c31c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER7 0x0058c320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER0_S0 0x0058c324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER1_S0 0x0058c328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER2_S0 0x0058c32c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER3_S0 0x0058c330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER0_S1 0x0058c334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER1_S1 0x0058c338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER2_S1 0x0058c33c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER3_S1 0x0058c340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER0_S2 0x0058c344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER1_S2 0x0058c348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER2_S2 0x0058c34c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER3_S2 0x0058c350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER0_S3 0x0058c354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER1_S3 0x0058c358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER2_S3 0x0058c35c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER3_S3 0x0058c360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058c364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058c368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058c36c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058c370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058c374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x0058c378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0058c37c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x0058c380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x0058c384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058c388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058c38c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058c390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058c394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058c398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058c39c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058c3a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058c3a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058c3a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058c3ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058c3b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058c3b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058c3b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058c3bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058c3c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058c3c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0 0x0058c600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1 0x0058c604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2 0x0058c608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0058c60c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1 0x0058c610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER4 0x0058c614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER5 0x0058c618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER6 0x0058c61c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER7 0x0058c620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER0_S0 0x0058c624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER1_S0 0x0058c628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER2_S0 0x0058c62c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER3_S0 0x0058c630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER0_S1 0x0058c634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER1_S1 0x0058c638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER2_S1 0x0058c63c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER3_S1 0x0058c640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER0_S2 0x0058c644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER1_S2 0x0058c648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER2_S2 0x0058c64c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER3_S2 0x0058c650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER0_S3 0x0058c654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER1_S3 0x0058c658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER2_S3 0x0058c65c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER3_S3 0x0058c660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058c664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058c668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058c66c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058c670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058c674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x0058c678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0058c67c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x0058c680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x0058c684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058c688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058c68c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058c690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058c694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058c698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058c69c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058c6a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058c6a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058c6a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058c6ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058c6b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058c6b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058c6b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058c6bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058c6c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058c6c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0 0x0058c700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1 0x0058c704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2 0x0058c708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0058c70c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1 0x0058c710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER4 0x0058c714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER5 0x0058c718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER6 0x0058c71c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER7 0x0058c720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER0_S0 0x0058c724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER1_S0 0x0058c728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER2_S0 0x0058c72c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER3_S0 0x0058c730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER0_S1 0x0058c734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER1_S1 0x0058c738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER2_S1 0x0058c73c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER3_S1 0x0058c740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER0_S2 0x0058c744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER1_S2 0x0058c748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER2_S2 0x0058c74c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER3_S2 0x0058c750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER0_S3 0x0058c754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER1_S3 0x0058c758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER2_S3 0x0058c75c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER3_S3 0x0058c760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058c764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058c768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058c76c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058c770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058c774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x0058c778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0058c77c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x0058c780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x0058c784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058c788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058c78c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058c790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058c794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058c798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058c79c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058c7a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058c7a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058c7a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058c7ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058c7b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058c7b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058c7b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058c7bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058c7c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058c7c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1 0x0058c800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x0058ca00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x0058ca04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0 0x0058ca08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5 0x0058ca0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1 0x0058ca10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2 0x0058ca14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3 0x0058ca18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4 0x0058ca1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL 0x0058ca20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL 0x0058ca24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL 0x0058ca28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL 0x0058ca2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL 0x0058ca30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL 0x0058ca34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL 0x0058ca38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL 0x0058ca3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x0058ca40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x0058ca44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL 0x0058ca48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0 0x0058cb00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1 0x0058cb04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2 0x0058cb08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0058cb0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1 0x0058cb10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER4 0x0058cb14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER5 0x0058cb18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER6 0x0058cb1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER7 0x0058cb20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER0_S0 0x0058cb24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER1_S0 0x0058cb28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER2_S0 0x0058cb2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER3_S0 0x0058cb30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER0_S1 0x0058cb34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER1_S1 0x0058cb38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER2_S1 0x0058cb3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER3_S1 0x0058cb40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER0_S2 0x0058cb44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER1_S2 0x0058cb48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER2_S2 0x0058cb4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER3_S2 0x0058cb50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER0_S3 0x0058cb54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER1_S3 0x0058cb58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER2_S3 0x0058cb5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER3_S3 0x0058cb60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058cb64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058cb68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058cb6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058cb70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058cb74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x0058cb78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0058cb7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x0058cb80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x0058cb84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058cb88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058cb8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058cb90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058cb94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058cb98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058cb9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058cba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058cba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058cba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058cbac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058cbb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058cbb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058cbb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058cbbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058cbc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058cbc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0 0x0058ce00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1 0x0058ce04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2 0x0058ce08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0058ce0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1 0x0058ce10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER4 0x0058ce14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER5 0x0058ce18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER6 0x0058ce1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER7 0x0058ce20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER0_S0 0x0058ce24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER1_S0 0x0058ce28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER2_S0 0x0058ce2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER3_S0 0x0058ce30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER0_S1 0x0058ce34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER1_S1 0x0058ce38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER2_S1 0x0058ce3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER3_S1 0x0058ce40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER0_S2 0x0058ce44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER1_S2 0x0058ce48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER2_S2 0x0058ce4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER3_S2 0x0058ce50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER0_S3 0x0058ce54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER1_S3 0x0058ce58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER2_S3 0x0058ce5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER3_S3 0x0058ce60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058ce64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058ce68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058ce6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058ce70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058ce74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x0058ce78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0058ce7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x0058ce80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x0058ce84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058ce88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058ce8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058ce90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058ce94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058ce98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058ce9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058cea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058cea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058cea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058ceac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058ceb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058ceb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058ceb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058cebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058cec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058cec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0 0x0058cf00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1 0x0058cf04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2 0x0058cf08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0058cf0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1 0x0058cf10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER4 0x0058cf14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER5 0x0058cf18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER6 0x0058cf1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER7 0x0058cf20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER0_S0 0x0058cf24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER1_S0 0x0058cf28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER2_S0 0x0058cf2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER3_S0 0x0058cf30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER0_S1 0x0058cf34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER1_S1 0x0058cf38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER2_S1 0x0058cf3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER3_S1 0x0058cf40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER0_S2 0x0058cf44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER1_S2 0x0058cf48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER2_S2 0x0058cf4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER3_S2 0x0058cf50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER0_S3 0x0058cf54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER1_S3 0x0058cf58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER2_S3 0x0058cf5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER3_S3 0x0058cf60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058cf64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058cf68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058cf6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058cf70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058cf74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x0058cf78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0058cf7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x0058cf80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x0058cf84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058cf88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058cf8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058cf90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058cf94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058cf98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058cf9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058cfa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058cfa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058cfa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058cfac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058cfb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058cfb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058cfb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058cfbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058cfc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058cfc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2 0x0058d000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x0058d200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x0058d204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0 0x0058d208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5 0x0058d20c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1 0x0058d210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2 0x0058d214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3 0x0058d218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4 0x0058d21c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL 0x0058d220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL 0x0058d224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL 0x0058d228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL 0x0058d22c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL 0x0058d230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL 0x0058d234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL 0x0058d238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL 0x0058d23c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x0058d240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x0058d244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL 0x0058d248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0 0x0058d300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1 0x0058d304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2 0x0058d308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0058d30c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1 0x0058d310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER4 0x0058d314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER5 0x0058d318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER6 0x0058d31c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER7 0x0058d320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER0_S0 0x0058d324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER1_S0 0x0058d328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER2_S0 0x0058d32c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER3_S0 0x0058d330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER0_S1 0x0058d334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER1_S1 0x0058d338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER2_S1 0x0058d33c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER3_S1 0x0058d340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER0_S2 0x0058d344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER1_S2 0x0058d348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER2_S2 0x0058d34c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER3_S2 0x0058d350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER0_S3 0x0058d354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER1_S3 0x0058d358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER2_S3 0x0058d35c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER3_S3 0x0058d360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058d364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058d368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058d36c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058d370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058d374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x0058d378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0058d37c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x0058d380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x0058d384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058d388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058d38c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058d390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058d394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058d398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058d39c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058d3a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058d3a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058d3a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058d3ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058d3b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058d3b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058d3b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058d3bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058d3c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058d3c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0 0x0058d600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1 0x0058d604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2 0x0058d608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0058d60c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1 0x0058d610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER4 0x0058d614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER5 0x0058d618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER6 0x0058d61c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER7 0x0058d620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER0_S0 0x0058d624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER1_S0 0x0058d628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER2_S0 0x0058d62c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER3_S0 0x0058d630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER0_S1 0x0058d634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER1_S1 0x0058d638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER2_S1 0x0058d63c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER3_S1 0x0058d640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER0_S2 0x0058d644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER1_S2 0x0058d648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER2_S2 0x0058d64c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER3_S2 0x0058d650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER0_S3 0x0058d654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER1_S3 0x0058d658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER2_S3 0x0058d65c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER3_S3 0x0058d660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058d664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058d668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058d66c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058d670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058d674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x0058d678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0058d67c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x0058d680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x0058d684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058d688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058d68c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058d690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058d694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058d698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058d69c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058d6a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058d6a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058d6a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058d6ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058d6b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058d6b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058d6b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058d6bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058d6c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058d6c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0 0x0058d700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1 0x0058d704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2 0x0058d708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0058d70c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1 0x0058d710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER4 0x0058d714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER5 0x0058d718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER6 0x0058d71c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER7 0x0058d720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER0_S0 0x0058d724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER1_S0 0x0058d728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER2_S0 0x0058d72c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER3_S0 0x0058d730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER0_S1 0x0058d734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER1_S1 0x0058d738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER2_S1 0x0058d73c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER3_S1 0x0058d740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER0_S2 0x0058d744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER1_S2 0x0058d748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER2_S2 0x0058d74c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER3_S2 0x0058d750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER0_S3 0x0058d754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER1_S3 0x0058d758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER2_S3 0x0058d75c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER3_S3 0x0058d760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058d764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058d768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058d76c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058d770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058d774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x0058d778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0058d77c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x0058d780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x0058d784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058d788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058d78c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058d790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058d794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058d798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058d79c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058d7a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058d7a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058d7a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058d7ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058d7b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058d7b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058d7b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058d7bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058d7c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058d7c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3 0x0058d800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x0058da00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x0058da04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0 0x0058da08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5 0x0058da0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1 0x0058da10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2 0x0058da14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3 0x0058da18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4 0x0058da1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL 0x0058da20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL 0x0058da24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL 0x0058da28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL 0x0058da2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL 0x0058da30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL 0x0058da34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL 0x0058da38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL 0x0058da3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x0058da40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x0058da44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL 0x0058da48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0 0x0058db00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1 0x0058db04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2 0x0058db08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0058db0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1 0x0058db10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER4 0x0058db14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER5 0x0058db18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER6 0x0058db1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER7 0x0058db20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER0_S0 0x0058db24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER1_S0 0x0058db28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER2_S0 0x0058db2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER3_S0 0x0058db30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER0_S1 0x0058db34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER1_S1 0x0058db38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER2_S1 0x0058db3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER3_S1 0x0058db40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER0_S2 0x0058db44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER1_S2 0x0058db48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER2_S2 0x0058db4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER3_S2 0x0058db50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER0_S3 0x0058db54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER1_S3 0x0058db58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER2_S3 0x0058db5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER3_S3 0x0058db60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058db64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058db68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058db6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058db70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058db74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x0058db78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0058db7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x0058db80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x0058db84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058db88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058db8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058db90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058db94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058db98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058db9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058dba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058dba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058dba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058dbac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058dbb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058dbb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058dbb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058dbbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058dbc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058dbc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0 0x0058de00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1 0x0058de04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2 0x0058de08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0058de0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1 0x0058de10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER4 0x0058de14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER5 0x0058de18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER6 0x0058de1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER7 0x0058de20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER0_S0 0x0058de24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER1_S0 0x0058de28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER2_S0 0x0058de2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER3_S0 0x0058de30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER0_S1 0x0058de34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER1_S1 0x0058de38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER2_S1 0x0058de3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER3_S1 0x0058de40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER0_S2 0x0058de44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER1_S2 0x0058de48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER2_S2 0x0058de4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER3_S2 0x0058de50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER0_S3 0x0058de54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER1_S3 0x0058de58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER2_S3 0x0058de5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER3_S3 0x0058de60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058de64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058de68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058de6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058de70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058de74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x0058de78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0058de7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x0058de80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x0058de84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058de88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058de8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058de90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058de94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058de98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058de9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058dea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058dea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058dea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058deac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058deb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058deb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058deb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058debc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058dec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058dec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0 0x0058df00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1 0x0058df04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2 0x0058df08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0058df0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1 0x0058df10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER4 0x0058df14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER5 0x0058df18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER6 0x0058df1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER7 0x0058df20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER0_S0 0x0058df24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER1_S0 0x0058df28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER2_S0 0x0058df2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER3_S0 0x0058df30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER0_S1 0x0058df34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER1_S1 0x0058df38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER2_S1 0x0058df3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER3_S1 0x0058df40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER0_S2 0x0058df44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER1_S2 0x0058df48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER2_S2 0x0058df4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER3_S2 0x0058df50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER0_S3 0x0058df54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER1_S3 0x0058df58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER2_S3 0x0058df5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER3_S3 0x0058df60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058df64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058df68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058df6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058df70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058df74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x0058df78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0058df7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x0058df80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x0058df84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058df88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058df8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058df90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058df94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058df98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058df9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058dfa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058dfa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058dfa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058dfac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058dfb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058dfb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058dfb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058dfbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058dfc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058dfc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4 0x0058e000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x0058e200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x0058e204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0 0x0058e208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5 0x0058e20c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1 0x0058e210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2 0x0058e214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3 0x0058e218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4 0x0058e21c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL 0x0058e220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL 0x0058e224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL 0x0058e228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL 0x0058e22c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL 0x0058e230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL 0x0058e234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL 0x0058e238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL 0x0058e23c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x0058e240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x0058e244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL 0x0058e248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0 0x0058e300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1 0x0058e304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2 0x0058e308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0058e30c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1 0x0058e310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER4 0x0058e314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER5 0x0058e318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER6 0x0058e31c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER7 0x0058e320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER0_S0 0x0058e324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER1_S0 0x0058e328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER2_S0 0x0058e32c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER3_S0 0x0058e330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER0_S1 0x0058e334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER1_S1 0x0058e338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER2_S1 0x0058e33c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER3_S1 0x0058e340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER0_S2 0x0058e344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER1_S2 0x0058e348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER2_S2 0x0058e34c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER3_S2 0x0058e350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER0_S3 0x0058e354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER1_S3 0x0058e358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER2_S3 0x0058e35c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER3_S3 0x0058e360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058e364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058e368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058e36c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058e370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058e374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x0058e378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0058e37c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x0058e380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x0058e384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058e388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058e38c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058e390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058e394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058e398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058e39c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058e3a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058e3a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058e3a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058e3ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058e3b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058e3b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058e3b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058e3bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058e3c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058e3c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0 0x0058e600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1 0x0058e604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2 0x0058e608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0058e60c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1 0x0058e610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER4 0x0058e614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER5 0x0058e618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER6 0x0058e61c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER7 0x0058e620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER0_S0 0x0058e624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER1_S0 0x0058e628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER2_S0 0x0058e62c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER3_S0 0x0058e630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER0_S1 0x0058e634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER1_S1 0x0058e638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER2_S1 0x0058e63c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER3_S1 0x0058e640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER0_S2 0x0058e644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER1_S2 0x0058e648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER2_S2 0x0058e64c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER3_S2 0x0058e650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER0_S3 0x0058e654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER1_S3 0x0058e658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER2_S3 0x0058e65c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER3_S3 0x0058e660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058e664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058e668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058e66c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058e670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058e674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x0058e678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0058e67c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x0058e680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x0058e684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058e688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058e68c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058e690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058e694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058e698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058e69c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058e6a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058e6a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058e6a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058e6ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058e6b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058e6b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058e6b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058e6bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058e6c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058e6c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0 0x0058e700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1 0x0058e704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2 0x0058e708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0058e70c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1 0x0058e710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER4 0x0058e714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER5 0x0058e718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER6 0x0058e71c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER7 0x0058e720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER0_S0 0x0058e724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER1_S0 0x0058e728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER2_S0 0x0058e72c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER3_S0 0x0058e730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER0_S1 0x0058e734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER1_S1 0x0058e738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER2_S1 0x0058e73c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER3_S1 0x0058e740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER0_S2 0x0058e744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER1_S2 0x0058e748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER2_S2 0x0058e74c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER3_S2 0x0058e750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER0_S3 0x0058e754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER1_S3 0x0058e758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER2_S3 0x0058e75c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER3_S3 0x0058e760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058e764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058e768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058e76c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058e770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058e774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x0058e778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0058e77c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x0058e780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x0058e784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058e788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058e78c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058e790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058e794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058e798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058e79c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058e7a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058e7a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058e7a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058e7ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058e7b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058e7b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058e7b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058e7bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058e7c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058e7c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5 0x0058e800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x0058ea00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x0058ea04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0 0x0058ea08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5 0x0058ea0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1 0x0058ea10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2 0x0058ea14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3 0x0058ea18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4 0x0058ea1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL 0x0058ea20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL 0x0058ea24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL 0x0058ea28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL 0x0058ea2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL 0x0058ea30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL 0x0058ea34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL 0x0058ea38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL 0x0058ea3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x0058ea40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x0058ea44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL 0x0058ea48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0 0x0058eb00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1 0x0058eb04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2 0x0058eb08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0058eb0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1 0x0058eb10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER4 0x0058eb14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER5 0x0058eb18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER6 0x0058eb1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER7 0x0058eb20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER0_S0 0x0058eb24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER1_S0 0x0058eb28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER2_S0 0x0058eb2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER3_S0 0x0058eb30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER0_S1 0x0058eb34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER1_S1 0x0058eb38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER2_S1 0x0058eb3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER3_S1 0x0058eb40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER0_S2 0x0058eb44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER1_S2 0x0058eb48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER2_S2 0x0058eb4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER3_S2 0x0058eb50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER0_S3 0x0058eb54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER1_S3 0x0058eb58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER2_S3 0x0058eb5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER3_S3 0x0058eb60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058eb64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058eb68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058eb6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058eb70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058eb74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x0058eb78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0058eb7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x0058eb80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x0058eb84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058eb88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058eb8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058eb90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058eb94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058eb98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058eb9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058eba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058eba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058eba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058ebac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058ebb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058ebb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058ebb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058ebbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058ebc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058ebc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0 0x0058ee00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1 0x0058ee04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2 0x0058ee08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0058ee0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1 0x0058ee10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER4 0x0058ee14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER5 0x0058ee18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER6 0x0058ee1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER7 0x0058ee20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER0_S0 0x0058ee24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER1_S0 0x0058ee28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER2_S0 0x0058ee2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER3_S0 0x0058ee30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER0_S1 0x0058ee34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER1_S1 0x0058ee38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER2_S1 0x0058ee3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER3_S1 0x0058ee40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER0_S2 0x0058ee44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER1_S2 0x0058ee48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER2_S2 0x0058ee4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER3_S2 0x0058ee50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER0_S3 0x0058ee54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER1_S3 0x0058ee58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER2_S3 0x0058ee5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER3_S3 0x0058ee60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058ee64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058ee68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058ee6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058ee70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058ee74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x0058ee78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0058ee7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x0058ee80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x0058ee84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058ee88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058ee8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058ee90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058ee94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058ee98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058ee9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058eea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058eea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058eea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058eeac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058eeb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058eeb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058eeb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058eebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058eec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058eec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0 0x0058ef00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1 0x0058ef04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2 0x0058ef08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0058ef0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1 0x0058ef10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER4 0x0058ef14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER5 0x0058ef18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER6 0x0058ef1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER7 0x0058ef20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER0_S0 0x0058ef24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER1_S0 0x0058ef28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER2_S0 0x0058ef2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER3_S0 0x0058ef30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER0_S1 0x0058ef34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER1_S1 0x0058ef38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER2_S1 0x0058ef3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER3_S1 0x0058ef40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER0_S2 0x0058ef44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER1_S2 0x0058ef48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER2_S2 0x0058ef4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER3_S2 0x0058ef50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER0_S3 0x0058ef54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER1_S3 0x0058ef58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER2_S3 0x0058ef5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER3_S3 0x0058ef60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0058ef64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0058ef68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0058ef6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0058ef70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0058ef74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x0058ef78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0058ef7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x0058ef80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x0058ef84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0058ef88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0058ef8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0058ef90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0058ef94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0058ef98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0058ef9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0058efa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0058efa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0058efa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0058efac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0058efb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0058efb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0058efb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0058efbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0058efc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0058efc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS 0x00589800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00589a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00589a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0 0x00589a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5 0x00589a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1 0x00589a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2 0x00589a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3 0x00589a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4 0x00589a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL 0x00589a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL 0x00589a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL 0x00589a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL 0x00589a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL 0x00589a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL 0x00589a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL 0x00589a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL 0x00589a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00589a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00589a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL 0x00589a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00589b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00589b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00589b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00589b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1 0x00589b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER4 0x00589b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER5 0x00589b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER6 0x00589b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER7 0x00589b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER0_S0 0x00589b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER1_S0 0x00589b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER2_S0 0x00589b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER3_S0 0x00589b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER0_S1 0x00589b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER1_S1 0x00589b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER2_S1 0x00589b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER3_S1 0x00589b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER0_S2 0x00589b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER1_S2 0x00589b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER2_S2 0x00589b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER3_S2 0x00589b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER0_S3 0x00589b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER1_S3 0x00589b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER2_S3 0x00589b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER3_S3 0x00589b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00589b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00589b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00589b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00589b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00589b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00589b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00589b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00589b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00589b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00589b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00589b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00589b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00589b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00589b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00589b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00589ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00589ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00589ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00589bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00589bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00589bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00589bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00589bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00589bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00589bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00589e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00589e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00589e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00589e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1 0x00589e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER4 0x00589e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER5 0x00589e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER6 0x00589e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER7 0x00589e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER0_S0 0x00589e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER1_S0 0x00589e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER2_S0 0x00589e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER3_S0 0x00589e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER0_S1 0x00589e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER1_S1 0x00589e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER2_S1 0x00589e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER3_S1 0x00589e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER0_S2 0x00589e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER1_S2 0x00589e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER2_S2 0x00589e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER3_S2 0x00589e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER0_S3 0x00589e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER1_S3 0x00589e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER2_S3 0x00589e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER3_S3 0x00589e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00589e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00589e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00589e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00589e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00589e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00589e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00589e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00589e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00589e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00589e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00589e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00589e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00589e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00589e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00589e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00589ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00589ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00589ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00589eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00589eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00589eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00589eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00589ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00589ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00589ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00589f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00589f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00589f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00589f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1 0x00589f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER4 0x00589f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER5 0x00589f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER6 0x00589f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER7 0x00589f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER0_S0 0x00589f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER1_S0 0x00589f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER2_S0 0x00589f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER3_S0 0x00589f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER0_S1 0x00589f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER1_S1 0x00589f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER2_S1 0x00589f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER3_S1 0x00589f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER0_S2 0x00589f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER1_S2 0x00589f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER2_S2 0x00589f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER3_S2 0x00589f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER0_S3 0x00589f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER1_S3 0x00589f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER2_S3 0x00589f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER3_S3 0x00589f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00589f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00589f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00589f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00589f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00589f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00589f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00589f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00589f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00589f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00589f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00589f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00589f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00589f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00589f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00589f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00589fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00589fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00589fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00589fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00589fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00589fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00589fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00589fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00589fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00589fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC1_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2 0x00590000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC2_ETPC0 0x00594000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00594200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00594204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x00594208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x0059420c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x00594210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x00594214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x00594218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x0059421c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x00594220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x00594224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x00594228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x0059422c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x00594230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x00594234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x00594238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x0059423c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00594240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00594244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL 0x00594248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00594300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00594304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00594308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0059430c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1 0x00594310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER4 0x00594314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER5 0x00594318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER6 0x0059431c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER7 0x00594320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER0_S0 0x00594324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER1_S0 0x00594328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER2_S0 0x0059432c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER3_S0 0x00594330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER0_S1 0x00594334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER1_S1 0x00594338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER2_S1 0x0059433c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER3_S1 0x00594340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER0_S2 0x00594344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER1_S2 0x00594348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER2_S2 0x0059434c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER3_S2 0x00594350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER0_S3 0x00594354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER1_S3 0x00594358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER2_S3 0x0059435c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER3_S3 0x00594360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00594364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00594368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059436c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00594370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00594374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00594378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0059437c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00594380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00594384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00594388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059438c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00594390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00594394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00594398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059439c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005943a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005943a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005943a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005943ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005943b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005943b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005943b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005943bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005943c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005943c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00594600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00594604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00594608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0059460c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1 0x00594610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER4 0x00594614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER5 0x00594618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER6 0x0059461c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER7 0x00594620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER0_S0 0x00594624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER1_S0 0x00594628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER2_S0 0x0059462c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER3_S0 0x00594630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER0_S1 0x00594634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER1_S1 0x00594638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER2_S1 0x0059463c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER3_S1 0x00594640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER0_S2 0x00594644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER1_S2 0x00594648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER2_S2 0x0059464c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER3_S2 0x00594650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER0_S3 0x00594654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER1_S3 0x00594658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER2_S3 0x0059465c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER3_S3 0x00594660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00594664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00594668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059466c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00594670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00594674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00594678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0059467c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00594680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00594684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00594688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059468c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00594690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00594694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00594698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059469c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005946a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005946a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005946a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005946ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005946b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005946b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005946b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005946bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005946c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005946c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00594700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00594704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00594708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0059470c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1 0x00594710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER4 0x00594714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER5 0x00594718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER6 0x0059471c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER7 0x00594720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER0_S0 0x00594724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER1_S0 0x00594728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER2_S0 0x0059472c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER3_S0 0x00594730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER0_S1 0x00594734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER1_S1 0x00594738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER2_S1 0x0059473c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER3_S1 0x00594740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER0_S2 0x00594744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER1_S2 0x00594748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER2_S2 0x0059474c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER3_S2 0x00594750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER0_S3 0x00594754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER1_S3 0x00594758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER2_S3 0x0059475c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER3_S3 0x00594760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00594764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00594768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059476c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00594770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00594774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00594778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0059477c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00594780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00594784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00594788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059478c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00594790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00594794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00594798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059479c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005947a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005947a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005947a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005947ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005947b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005947b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005947b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005947bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005947c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005947c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1 0x00594800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00594a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00594a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0 0x00594a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5 0x00594a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1 0x00594a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2 0x00594a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3 0x00594a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4 0x00594a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL 0x00594a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL 0x00594a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL 0x00594a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL 0x00594a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL 0x00594a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL 0x00594a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL 0x00594a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL 0x00594a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00594a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00594a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL 0x00594a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00594b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00594b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00594b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00594b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1 0x00594b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER4 0x00594b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER5 0x00594b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER6 0x00594b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER7 0x00594b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER0_S0 0x00594b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER1_S0 0x00594b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER2_S0 0x00594b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER3_S0 0x00594b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER0_S1 0x00594b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER1_S1 0x00594b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER2_S1 0x00594b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER3_S1 0x00594b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER0_S2 0x00594b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER1_S2 0x00594b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER2_S2 0x00594b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER3_S2 0x00594b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER0_S3 0x00594b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER1_S3 0x00594b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER2_S3 0x00594b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER3_S3 0x00594b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00594b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00594b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00594b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00594b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00594b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00594b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00594b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00594b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00594b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00594b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00594b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00594b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00594b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00594b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00594b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00594ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00594ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00594ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00594bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00594bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00594bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00594bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00594bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00594bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00594bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00594e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00594e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00594e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00594e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1 0x00594e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER4 0x00594e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER5 0x00594e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER6 0x00594e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER7 0x00594e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER0_S0 0x00594e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER1_S0 0x00594e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER2_S0 0x00594e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER3_S0 0x00594e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER0_S1 0x00594e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER1_S1 0x00594e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER2_S1 0x00594e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER3_S1 0x00594e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER0_S2 0x00594e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER1_S2 0x00594e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER2_S2 0x00594e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER3_S2 0x00594e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER0_S3 0x00594e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER1_S3 0x00594e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER2_S3 0x00594e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER3_S3 0x00594e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00594e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00594e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00594e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00594e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00594e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00594e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00594e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00594e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00594e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00594e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00594e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00594e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00594e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00594e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00594e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00594ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00594ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00594ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00594eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00594eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00594eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00594eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00594ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00594ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00594ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00594f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00594f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00594f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00594f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1 0x00594f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER4 0x00594f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER5 0x00594f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER6 0x00594f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER7 0x00594f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER0_S0 0x00594f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER1_S0 0x00594f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER2_S0 0x00594f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER3_S0 0x00594f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER0_S1 0x00594f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER1_S1 0x00594f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER2_S1 0x00594f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER3_S1 0x00594f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER0_S2 0x00594f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER1_S2 0x00594f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER2_S2 0x00594f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER3_S2 0x00594f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER0_S3 0x00594f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER1_S3 0x00594f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER2_S3 0x00594f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER3_S3 0x00594f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00594f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00594f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00594f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00594f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00594f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00594f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00594f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00594f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00594f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00594f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00594f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00594f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00594f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00594f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00594f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00594fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00594fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00594fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00594fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00594fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00594fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00594fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00594fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00594fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00594fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2 0x00595000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00595200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00595204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0 0x00595208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5 0x0059520c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1 0x00595210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2 0x00595214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3 0x00595218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4 0x0059521c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL 0x00595220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL 0x00595224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL 0x00595228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL 0x0059522c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL 0x00595230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL 0x00595234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL 0x00595238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL 0x0059523c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00595240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00595244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL 0x00595248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00595300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00595304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00595308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0059530c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1 0x00595310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER4 0x00595314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER5 0x00595318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER6 0x0059531c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER7 0x00595320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER0_S0 0x00595324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER1_S0 0x00595328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER2_S0 0x0059532c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER3_S0 0x00595330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER0_S1 0x00595334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER1_S1 0x00595338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER2_S1 0x0059533c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER3_S1 0x00595340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER0_S2 0x00595344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER1_S2 0x00595348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER2_S2 0x0059534c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER3_S2 0x00595350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER0_S3 0x00595354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER1_S3 0x00595358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER2_S3 0x0059535c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER3_S3 0x00595360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00595364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00595368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059536c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00595370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00595374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00595378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0059537c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00595380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00595384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00595388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059538c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00595390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00595394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00595398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059539c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005953a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005953a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005953a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005953ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005953b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005953b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005953b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005953bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005953c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005953c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00595600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00595604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00595608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0059560c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1 0x00595610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER4 0x00595614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER5 0x00595618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER6 0x0059561c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER7 0x00595620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER0_S0 0x00595624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER1_S0 0x00595628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER2_S0 0x0059562c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER3_S0 0x00595630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER0_S1 0x00595634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER1_S1 0x00595638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER2_S1 0x0059563c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER3_S1 0x00595640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER0_S2 0x00595644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER1_S2 0x00595648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER2_S2 0x0059564c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER3_S2 0x00595650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER0_S3 0x00595654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER1_S3 0x00595658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER2_S3 0x0059565c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER3_S3 0x00595660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00595664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00595668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059566c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00595670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00595674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00595678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0059567c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00595680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00595684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00595688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059568c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00595690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00595694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00595698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059569c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005956a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005956a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005956a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005956ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005956b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005956b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005956b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005956bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005956c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005956c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00595700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00595704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00595708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0059570c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1 0x00595710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER4 0x00595714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER5 0x00595718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER6 0x0059571c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER7 0x00595720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER0_S0 0x00595724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER1_S0 0x00595728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER2_S0 0x0059572c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER3_S0 0x00595730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER0_S1 0x00595734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER1_S1 0x00595738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER2_S1 0x0059573c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER3_S1 0x00595740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER0_S2 0x00595744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER1_S2 0x00595748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER2_S2 0x0059574c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER3_S2 0x00595750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER0_S3 0x00595754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER1_S3 0x00595758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER2_S3 0x0059575c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER3_S3 0x00595760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00595764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00595768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059576c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00595770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00595774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00595778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0059577c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00595780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00595784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00595788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059578c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00595790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00595794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00595798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059579c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005957a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005957a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005957a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005957ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005957b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005957b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005957b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005957bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005957c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005957c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3 0x00595800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00595a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00595a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0 0x00595a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5 0x00595a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1 0x00595a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2 0x00595a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3 0x00595a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4 0x00595a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL 0x00595a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL 0x00595a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL 0x00595a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL 0x00595a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL 0x00595a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL 0x00595a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL 0x00595a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL 0x00595a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00595a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00595a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL 0x00595a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00595b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00595b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00595b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00595b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1 0x00595b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER4 0x00595b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER5 0x00595b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER6 0x00595b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER7 0x00595b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER0_S0 0x00595b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER1_S0 0x00595b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER2_S0 0x00595b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER3_S0 0x00595b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER0_S1 0x00595b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER1_S1 0x00595b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER2_S1 0x00595b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER3_S1 0x00595b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER0_S2 0x00595b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER1_S2 0x00595b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER2_S2 0x00595b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER3_S2 0x00595b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER0_S3 0x00595b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER1_S3 0x00595b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER2_S3 0x00595b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER3_S3 0x00595b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00595b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00595b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00595b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00595b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00595b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00595b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00595b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00595b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00595b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00595b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00595b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00595b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00595b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00595b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00595b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00595ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00595ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00595ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00595bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00595bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00595bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00595bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00595bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00595bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00595bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00595e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00595e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00595e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00595e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1 0x00595e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER4 0x00595e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER5 0x00595e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER6 0x00595e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER7 0x00595e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER0_S0 0x00595e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER1_S0 0x00595e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER2_S0 0x00595e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER3_S0 0x00595e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER0_S1 0x00595e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER1_S1 0x00595e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER2_S1 0x00595e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER3_S1 0x00595e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER0_S2 0x00595e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER1_S2 0x00595e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER2_S2 0x00595e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER3_S2 0x00595e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER0_S3 0x00595e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER1_S3 0x00595e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER2_S3 0x00595e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER3_S3 0x00595e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00595e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00595e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00595e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00595e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00595e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00595e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00595e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00595e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00595e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00595e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00595e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00595e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00595e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00595e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00595e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00595ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00595ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00595ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00595eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00595eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00595eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00595eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00595ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00595ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00595ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00595f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00595f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00595f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00595f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1 0x00595f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER4 0x00595f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER5 0x00595f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER6 0x00595f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER7 0x00595f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER0_S0 0x00595f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER1_S0 0x00595f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER2_S0 0x00595f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER3_S0 0x00595f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER0_S1 0x00595f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER1_S1 0x00595f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER2_S1 0x00595f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER3_S1 0x00595f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER0_S2 0x00595f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER1_S2 0x00595f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER2_S2 0x00595f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER3_S2 0x00595f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER0_S3 0x00595f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER1_S3 0x00595f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER2_S3 0x00595f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER3_S3 0x00595f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00595f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00595f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00595f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00595f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00595f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00595f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00595f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00595f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00595f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00595f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00595f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00595f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00595f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00595f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00595f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00595fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00595fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00595fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00595fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00595fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00595fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00595fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00595fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00595fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00595fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4 0x00596000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00596200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00596204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0 0x00596208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5 0x0059620c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1 0x00596210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2 0x00596214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3 0x00596218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4 0x0059621c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL 0x00596220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL 0x00596224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL 0x00596228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL 0x0059622c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL 0x00596230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL 0x00596234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL 0x00596238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL 0x0059623c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00596240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00596244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL 0x00596248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00596300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00596304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00596308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0059630c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1 0x00596310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER4 0x00596314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER5 0x00596318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER6 0x0059631c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER7 0x00596320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER0_S0 0x00596324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER1_S0 0x00596328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER2_S0 0x0059632c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER3_S0 0x00596330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER0_S1 0x00596334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER1_S1 0x00596338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER2_S1 0x0059633c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER3_S1 0x00596340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER0_S2 0x00596344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER1_S2 0x00596348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER2_S2 0x0059634c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER3_S2 0x00596350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER0_S3 0x00596354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER1_S3 0x00596358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER2_S3 0x0059635c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER3_S3 0x00596360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00596364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00596368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059636c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00596370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00596374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00596378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0059637c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00596380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00596384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00596388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059638c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00596390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00596394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00596398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059639c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005963a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005963a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005963a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005963ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005963b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005963b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005963b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005963bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005963c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005963c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00596600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00596604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00596608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0059660c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1 0x00596610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER4 0x00596614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER5 0x00596618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER6 0x0059661c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER7 0x00596620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER0_S0 0x00596624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER1_S0 0x00596628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER2_S0 0x0059662c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER3_S0 0x00596630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER0_S1 0x00596634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER1_S1 0x00596638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER2_S1 0x0059663c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER3_S1 0x00596640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER0_S2 0x00596644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER1_S2 0x00596648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER2_S2 0x0059664c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER3_S2 0x00596650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER0_S3 0x00596654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER1_S3 0x00596658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER2_S3 0x0059665c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER3_S3 0x00596660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00596664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00596668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059666c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00596670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00596674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00596678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0059667c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00596680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00596684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00596688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059668c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00596690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00596694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00596698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059669c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005966a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005966a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005966a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005966ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005966b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005966b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005966b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005966bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005966c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005966c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00596700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00596704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00596708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0059670c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1 0x00596710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER4 0x00596714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER5 0x00596718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER6 0x0059671c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER7 0x00596720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER0_S0 0x00596724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER1_S0 0x00596728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER2_S0 0x0059672c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER3_S0 0x00596730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER0_S1 0x00596734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER1_S1 0x00596738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER2_S1 0x0059673c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER3_S1 0x00596740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER0_S2 0x00596744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER1_S2 0x00596748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER2_S2 0x0059674c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER3_S2 0x00596750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER0_S3 0x00596754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER1_S3 0x00596758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER2_S3 0x0059675c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER3_S3 0x00596760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00596764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00596768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059676c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00596770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00596774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00596778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0059677c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00596780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00596784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00596788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059678c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00596790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00596794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00596798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059679c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005967a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005967a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005967a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005967ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005967b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005967b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005967b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005967bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005967c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005967c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5 0x00596800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00596a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00596a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0 0x00596a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5 0x00596a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1 0x00596a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2 0x00596a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3 0x00596a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4 0x00596a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL 0x00596a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL 0x00596a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL 0x00596a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL 0x00596a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL 0x00596a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL 0x00596a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL 0x00596a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL 0x00596a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00596a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00596a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL 0x00596a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00596b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00596b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00596b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00596b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1 0x00596b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER4 0x00596b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER5 0x00596b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER6 0x00596b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER7 0x00596b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER0_S0 0x00596b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER1_S0 0x00596b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER2_S0 0x00596b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER3_S0 0x00596b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER0_S1 0x00596b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER1_S1 0x00596b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER2_S1 0x00596b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER3_S1 0x00596b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER0_S2 0x00596b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER1_S2 0x00596b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER2_S2 0x00596b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER3_S2 0x00596b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER0_S3 0x00596b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER1_S3 0x00596b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER2_S3 0x00596b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER3_S3 0x00596b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00596b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00596b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00596b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00596b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00596b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00596b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00596b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00596b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00596b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00596b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00596b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00596b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00596b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00596b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00596b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00596ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00596ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00596ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00596bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00596bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00596bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00596bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00596bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00596bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00596bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00596e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00596e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00596e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00596e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1 0x00596e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER4 0x00596e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER5 0x00596e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER6 0x00596e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER7 0x00596e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER0_S0 0x00596e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER1_S0 0x00596e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER2_S0 0x00596e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER3_S0 0x00596e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER0_S1 0x00596e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER1_S1 0x00596e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER2_S1 0x00596e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER3_S1 0x00596e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER0_S2 0x00596e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER1_S2 0x00596e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER2_S2 0x00596e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER3_S2 0x00596e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER0_S3 0x00596e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER1_S3 0x00596e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER2_S3 0x00596e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER3_S3 0x00596e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00596e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00596e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00596e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00596e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00596e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00596e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00596e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00596e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00596e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00596e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00596e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00596e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00596e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00596e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00596e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00596ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00596ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00596ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00596eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00596eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00596eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00596eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00596ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00596ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00596ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00596f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00596f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00596f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00596f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1 0x00596f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER4 0x00596f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER5 0x00596f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER6 0x00596f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER7 0x00596f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER0_S0 0x00596f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER1_S0 0x00596f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER2_S0 0x00596f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER3_S0 0x00596f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER0_S1 0x00596f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER1_S1 0x00596f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER2_S1 0x00596f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER3_S1 0x00596f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER0_S2 0x00596f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER1_S2 0x00596f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER2_S2 0x00596f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER3_S2 0x00596f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER0_S3 0x00596f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER1_S3 0x00596f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER2_S3 0x00596f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER3_S3 0x00596f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00596f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00596f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00596f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00596f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00596f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00596f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00596f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00596f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00596f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00596f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00596f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00596f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00596f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00596f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00596f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00596fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00596fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00596fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00596fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00596fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00596fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00596fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00596fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00596fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00596fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS 0x00591800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00591a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00591a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0 0x00591a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5 0x00591a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1 0x00591a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2 0x00591a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3 0x00591a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4 0x00591a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL 0x00591a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL 0x00591a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL 0x00591a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL 0x00591a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL 0x00591a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL 0x00591a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL 0x00591a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL 0x00591a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00591a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00591a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL 0x00591a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00591b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00591b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00591b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00591b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1 0x00591b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER4 0x00591b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER5 0x00591b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER6 0x00591b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER7 0x00591b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER0_S0 0x00591b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER1_S0 0x00591b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER2_S0 0x00591b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER3_S0 0x00591b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER0_S1 0x00591b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER1_S1 0x00591b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER2_S1 0x00591b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER3_S1 0x00591b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER0_S2 0x00591b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER1_S2 0x00591b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER2_S2 0x00591b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER3_S2 0x00591b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER0_S3 0x00591b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER1_S3 0x00591b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER2_S3 0x00591b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER3_S3 0x00591b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00591b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00591b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00591b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00591b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00591b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00591b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00591b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00591b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00591b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00591b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00591b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00591b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00591b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00591b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00591b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00591ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00591ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00591ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00591bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00591bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00591bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00591bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00591bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00591bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00591bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00591e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00591e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00591e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00591e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1 0x00591e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER4 0x00591e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER5 0x00591e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER6 0x00591e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER7 0x00591e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER0_S0 0x00591e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER1_S0 0x00591e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER2_S0 0x00591e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER3_S0 0x00591e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER0_S1 0x00591e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER1_S1 0x00591e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER2_S1 0x00591e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER3_S1 0x00591e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER0_S2 0x00591e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER1_S2 0x00591e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER2_S2 0x00591e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER3_S2 0x00591e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER0_S3 0x00591e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER1_S3 0x00591e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER2_S3 0x00591e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER3_S3 0x00591e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00591e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00591e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00591e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00591e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00591e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00591e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00591e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00591e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00591e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00591e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00591e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00591e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00591e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00591e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00591e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00591ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00591ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00591ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00591eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00591eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00591eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00591eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00591ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00591ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00591ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00591f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00591f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00591f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00591f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1 0x00591f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER4 0x00591f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER5 0x00591f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER6 0x00591f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER7 0x00591f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER0_S0 0x00591f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER1_S0 0x00591f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER2_S0 0x00591f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER3_S0 0x00591f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER0_S1 0x00591f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER1_S1 0x00591f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER2_S1 0x00591f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER3_S1 0x00591f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER0_S2 0x00591f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER1_S2 0x00591f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER2_S2 0x00591f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER3_S2 0x00591f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER0_S3 0x00591f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER1_S3 0x00591f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER2_S3 0x00591f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER3_S3 0x00591f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00591f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00591f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00591f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00591f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00591f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00591f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00591f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00591f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00591f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00591f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00591f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00591f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00591f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00591f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00591f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00591fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00591fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00591fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00591fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00591fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00591fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00591fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00591fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00591fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00591fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC2_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3 0x00598000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC3_ETPC0 0x0059c000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x0059c200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x0059c204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x0059c208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x0059c20c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x0059c210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x0059c214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x0059c218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x0059c21c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x0059c220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x0059c224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x0059c228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x0059c22c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x0059c230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x0059c234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x0059c238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x0059c23c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x0059c240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x0059c244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL 0x0059c248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0 0x0059c300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1 0x0059c304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2 0x0059c308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0059c30c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1 0x0059c310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER4 0x0059c314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER5 0x0059c318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER6 0x0059c31c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER7 0x0059c320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER0_S0 0x0059c324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER1_S0 0x0059c328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER2_S0 0x0059c32c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER3_S0 0x0059c330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER0_S1 0x0059c334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER1_S1 0x0059c338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER2_S1 0x0059c33c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER3_S1 0x0059c340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER0_S2 0x0059c344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER1_S2 0x0059c348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER2_S2 0x0059c34c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER3_S2 0x0059c350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER0_S3 0x0059c354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER1_S3 0x0059c358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER2_S3 0x0059c35c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER3_S3 0x0059c360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059c364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059c368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059c36c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059c370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059c374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x0059c378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0059c37c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x0059c380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x0059c384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059c388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059c38c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059c390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059c394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059c398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059c39c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059c3a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059c3a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059c3a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059c3ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059c3b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059c3b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059c3b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059c3bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059c3c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059c3c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0 0x0059c600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1 0x0059c604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2 0x0059c608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0059c60c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1 0x0059c610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER4 0x0059c614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER5 0x0059c618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER6 0x0059c61c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER7 0x0059c620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER0_S0 0x0059c624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER1_S0 0x0059c628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER2_S0 0x0059c62c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER3_S0 0x0059c630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER0_S1 0x0059c634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER1_S1 0x0059c638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER2_S1 0x0059c63c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER3_S1 0x0059c640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER0_S2 0x0059c644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER1_S2 0x0059c648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER2_S2 0x0059c64c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER3_S2 0x0059c650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER0_S3 0x0059c654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER1_S3 0x0059c658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER2_S3 0x0059c65c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER3_S3 0x0059c660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059c664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059c668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059c66c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059c670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059c674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x0059c678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0059c67c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x0059c680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x0059c684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059c688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059c68c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059c690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059c694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059c698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059c69c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059c6a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059c6a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059c6a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059c6ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059c6b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059c6b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059c6b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059c6bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059c6c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059c6c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0 0x0059c700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1 0x0059c704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2 0x0059c708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0059c70c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1 0x0059c710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER4 0x0059c714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER5 0x0059c718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER6 0x0059c71c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER7 0x0059c720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER0_S0 0x0059c724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER1_S0 0x0059c728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER2_S0 0x0059c72c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER3_S0 0x0059c730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER0_S1 0x0059c734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER1_S1 0x0059c738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER2_S1 0x0059c73c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER3_S1 0x0059c740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER0_S2 0x0059c744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER1_S2 0x0059c748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER2_S2 0x0059c74c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER3_S2 0x0059c750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER0_S3 0x0059c754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER1_S3 0x0059c758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER2_S3 0x0059c75c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER3_S3 0x0059c760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059c764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059c768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059c76c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059c770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059c774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x0059c778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0059c77c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x0059c780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x0059c784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059c788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059c78c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059c790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059c794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059c798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059c79c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059c7a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059c7a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059c7a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059c7ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059c7b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059c7b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059c7b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059c7bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059c7c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059c7c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1 0x0059c800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x0059ca00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x0059ca04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0 0x0059ca08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5 0x0059ca0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1 0x0059ca10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2 0x0059ca14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3 0x0059ca18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4 0x0059ca1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL 0x0059ca20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL 0x0059ca24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL 0x0059ca28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL 0x0059ca2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL 0x0059ca30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL 0x0059ca34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL 0x0059ca38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL 0x0059ca3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x0059ca40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x0059ca44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL 0x0059ca48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0 0x0059cb00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1 0x0059cb04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2 0x0059cb08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0059cb0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1 0x0059cb10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER4 0x0059cb14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER5 0x0059cb18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER6 0x0059cb1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER7 0x0059cb20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER0_S0 0x0059cb24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER1_S0 0x0059cb28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER2_S0 0x0059cb2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER3_S0 0x0059cb30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER0_S1 0x0059cb34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER1_S1 0x0059cb38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER2_S1 0x0059cb3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER3_S1 0x0059cb40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER0_S2 0x0059cb44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER1_S2 0x0059cb48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER2_S2 0x0059cb4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER3_S2 0x0059cb50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER0_S3 0x0059cb54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER1_S3 0x0059cb58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER2_S3 0x0059cb5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER3_S3 0x0059cb60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059cb64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059cb68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059cb6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059cb70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059cb74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x0059cb78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0059cb7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x0059cb80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x0059cb84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059cb88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059cb8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059cb90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059cb94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059cb98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059cb9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059cba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059cba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059cba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059cbac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059cbb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059cbb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059cbb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059cbbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059cbc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059cbc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0 0x0059ce00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1 0x0059ce04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2 0x0059ce08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0059ce0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1 0x0059ce10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER4 0x0059ce14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER5 0x0059ce18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER6 0x0059ce1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER7 0x0059ce20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER0_S0 0x0059ce24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER1_S0 0x0059ce28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER2_S0 0x0059ce2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER3_S0 0x0059ce30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER0_S1 0x0059ce34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER1_S1 0x0059ce38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER2_S1 0x0059ce3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER3_S1 0x0059ce40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER0_S2 0x0059ce44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER1_S2 0x0059ce48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER2_S2 0x0059ce4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER3_S2 0x0059ce50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER0_S3 0x0059ce54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER1_S3 0x0059ce58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER2_S3 0x0059ce5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER3_S3 0x0059ce60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059ce64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059ce68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059ce6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059ce70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059ce74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x0059ce78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0059ce7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x0059ce80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x0059ce84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059ce88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059ce8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059ce90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059ce94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059ce98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059ce9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059cea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059cea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059cea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059ceac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059ceb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059ceb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059ceb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059cebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059cec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059cec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0 0x0059cf00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1 0x0059cf04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2 0x0059cf08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0059cf0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1 0x0059cf10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER4 0x0059cf14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER5 0x0059cf18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER6 0x0059cf1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER7 0x0059cf20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER0_S0 0x0059cf24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER1_S0 0x0059cf28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER2_S0 0x0059cf2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER3_S0 0x0059cf30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER0_S1 0x0059cf34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER1_S1 0x0059cf38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER2_S1 0x0059cf3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER3_S1 0x0059cf40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER0_S2 0x0059cf44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER1_S2 0x0059cf48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER2_S2 0x0059cf4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER3_S2 0x0059cf50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER0_S3 0x0059cf54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER1_S3 0x0059cf58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER2_S3 0x0059cf5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER3_S3 0x0059cf60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059cf64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059cf68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059cf6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059cf70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059cf74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x0059cf78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0059cf7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x0059cf80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x0059cf84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059cf88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059cf8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059cf90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059cf94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059cf98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059cf9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059cfa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059cfa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059cfa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059cfac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059cfb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059cfb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059cfb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059cfbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059cfc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059cfc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2 0x0059d000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x0059d200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x0059d204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0 0x0059d208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5 0x0059d20c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1 0x0059d210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2 0x0059d214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3 0x0059d218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4 0x0059d21c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL 0x0059d220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL 0x0059d224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL 0x0059d228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL 0x0059d22c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL 0x0059d230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL 0x0059d234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL 0x0059d238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL 0x0059d23c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x0059d240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x0059d244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL 0x0059d248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0 0x0059d300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1 0x0059d304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2 0x0059d308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0059d30c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1 0x0059d310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER4 0x0059d314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER5 0x0059d318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER6 0x0059d31c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER7 0x0059d320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER0_S0 0x0059d324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER1_S0 0x0059d328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER2_S0 0x0059d32c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER3_S0 0x0059d330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER0_S1 0x0059d334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER1_S1 0x0059d338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER2_S1 0x0059d33c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER3_S1 0x0059d340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER0_S2 0x0059d344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER1_S2 0x0059d348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER2_S2 0x0059d34c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER3_S2 0x0059d350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER0_S3 0x0059d354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER1_S3 0x0059d358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER2_S3 0x0059d35c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER3_S3 0x0059d360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059d364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059d368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059d36c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059d370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059d374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x0059d378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0059d37c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x0059d380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x0059d384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059d388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059d38c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059d390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059d394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059d398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059d39c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059d3a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059d3a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059d3a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059d3ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059d3b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059d3b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059d3b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059d3bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059d3c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059d3c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0 0x0059d600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1 0x0059d604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2 0x0059d608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0059d60c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1 0x0059d610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER4 0x0059d614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER5 0x0059d618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER6 0x0059d61c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER7 0x0059d620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER0_S0 0x0059d624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER1_S0 0x0059d628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER2_S0 0x0059d62c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER3_S0 0x0059d630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER0_S1 0x0059d634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER1_S1 0x0059d638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER2_S1 0x0059d63c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER3_S1 0x0059d640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER0_S2 0x0059d644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER1_S2 0x0059d648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER2_S2 0x0059d64c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER3_S2 0x0059d650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER0_S3 0x0059d654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER1_S3 0x0059d658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER2_S3 0x0059d65c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER3_S3 0x0059d660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059d664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059d668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059d66c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059d670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059d674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x0059d678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0059d67c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x0059d680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x0059d684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059d688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059d68c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059d690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059d694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059d698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059d69c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059d6a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059d6a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059d6a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059d6ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059d6b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059d6b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059d6b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059d6bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059d6c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059d6c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0 0x0059d700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1 0x0059d704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2 0x0059d708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0059d70c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1 0x0059d710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER4 0x0059d714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER5 0x0059d718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER6 0x0059d71c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER7 0x0059d720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER0_S0 0x0059d724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER1_S0 0x0059d728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER2_S0 0x0059d72c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER3_S0 0x0059d730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER0_S1 0x0059d734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER1_S1 0x0059d738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER2_S1 0x0059d73c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER3_S1 0x0059d740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER0_S2 0x0059d744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER1_S2 0x0059d748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER2_S2 0x0059d74c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER3_S2 0x0059d750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER0_S3 0x0059d754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER1_S3 0x0059d758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER2_S3 0x0059d75c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER3_S3 0x0059d760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059d764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059d768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059d76c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059d770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059d774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x0059d778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0059d77c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x0059d780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x0059d784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059d788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059d78c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059d790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059d794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059d798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059d79c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059d7a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059d7a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059d7a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059d7ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059d7b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059d7b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059d7b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059d7bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059d7c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059d7c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3 0x0059d800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x0059da00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x0059da04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0 0x0059da08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5 0x0059da0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1 0x0059da10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2 0x0059da14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3 0x0059da18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4 0x0059da1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL 0x0059da20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL 0x0059da24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL 0x0059da28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL 0x0059da2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL 0x0059da30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL 0x0059da34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL 0x0059da38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL 0x0059da3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x0059da40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x0059da44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL 0x0059da48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0 0x0059db00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1 0x0059db04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2 0x0059db08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0059db0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1 0x0059db10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER4 0x0059db14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER5 0x0059db18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER6 0x0059db1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER7 0x0059db20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER0_S0 0x0059db24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER1_S0 0x0059db28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER2_S0 0x0059db2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER3_S0 0x0059db30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER0_S1 0x0059db34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER1_S1 0x0059db38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER2_S1 0x0059db3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER3_S1 0x0059db40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER0_S2 0x0059db44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER1_S2 0x0059db48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER2_S2 0x0059db4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER3_S2 0x0059db50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER0_S3 0x0059db54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER1_S3 0x0059db58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER2_S3 0x0059db5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER3_S3 0x0059db60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059db64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059db68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059db6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059db70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059db74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x0059db78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0059db7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x0059db80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x0059db84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059db88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059db8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059db90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059db94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059db98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059db9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059dba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059dba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059dba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059dbac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059dbb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059dbb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059dbb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059dbbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059dbc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059dbc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0 0x0059de00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1 0x0059de04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2 0x0059de08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0059de0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1 0x0059de10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER4 0x0059de14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER5 0x0059de18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER6 0x0059de1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER7 0x0059de20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER0_S0 0x0059de24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER1_S0 0x0059de28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER2_S0 0x0059de2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER3_S0 0x0059de30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER0_S1 0x0059de34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER1_S1 0x0059de38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER2_S1 0x0059de3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER3_S1 0x0059de40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER0_S2 0x0059de44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER1_S2 0x0059de48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER2_S2 0x0059de4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER3_S2 0x0059de50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER0_S3 0x0059de54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER1_S3 0x0059de58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER2_S3 0x0059de5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER3_S3 0x0059de60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059de64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059de68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059de6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059de70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059de74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x0059de78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0059de7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x0059de80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x0059de84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059de88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059de8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059de90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059de94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059de98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059de9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059dea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059dea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059dea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059deac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059deb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059deb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059deb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059debc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059dec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059dec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0 0x0059df00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1 0x0059df04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2 0x0059df08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0059df0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1 0x0059df10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER4 0x0059df14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER5 0x0059df18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER6 0x0059df1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER7 0x0059df20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER0_S0 0x0059df24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER1_S0 0x0059df28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER2_S0 0x0059df2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER3_S0 0x0059df30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER0_S1 0x0059df34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER1_S1 0x0059df38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER2_S1 0x0059df3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER3_S1 0x0059df40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER0_S2 0x0059df44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER1_S2 0x0059df48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER2_S2 0x0059df4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER3_S2 0x0059df50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER0_S3 0x0059df54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER1_S3 0x0059df58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER2_S3 0x0059df5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER3_S3 0x0059df60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059df64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059df68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059df6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059df70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059df74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x0059df78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0059df7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x0059df80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x0059df84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059df88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059df8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059df90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059df94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059df98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059df9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059dfa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059dfa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059dfa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059dfac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059dfb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059dfb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059dfb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059dfbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059dfc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059dfc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4 0x0059e000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x0059e200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x0059e204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0 0x0059e208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5 0x0059e20c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1 0x0059e210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2 0x0059e214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3 0x0059e218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4 0x0059e21c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL 0x0059e220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL 0x0059e224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL 0x0059e228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL 0x0059e22c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL 0x0059e230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL 0x0059e234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL 0x0059e238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL 0x0059e23c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x0059e240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x0059e244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL 0x0059e248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0 0x0059e300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1 0x0059e304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2 0x0059e308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0059e30c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1 0x0059e310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER4 0x0059e314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER5 0x0059e318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER6 0x0059e31c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER7 0x0059e320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER0_S0 0x0059e324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER1_S0 0x0059e328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER2_S0 0x0059e32c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER3_S0 0x0059e330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER0_S1 0x0059e334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER1_S1 0x0059e338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER2_S1 0x0059e33c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER3_S1 0x0059e340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER0_S2 0x0059e344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER1_S2 0x0059e348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER2_S2 0x0059e34c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER3_S2 0x0059e350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER0_S3 0x0059e354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER1_S3 0x0059e358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER2_S3 0x0059e35c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER3_S3 0x0059e360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059e364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059e368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059e36c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059e370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059e374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x0059e378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0059e37c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x0059e380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x0059e384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059e388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059e38c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059e390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059e394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059e398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059e39c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059e3a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059e3a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059e3a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059e3ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059e3b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059e3b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059e3b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059e3bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059e3c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059e3c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0 0x0059e600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1 0x0059e604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2 0x0059e608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0059e60c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1 0x0059e610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER4 0x0059e614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER5 0x0059e618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER6 0x0059e61c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER7 0x0059e620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER0_S0 0x0059e624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER1_S0 0x0059e628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER2_S0 0x0059e62c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER3_S0 0x0059e630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER0_S1 0x0059e634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER1_S1 0x0059e638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER2_S1 0x0059e63c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER3_S1 0x0059e640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER0_S2 0x0059e644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER1_S2 0x0059e648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER2_S2 0x0059e64c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER3_S2 0x0059e650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER0_S3 0x0059e654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER1_S3 0x0059e658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER2_S3 0x0059e65c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER3_S3 0x0059e660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059e664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059e668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059e66c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059e670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059e674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x0059e678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0059e67c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x0059e680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x0059e684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059e688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059e68c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059e690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059e694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059e698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059e69c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059e6a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059e6a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059e6a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059e6ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059e6b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059e6b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059e6b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059e6bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059e6c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059e6c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0 0x0059e700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1 0x0059e704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2 0x0059e708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0059e70c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1 0x0059e710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER4 0x0059e714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER5 0x0059e718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER6 0x0059e71c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER7 0x0059e720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER0_S0 0x0059e724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER1_S0 0x0059e728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER2_S0 0x0059e72c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER3_S0 0x0059e730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER0_S1 0x0059e734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER1_S1 0x0059e738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER2_S1 0x0059e73c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER3_S1 0x0059e740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER0_S2 0x0059e744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER1_S2 0x0059e748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER2_S2 0x0059e74c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER3_S2 0x0059e750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER0_S3 0x0059e754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER1_S3 0x0059e758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER2_S3 0x0059e75c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER3_S3 0x0059e760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059e764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059e768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059e76c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059e770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059e774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x0059e778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0059e77c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x0059e780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x0059e784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059e788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059e78c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059e790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059e794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059e798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059e79c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059e7a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059e7a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059e7a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059e7ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059e7b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059e7b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059e7b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059e7bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059e7c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059e7c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5 0x0059e800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x0059ea00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x0059ea04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0 0x0059ea08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5 0x0059ea0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1 0x0059ea10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2 0x0059ea14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3 0x0059ea18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4 0x0059ea1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL 0x0059ea20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL 0x0059ea24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL 0x0059ea28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL 0x0059ea2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL 0x0059ea30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL 0x0059ea34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL 0x0059ea38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL 0x0059ea3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x0059ea40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x0059ea44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL 0x0059ea48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0 0x0059eb00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1 0x0059eb04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2 0x0059eb08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0059eb0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1 0x0059eb10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER4 0x0059eb14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER5 0x0059eb18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER6 0x0059eb1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER7 0x0059eb20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER0_S0 0x0059eb24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER1_S0 0x0059eb28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER2_S0 0x0059eb2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER3_S0 0x0059eb30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER0_S1 0x0059eb34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER1_S1 0x0059eb38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER2_S1 0x0059eb3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER3_S1 0x0059eb40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER0_S2 0x0059eb44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER1_S2 0x0059eb48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER2_S2 0x0059eb4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER3_S2 0x0059eb50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER0_S3 0x0059eb54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER1_S3 0x0059eb58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER2_S3 0x0059eb5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER3_S3 0x0059eb60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059eb64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059eb68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059eb6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059eb70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059eb74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x0059eb78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0059eb7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x0059eb80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x0059eb84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059eb88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059eb8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059eb90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059eb94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059eb98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059eb9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059eba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059eba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059eba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059ebac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059ebb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059ebb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059ebb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059ebbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059ebc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059ebc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0 0x0059ee00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1 0x0059ee04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2 0x0059ee08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0059ee0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1 0x0059ee10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER4 0x0059ee14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER5 0x0059ee18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER6 0x0059ee1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER7 0x0059ee20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER0_S0 0x0059ee24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER1_S0 0x0059ee28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER2_S0 0x0059ee2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER3_S0 0x0059ee30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER0_S1 0x0059ee34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER1_S1 0x0059ee38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER2_S1 0x0059ee3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER3_S1 0x0059ee40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER0_S2 0x0059ee44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER1_S2 0x0059ee48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER2_S2 0x0059ee4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER3_S2 0x0059ee50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER0_S3 0x0059ee54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER1_S3 0x0059ee58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER2_S3 0x0059ee5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER3_S3 0x0059ee60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059ee64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059ee68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059ee6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059ee70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059ee74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x0059ee78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0059ee7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x0059ee80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x0059ee84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059ee88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059ee8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059ee90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059ee94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059ee98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059ee9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059eea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059eea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059eea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059eeac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059eeb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059eeb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059eeb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059eebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059eec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059eec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0 0x0059ef00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1 0x0059ef04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2 0x0059ef08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0059ef0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1 0x0059ef10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER4 0x0059ef14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER5 0x0059ef18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER6 0x0059ef1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER7 0x0059ef20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER0_S0 0x0059ef24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER1_S0 0x0059ef28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER2_S0 0x0059ef2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER3_S0 0x0059ef30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER0_S1 0x0059ef34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER1_S1 0x0059ef38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER2_S1 0x0059ef3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER3_S1 0x0059ef40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER0_S2 0x0059ef44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER1_S2 0x0059ef48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER2_S2 0x0059ef4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER3_S2 0x0059ef50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER0_S3 0x0059ef54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER1_S3 0x0059ef58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER2_S3 0x0059ef5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER3_S3 0x0059ef60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x0059ef64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x0059ef68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0059ef6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x0059ef70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x0059ef74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x0059ef78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0059ef7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x0059ef80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x0059ef84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x0059ef88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0059ef8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x0059ef90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x0059ef94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x0059ef98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0059ef9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x0059efa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x0059efa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x0059efa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x0059efac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x0059efb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x0059efb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x0059efb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x0059efbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x0059efc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x0059efc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS 0x00599800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00599a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00599a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0 0x00599a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5 0x00599a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1 0x00599a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2 0x00599a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3 0x00599a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4 0x00599a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL 0x00599a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL 0x00599a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL 0x00599a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL 0x00599a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL 0x00599a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL 0x00599a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL 0x00599a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL 0x00599a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00599a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00599a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL 0x00599a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00599b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00599b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00599b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00599b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1 0x00599b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER4 0x00599b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER5 0x00599b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER6 0x00599b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER7 0x00599b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER0_S0 0x00599b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER1_S0 0x00599b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER2_S0 0x00599b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER3_S0 0x00599b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER0_S1 0x00599b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER1_S1 0x00599b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER2_S1 0x00599b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER3_S1 0x00599b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER0_S2 0x00599b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER1_S2 0x00599b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER2_S2 0x00599b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER3_S2 0x00599b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER0_S3 0x00599b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER1_S3 0x00599b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER2_S3 0x00599b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER3_S3 0x00599b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00599b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00599b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00599b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00599b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00599b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00599b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00599b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00599b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00599b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00599b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00599b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00599b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00599b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00599b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00599b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00599ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00599ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00599ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00599bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00599bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00599bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00599bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00599bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00599bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00599bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00599e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00599e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00599e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00599e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1 0x00599e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER4 0x00599e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER5 0x00599e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER6 0x00599e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER7 0x00599e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER0_S0 0x00599e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER1_S0 0x00599e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER2_S0 0x00599e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER3_S0 0x00599e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER0_S1 0x00599e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER1_S1 0x00599e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER2_S1 0x00599e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER3_S1 0x00599e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER0_S2 0x00599e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER1_S2 0x00599e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER2_S2 0x00599e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER3_S2 0x00599e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER0_S3 0x00599e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER1_S3 0x00599e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER2_S3 0x00599e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER3_S3 0x00599e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00599e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00599e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00599e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00599e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00599e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00599e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00599e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00599e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00599e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00599e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00599e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00599e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00599e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00599e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00599e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00599ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00599ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00599ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00599eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00599eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00599eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00599eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00599ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00599ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00599ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00599f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00599f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00599f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00599f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1 0x00599f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER4 0x00599f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER5 0x00599f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER6 0x00599f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER7 0x00599f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER0_S0 0x00599f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER1_S0 0x00599f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER2_S0 0x00599f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER3_S0 0x00599f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER0_S1 0x00599f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER1_S1 0x00599f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER2_S1 0x00599f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER3_S1 0x00599f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER0_S2 0x00599f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER1_S2 0x00599f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER2_S2 0x00599f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER3_S2 0x00599f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER0_S3 0x00599f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER1_S3 0x00599f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER2_S3 0x00599f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER3_S3 0x00599f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00599f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00599f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00599f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00599f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00599f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00599f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00599f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00599f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00599f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00599f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00599f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00599f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00599f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00599f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00599f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00599fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00599fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00599fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00599fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00599fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00599fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00599fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00599fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00599fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00599fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC3_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4 0x005a0000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC4_ETPC0 0x005a4000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005a4200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005a4204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x005a4208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x005a420c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x005a4210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x005a4214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x005a4218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x005a421c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x005a4220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x005a4224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x005a4228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x005a422c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x005a4230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x005a4234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x005a4238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x005a423c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005a4240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005a4244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL 0x005a4248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005a4300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005a4304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005a4308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005a430c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1 0x005a4310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER4 0x005a4314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER5 0x005a4318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER6 0x005a431c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER7 0x005a4320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER0_S0 0x005a4324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER1_S0 0x005a4328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER2_S0 0x005a432c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER3_S0 0x005a4330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER0_S1 0x005a4334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER1_S1 0x005a4338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER2_S1 0x005a433c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER3_S1 0x005a4340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER0_S2 0x005a4344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER1_S2 0x005a4348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER2_S2 0x005a434c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER3_S2 0x005a4350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER0_S3 0x005a4354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER1_S3 0x005a4358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER2_S3 0x005a435c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER3_S3 0x005a4360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a4364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a4368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a436c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a4370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a4374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005a4378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005a437c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005a4380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005a4384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a4388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a438c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a4390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a4394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a4398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a439c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a43a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a43a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a43a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a43ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a43b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a43b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a43b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a43bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a43c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a43c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005a4600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005a4604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005a4608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005a460c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1 0x005a4610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER4 0x005a4614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER5 0x005a4618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER6 0x005a461c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER7 0x005a4620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER0_S0 0x005a4624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER1_S0 0x005a4628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER2_S0 0x005a462c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER3_S0 0x005a4630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER0_S1 0x005a4634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER1_S1 0x005a4638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER2_S1 0x005a463c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER3_S1 0x005a4640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER0_S2 0x005a4644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER1_S2 0x005a4648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER2_S2 0x005a464c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER3_S2 0x005a4650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER0_S3 0x005a4654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER1_S3 0x005a4658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER2_S3 0x005a465c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER3_S3 0x005a4660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a4664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a4668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a466c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a4670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a4674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005a4678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005a467c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005a4680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005a4684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a4688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a468c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a4690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a4694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a4698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a469c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a46a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a46a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a46a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a46ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a46b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a46b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a46b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a46bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a46c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a46c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005a4700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005a4704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005a4708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005a470c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1 0x005a4710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER4 0x005a4714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER5 0x005a4718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER6 0x005a471c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER7 0x005a4720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER0_S0 0x005a4724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER1_S0 0x005a4728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER2_S0 0x005a472c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER3_S0 0x005a4730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER0_S1 0x005a4734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER1_S1 0x005a4738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER2_S1 0x005a473c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER3_S1 0x005a4740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER0_S2 0x005a4744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER1_S2 0x005a4748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER2_S2 0x005a474c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER3_S2 0x005a4750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER0_S3 0x005a4754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER1_S3 0x005a4758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER2_S3 0x005a475c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER3_S3 0x005a4760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a4764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a4768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a476c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a4770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a4774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005a4778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005a477c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005a4780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005a4784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a4788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a478c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a4790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a4794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a4798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a479c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a47a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a47a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a47a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a47ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a47b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a47b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a47b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a47bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a47c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a47c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1 0x005a4800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005a4a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005a4a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0 0x005a4a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5 0x005a4a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1 0x005a4a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2 0x005a4a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3 0x005a4a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4 0x005a4a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL 0x005a4a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL 0x005a4a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL 0x005a4a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL 0x005a4a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL 0x005a4a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL 0x005a4a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL 0x005a4a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL 0x005a4a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005a4a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005a4a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL 0x005a4a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005a4b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005a4b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005a4b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005a4b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1 0x005a4b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER4 0x005a4b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER5 0x005a4b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER6 0x005a4b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER7 0x005a4b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER0_S0 0x005a4b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER1_S0 0x005a4b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER2_S0 0x005a4b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER3_S0 0x005a4b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER0_S1 0x005a4b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER1_S1 0x005a4b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER2_S1 0x005a4b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER3_S1 0x005a4b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER0_S2 0x005a4b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER1_S2 0x005a4b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER2_S2 0x005a4b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER3_S2 0x005a4b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER0_S3 0x005a4b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER1_S3 0x005a4b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER2_S3 0x005a4b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER3_S3 0x005a4b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a4b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a4b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a4b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a4b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a4b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005a4b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005a4b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005a4b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005a4b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a4b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a4b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a4b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a4b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a4b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a4b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a4ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a4ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a4ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a4bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a4bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a4bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a4bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a4bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a4bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a4bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005a4e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005a4e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005a4e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005a4e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1 0x005a4e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER4 0x005a4e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER5 0x005a4e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER6 0x005a4e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER7 0x005a4e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER0_S0 0x005a4e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER1_S0 0x005a4e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER2_S0 0x005a4e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER3_S0 0x005a4e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER0_S1 0x005a4e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER1_S1 0x005a4e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER2_S1 0x005a4e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER3_S1 0x005a4e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER0_S2 0x005a4e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER1_S2 0x005a4e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER2_S2 0x005a4e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER3_S2 0x005a4e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER0_S3 0x005a4e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER1_S3 0x005a4e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER2_S3 0x005a4e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER3_S3 0x005a4e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a4e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a4e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a4e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a4e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a4e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005a4e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005a4e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005a4e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005a4e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a4e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a4e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a4e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a4e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a4e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a4e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a4ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a4ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a4ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a4eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a4eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a4eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a4eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a4ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a4ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a4ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005a4f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005a4f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005a4f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005a4f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1 0x005a4f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER4 0x005a4f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER5 0x005a4f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER6 0x005a4f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER7 0x005a4f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER0_S0 0x005a4f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER1_S0 0x005a4f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER2_S0 0x005a4f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER3_S0 0x005a4f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER0_S1 0x005a4f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER1_S1 0x005a4f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER2_S1 0x005a4f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER3_S1 0x005a4f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER0_S2 0x005a4f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER1_S2 0x005a4f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER2_S2 0x005a4f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER3_S2 0x005a4f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER0_S3 0x005a4f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER1_S3 0x005a4f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER2_S3 0x005a4f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER3_S3 0x005a4f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a4f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a4f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a4f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a4f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a4f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005a4f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005a4f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005a4f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005a4f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a4f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a4f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a4f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a4f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a4f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a4f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a4fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a4fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a4fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a4fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a4fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a4fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a4fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a4fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a4fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a4fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2 0x005a5000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005a5200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005a5204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0 0x005a5208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5 0x005a520c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1 0x005a5210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2 0x005a5214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3 0x005a5218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4 0x005a521c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL 0x005a5220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL 0x005a5224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL 0x005a5228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL 0x005a522c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL 0x005a5230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL 0x005a5234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL 0x005a5238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL 0x005a523c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005a5240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005a5244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL 0x005a5248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005a5300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005a5304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005a5308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005a530c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1 0x005a5310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER4 0x005a5314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER5 0x005a5318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER6 0x005a531c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER7 0x005a5320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER0_S0 0x005a5324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER1_S0 0x005a5328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER2_S0 0x005a532c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER3_S0 0x005a5330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER0_S1 0x005a5334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER1_S1 0x005a5338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER2_S1 0x005a533c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER3_S1 0x005a5340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER0_S2 0x005a5344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER1_S2 0x005a5348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER2_S2 0x005a534c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER3_S2 0x005a5350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER0_S3 0x005a5354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER1_S3 0x005a5358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER2_S3 0x005a535c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER3_S3 0x005a5360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a5364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a5368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a536c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a5370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a5374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005a5378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005a537c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005a5380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005a5384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a5388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a538c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a5390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a5394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a5398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a539c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a53a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a53a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a53a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a53ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a53b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a53b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a53b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a53bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a53c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a53c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005a5600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005a5604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005a5608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005a560c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1 0x005a5610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER4 0x005a5614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER5 0x005a5618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER6 0x005a561c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER7 0x005a5620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER0_S0 0x005a5624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER1_S0 0x005a5628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER2_S0 0x005a562c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER3_S0 0x005a5630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER0_S1 0x005a5634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER1_S1 0x005a5638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER2_S1 0x005a563c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER3_S1 0x005a5640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER0_S2 0x005a5644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER1_S2 0x005a5648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER2_S2 0x005a564c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER3_S2 0x005a5650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER0_S3 0x005a5654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER1_S3 0x005a5658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER2_S3 0x005a565c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER3_S3 0x005a5660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a5664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a5668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a566c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a5670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a5674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005a5678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005a567c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005a5680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005a5684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a5688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a568c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a5690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a5694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a5698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a569c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a56a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a56a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a56a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a56ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a56b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a56b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a56b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a56bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a56c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a56c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005a5700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005a5704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005a5708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005a570c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1 0x005a5710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER4 0x005a5714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER5 0x005a5718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER6 0x005a571c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER7 0x005a5720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER0_S0 0x005a5724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER1_S0 0x005a5728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER2_S0 0x005a572c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER3_S0 0x005a5730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER0_S1 0x005a5734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER1_S1 0x005a5738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER2_S1 0x005a573c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER3_S1 0x005a5740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER0_S2 0x005a5744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER1_S2 0x005a5748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER2_S2 0x005a574c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER3_S2 0x005a5750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER0_S3 0x005a5754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER1_S3 0x005a5758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER2_S3 0x005a575c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER3_S3 0x005a5760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a5764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a5768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a576c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a5770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a5774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005a5778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005a577c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005a5780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005a5784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a5788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a578c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a5790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a5794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a5798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a579c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a57a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a57a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a57a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a57ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a57b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a57b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a57b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a57bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a57c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a57c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3 0x005a5800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005a5a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005a5a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0 0x005a5a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5 0x005a5a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1 0x005a5a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2 0x005a5a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3 0x005a5a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4 0x005a5a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL 0x005a5a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL 0x005a5a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL 0x005a5a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL 0x005a5a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL 0x005a5a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL 0x005a5a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL 0x005a5a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL 0x005a5a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005a5a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005a5a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL 0x005a5a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005a5b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005a5b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005a5b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005a5b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1 0x005a5b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER4 0x005a5b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER5 0x005a5b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER6 0x005a5b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER7 0x005a5b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER0_S0 0x005a5b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER1_S0 0x005a5b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER2_S0 0x005a5b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER3_S0 0x005a5b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER0_S1 0x005a5b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER1_S1 0x005a5b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER2_S1 0x005a5b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER3_S1 0x005a5b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER0_S2 0x005a5b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER1_S2 0x005a5b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER2_S2 0x005a5b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER3_S2 0x005a5b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER0_S3 0x005a5b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER1_S3 0x005a5b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER2_S3 0x005a5b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER3_S3 0x005a5b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a5b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a5b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a5b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a5b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a5b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005a5b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005a5b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005a5b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005a5b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a5b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a5b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a5b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a5b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a5b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a5b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a5ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a5ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a5ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a5bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a5bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a5bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a5bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a5bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a5bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a5bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005a5e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005a5e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005a5e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005a5e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1 0x005a5e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER4 0x005a5e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER5 0x005a5e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER6 0x005a5e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER7 0x005a5e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER0_S0 0x005a5e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER1_S0 0x005a5e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER2_S0 0x005a5e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER3_S0 0x005a5e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER0_S1 0x005a5e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER1_S1 0x005a5e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER2_S1 0x005a5e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER3_S1 0x005a5e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER0_S2 0x005a5e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER1_S2 0x005a5e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER2_S2 0x005a5e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER3_S2 0x005a5e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER0_S3 0x005a5e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER1_S3 0x005a5e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER2_S3 0x005a5e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER3_S3 0x005a5e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a5e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a5e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a5e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a5e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a5e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005a5e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005a5e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005a5e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005a5e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a5e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a5e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a5e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a5e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a5e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a5e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a5ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a5ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a5ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a5eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a5eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a5eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a5eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a5ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a5ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a5ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005a5f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005a5f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005a5f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005a5f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1 0x005a5f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER4 0x005a5f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER5 0x005a5f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER6 0x005a5f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER7 0x005a5f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER0_S0 0x005a5f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER1_S0 0x005a5f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER2_S0 0x005a5f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER3_S0 0x005a5f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER0_S1 0x005a5f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER1_S1 0x005a5f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER2_S1 0x005a5f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER3_S1 0x005a5f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER0_S2 0x005a5f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER1_S2 0x005a5f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER2_S2 0x005a5f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER3_S2 0x005a5f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER0_S3 0x005a5f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER1_S3 0x005a5f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER2_S3 0x005a5f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER3_S3 0x005a5f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a5f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a5f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a5f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a5f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a5f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005a5f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005a5f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005a5f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005a5f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a5f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a5f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a5f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a5f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a5f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a5f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a5fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a5fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a5fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a5fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a5fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a5fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a5fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a5fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a5fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a5fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4 0x005a6000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005a6200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005a6204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0 0x005a6208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5 0x005a620c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1 0x005a6210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2 0x005a6214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3 0x005a6218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4 0x005a621c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL 0x005a6220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL 0x005a6224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL 0x005a6228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL 0x005a622c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL 0x005a6230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL 0x005a6234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL 0x005a6238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL 0x005a623c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005a6240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005a6244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL 0x005a6248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005a6300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005a6304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005a6308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005a630c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1 0x005a6310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER4 0x005a6314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER5 0x005a6318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER6 0x005a631c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER7 0x005a6320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER0_S0 0x005a6324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER1_S0 0x005a6328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER2_S0 0x005a632c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER3_S0 0x005a6330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER0_S1 0x005a6334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER1_S1 0x005a6338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER2_S1 0x005a633c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER3_S1 0x005a6340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER0_S2 0x005a6344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER1_S2 0x005a6348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER2_S2 0x005a634c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER3_S2 0x005a6350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER0_S3 0x005a6354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER1_S3 0x005a6358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER2_S3 0x005a635c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER3_S3 0x005a6360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a6364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a6368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a636c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a6370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a6374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005a6378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005a637c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005a6380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005a6384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a6388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a638c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a6390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a6394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a6398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a639c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a63a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a63a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a63a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a63ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a63b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a63b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a63b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a63bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a63c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a63c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005a6600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005a6604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005a6608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005a660c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1 0x005a6610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER4 0x005a6614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER5 0x005a6618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER6 0x005a661c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER7 0x005a6620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER0_S0 0x005a6624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER1_S0 0x005a6628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER2_S0 0x005a662c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER3_S0 0x005a6630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER0_S1 0x005a6634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER1_S1 0x005a6638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER2_S1 0x005a663c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER3_S1 0x005a6640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER0_S2 0x005a6644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER1_S2 0x005a6648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER2_S2 0x005a664c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER3_S2 0x005a6650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER0_S3 0x005a6654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER1_S3 0x005a6658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER2_S3 0x005a665c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER3_S3 0x005a6660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a6664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a6668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a666c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a6670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a6674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005a6678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005a667c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005a6680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005a6684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a6688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a668c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a6690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a6694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a6698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a669c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a66a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a66a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a66a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a66ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a66b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a66b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a66b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a66bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a66c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a66c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005a6700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005a6704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005a6708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005a670c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1 0x005a6710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER4 0x005a6714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER5 0x005a6718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER6 0x005a671c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER7 0x005a6720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER0_S0 0x005a6724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER1_S0 0x005a6728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER2_S0 0x005a672c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER3_S0 0x005a6730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER0_S1 0x005a6734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER1_S1 0x005a6738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER2_S1 0x005a673c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER3_S1 0x005a6740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER0_S2 0x005a6744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER1_S2 0x005a6748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER2_S2 0x005a674c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER3_S2 0x005a6750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER0_S3 0x005a6754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER1_S3 0x005a6758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER2_S3 0x005a675c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER3_S3 0x005a6760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a6764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a6768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a676c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a6770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a6774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005a6778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005a677c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005a6780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005a6784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a6788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a678c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a6790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a6794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a6798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a679c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a67a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a67a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a67a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a67ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a67b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a67b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a67b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a67bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a67c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a67c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5 0x005a6800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005a6a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005a6a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0 0x005a6a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5 0x005a6a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1 0x005a6a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2 0x005a6a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3 0x005a6a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4 0x005a6a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL 0x005a6a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL 0x005a6a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL 0x005a6a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL 0x005a6a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL 0x005a6a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL 0x005a6a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL 0x005a6a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL 0x005a6a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005a6a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005a6a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL 0x005a6a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005a6b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005a6b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005a6b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005a6b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1 0x005a6b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER4 0x005a6b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER5 0x005a6b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER6 0x005a6b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER7 0x005a6b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER0_S0 0x005a6b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER1_S0 0x005a6b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER2_S0 0x005a6b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER3_S0 0x005a6b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER0_S1 0x005a6b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER1_S1 0x005a6b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER2_S1 0x005a6b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER3_S1 0x005a6b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER0_S2 0x005a6b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER1_S2 0x005a6b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER2_S2 0x005a6b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER3_S2 0x005a6b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER0_S3 0x005a6b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER1_S3 0x005a6b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER2_S3 0x005a6b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER3_S3 0x005a6b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a6b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a6b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a6b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a6b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a6b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005a6b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005a6b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005a6b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005a6b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a6b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a6b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a6b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a6b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a6b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a6b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a6ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a6ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a6ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a6bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a6bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a6bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a6bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a6bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a6bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a6bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005a6e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005a6e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005a6e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005a6e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1 0x005a6e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER4 0x005a6e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER5 0x005a6e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER6 0x005a6e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER7 0x005a6e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER0_S0 0x005a6e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER1_S0 0x005a6e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER2_S0 0x005a6e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER3_S0 0x005a6e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER0_S1 0x005a6e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER1_S1 0x005a6e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER2_S1 0x005a6e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER3_S1 0x005a6e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER0_S2 0x005a6e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER1_S2 0x005a6e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER2_S2 0x005a6e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER3_S2 0x005a6e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER0_S3 0x005a6e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER1_S3 0x005a6e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER2_S3 0x005a6e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER3_S3 0x005a6e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a6e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a6e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a6e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a6e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a6e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005a6e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005a6e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005a6e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005a6e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a6e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a6e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a6e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a6e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a6e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a6e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a6ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a6ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a6ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a6eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a6eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a6eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a6eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a6ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a6ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a6ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005a6f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005a6f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005a6f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005a6f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1 0x005a6f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER4 0x005a6f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER5 0x005a6f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER6 0x005a6f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER7 0x005a6f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER0_S0 0x005a6f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER1_S0 0x005a6f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER2_S0 0x005a6f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER3_S0 0x005a6f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER0_S1 0x005a6f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER1_S1 0x005a6f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER2_S1 0x005a6f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER3_S1 0x005a6f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER0_S2 0x005a6f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER1_S2 0x005a6f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER2_S2 0x005a6f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER3_S2 0x005a6f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER0_S3 0x005a6f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER1_S3 0x005a6f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER2_S3 0x005a6f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER3_S3 0x005a6f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a6f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a6f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a6f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a6f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a6f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005a6f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005a6f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005a6f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005a6f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a6f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a6f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a6f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a6f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a6f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a6f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a6fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a6fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a6fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a6fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a6fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a6fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a6fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a6fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a6fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a6fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS 0x005a1800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005a1a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005a1a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0 0x005a1a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5 0x005a1a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1 0x005a1a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2 0x005a1a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3 0x005a1a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4 0x005a1a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL 0x005a1a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL 0x005a1a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL 0x005a1a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL 0x005a1a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL 0x005a1a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL 0x005a1a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL 0x005a1a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL 0x005a1a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005a1a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005a1a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL 0x005a1a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005a1b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005a1b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005a1b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005a1b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1 0x005a1b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER4 0x005a1b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER5 0x005a1b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER6 0x005a1b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER7 0x005a1b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER0_S0 0x005a1b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER1_S0 0x005a1b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER2_S0 0x005a1b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER3_S0 0x005a1b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER0_S1 0x005a1b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER1_S1 0x005a1b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER2_S1 0x005a1b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER3_S1 0x005a1b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER0_S2 0x005a1b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER1_S2 0x005a1b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER2_S2 0x005a1b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER3_S2 0x005a1b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER0_S3 0x005a1b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER1_S3 0x005a1b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER2_S3 0x005a1b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER3_S3 0x005a1b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a1b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a1b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a1b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a1b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a1b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005a1b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005a1b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005a1b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005a1b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a1b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a1b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a1b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a1b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a1b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a1b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a1ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a1ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a1ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a1bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a1bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a1bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a1bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a1bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a1bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a1bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005a1e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005a1e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005a1e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005a1e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1 0x005a1e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER4 0x005a1e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER5 0x005a1e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER6 0x005a1e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER7 0x005a1e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER0_S0 0x005a1e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER1_S0 0x005a1e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER2_S0 0x005a1e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER3_S0 0x005a1e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER0_S1 0x005a1e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER1_S1 0x005a1e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER2_S1 0x005a1e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER3_S1 0x005a1e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER0_S2 0x005a1e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER1_S2 0x005a1e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER2_S2 0x005a1e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER3_S2 0x005a1e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER0_S3 0x005a1e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER1_S3 0x005a1e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER2_S3 0x005a1e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER3_S3 0x005a1e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a1e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a1e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a1e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a1e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a1e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005a1e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005a1e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005a1e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005a1e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a1e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a1e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a1e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a1e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a1e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a1e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a1ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a1ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a1ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a1eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a1eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a1eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a1eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a1ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a1ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a1ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005a1f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005a1f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005a1f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005a1f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1 0x005a1f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER4 0x005a1f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER5 0x005a1f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER6 0x005a1f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER7 0x005a1f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER0_S0 0x005a1f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER1_S0 0x005a1f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER2_S0 0x005a1f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER3_S0 0x005a1f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER0_S1 0x005a1f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER1_S1 0x005a1f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER2_S1 0x005a1f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER3_S1 0x005a1f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER0_S2 0x005a1f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER1_S2 0x005a1f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER2_S2 0x005a1f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER3_S2 0x005a1f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER0_S3 0x005a1f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER1_S3 0x005a1f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER2_S3 0x005a1f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER3_S3 0x005a1f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a1f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a1f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a1f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a1f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a1f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005a1f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005a1f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005a1f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005a1f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a1f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a1f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a1f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a1f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a1f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a1f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a1fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a1fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a1fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a1fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a1fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a1fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a1fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a1fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a1fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a1fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC4_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5 0x005a8000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC5_ETPC0 0x005ac000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005ac200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005ac204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x005ac208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x005ac20c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x005ac210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x005ac214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x005ac218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x005ac21c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x005ac220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x005ac224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x005ac228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x005ac22c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x005ac230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x005ac234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x005ac238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x005ac23c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005ac240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005ac244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL 0x005ac248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005ac300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005ac304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005ac308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005ac30c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1 0x005ac310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER4 0x005ac314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER5 0x005ac318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER6 0x005ac31c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER7 0x005ac320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER0_S0 0x005ac324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER1_S0 0x005ac328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER2_S0 0x005ac32c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER3_S0 0x005ac330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER0_S1 0x005ac334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER1_S1 0x005ac338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER2_S1 0x005ac33c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER3_S1 0x005ac340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER0_S2 0x005ac344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER1_S2 0x005ac348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER2_S2 0x005ac34c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER3_S2 0x005ac350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER0_S3 0x005ac354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER1_S3 0x005ac358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER2_S3 0x005ac35c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER3_S3 0x005ac360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005ac364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005ac368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005ac36c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005ac370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005ac374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005ac378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005ac37c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005ac380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005ac384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005ac388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005ac38c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005ac390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005ac394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005ac398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005ac39c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005ac3a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005ac3a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005ac3a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005ac3ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005ac3b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005ac3b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005ac3b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005ac3bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005ac3c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005ac3c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005ac600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005ac604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005ac608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005ac60c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1 0x005ac610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER4 0x005ac614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER5 0x005ac618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER6 0x005ac61c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER7 0x005ac620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER0_S0 0x005ac624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER1_S0 0x005ac628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER2_S0 0x005ac62c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER3_S0 0x005ac630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER0_S1 0x005ac634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER1_S1 0x005ac638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER2_S1 0x005ac63c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER3_S1 0x005ac640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER0_S2 0x005ac644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER1_S2 0x005ac648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER2_S2 0x005ac64c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER3_S2 0x005ac650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER0_S3 0x005ac654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER1_S3 0x005ac658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER2_S3 0x005ac65c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER3_S3 0x005ac660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005ac664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005ac668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005ac66c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005ac670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005ac674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005ac678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005ac67c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005ac680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005ac684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005ac688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005ac68c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005ac690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005ac694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005ac698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005ac69c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005ac6a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005ac6a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005ac6a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005ac6ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005ac6b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005ac6b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005ac6b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005ac6bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005ac6c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005ac6c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005ac700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005ac704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005ac708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005ac70c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1 0x005ac710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER4 0x005ac714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER5 0x005ac718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER6 0x005ac71c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER7 0x005ac720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER0_S0 0x005ac724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER1_S0 0x005ac728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER2_S0 0x005ac72c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER3_S0 0x005ac730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER0_S1 0x005ac734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER1_S1 0x005ac738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER2_S1 0x005ac73c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER3_S1 0x005ac740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER0_S2 0x005ac744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER1_S2 0x005ac748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER2_S2 0x005ac74c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER3_S2 0x005ac750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER0_S3 0x005ac754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER1_S3 0x005ac758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER2_S3 0x005ac75c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER3_S3 0x005ac760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005ac764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005ac768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005ac76c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005ac770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005ac774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005ac778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005ac77c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005ac780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005ac784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005ac788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005ac78c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005ac790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005ac794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005ac798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005ac79c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005ac7a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005ac7a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005ac7a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005ac7ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005ac7b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005ac7b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005ac7b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005ac7bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005ac7c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005ac7c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1 0x005ac800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005aca00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005aca04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0 0x005aca08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5 0x005aca0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1 0x005aca10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2 0x005aca14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3 0x005aca18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4 0x005aca1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL 0x005aca20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL 0x005aca24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL 0x005aca28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL 0x005aca2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL 0x005aca30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL 0x005aca34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL 0x005aca38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL 0x005aca3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005aca40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005aca44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL 0x005aca48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005acb00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005acb04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005acb08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005acb0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1 0x005acb10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER4 0x005acb14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER5 0x005acb18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER6 0x005acb1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER7 0x005acb20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER0_S0 0x005acb24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER1_S0 0x005acb28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER2_S0 0x005acb2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER3_S0 0x005acb30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER0_S1 0x005acb34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER1_S1 0x005acb38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER2_S1 0x005acb3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER3_S1 0x005acb40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER0_S2 0x005acb44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER1_S2 0x005acb48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER2_S2 0x005acb4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER3_S2 0x005acb50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER0_S3 0x005acb54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER1_S3 0x005acb58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER2_S3 0x005acb5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER3_S3 0x005acb60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005acb64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005acb68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005acb6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005acb70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005acb74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005acb78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005acb7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005acb80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005acb84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005acb88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005acb8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005acb90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005acb94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005acb98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005acb9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005acba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005acba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005acba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005acbac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005acbb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005acbb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005acbb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005acbbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005acbc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005acbc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005ace00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005ace04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005ace08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005ace0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1 0x005ace10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER4 0x005ace14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER5 0x005ace18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER6 0x005ace1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER7 0x005ace20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER0_S0 0x005ace24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER1_S0 0x005ace28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER2_S0 0x005ace2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER3_S0 0x005ace30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER0_S1 0x005ace34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER1_S1 0x005ace38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER2_S1 0x005ace3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER3_S1 0x005ace40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER0_S2 0x005ace44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER1_S2 0x005ace48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER2_S2 0x005ace4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER3_S2 0x005ace50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER0_S3 0x005ace54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER1_S3 0x005ace58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER2_S3 0x005ace5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER3_S3 0x005ace60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005ace64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005ace68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005ace6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005ace70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005ace74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005ace78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005ace7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005ace80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005ace84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005ace88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005ace8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005ace90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005ace94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005ace98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005ace9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005acea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005acea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005acea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005aceac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005aceb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005aceb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005aceb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005acebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005acec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005acec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005acf00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005acf04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005acf08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005acf0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1 0x005acf10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER4 0x005acf14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER5 0x005acf18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER6 0x005acf1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER7 0x005acf20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER0_S0 0x005acf24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER1_S0 0x005acf28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER2_S0 0x005acf2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER3_S0 0x005acf30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER0_S1 0x005acf34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER1_S1 0x005acf38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER2_S1 0x005acf3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER3_S1 0x005acf40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER0_S2 0x005acf44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER1_S2 0x005acf48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER2_S2 0x005acf4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER3_S2 0x005acf50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER0_S3 0x005acf54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER1_S3 0x005acf58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER2_S3 0x005acf5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER3_S3 0x005acf60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005acf64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005acf68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005acf6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005acf70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005acf74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005acf78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005acf7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005acf80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005acf84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005acf88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005acf8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005acf90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005acf94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005acf98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005acf9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005acfa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005acfa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005acfa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005acfac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005acfb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005acfb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005acfb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005acfbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005acfc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005acfc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2 0x005ad000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005ad200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005ad204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0 0x005ad208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5 0x005ad20c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1 0x005ad210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2 0x005ad214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3 0x005ad218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4 0x005ad21c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL 0x005ad220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL 0x005ad224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL 0x005ad228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL 0x005ad22c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL 0x005ad230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL 0x005ad234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL 0x005ad238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL 0x005ad23c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005ad240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005ad244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL 0x005ad248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005ad300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005ad304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005ad308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005ad30c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1 0x005ad310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER4 0x005ad314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER5 0x005ad318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER6 0x005ad31c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER7 0x005ad320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER0_S0 0x005ad324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER1_S0 0x005ad328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER2_S0 0x005ad32c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER3_S0 0x005ad330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER0_S1 0x005ad334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER1_S1 0x005ad338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER2_S1 0x005ad33c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER3_S1 0x005ad340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER0_S2 0x005ad344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER1_S2 0x005ad348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER2_S2 0x005ad34c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER3_S2 0x005ad350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER0_S3 0x005ad354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER1_S3 0x005ad358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER2_S3 0x005ad35c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER3_S3 0x005ad360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005ad364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005ad368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005ad36c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005ad370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005ad374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005ad378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005ad37c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005ad380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005ad384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005ad388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005ad38c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005ad390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005ad394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005ad398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005ad39c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005ad3a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005ad3a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005ad3a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005ad3ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005ad3b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005ad3b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005ad3b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005ad3bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005ad3c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005ad3c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005ad600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005ad604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005ad608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005ad60c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1 0x005ad610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER4 0x005ad614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER5 0x005ad618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER6 0x005ad61c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER7 0x005ad620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER0_S0 0x005ad624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER1_S0 0x005ad628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER2_S0 0x005ad62c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER3_S0 0x005ad630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER0_S1 0x005ad634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER1_S1 0x005ad638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER2_S1 0x005ad63c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER3_S1 0x005ad640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER0_S2 0x005ad644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER1_S2 0x005ad648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER2_S2 0x005ad64c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER3_S2 0x005ad650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER0_S3 0x005ad654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER1_S3 0x005ad658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER2_S3 0x005ad65c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER3_S3 0x005ad660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005ad664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005ad668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005ad66c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005ad670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005ad674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005ad678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005ad67c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005ad680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005ad684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005ad688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005ad68c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005ad690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005ad694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005ad698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005ad69c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005ad6a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005ad6a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005ad6a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005ad6ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005ad6b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005ad6b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005ad6b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005ad6bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005ad6c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005ad6c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005ad700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005ad704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005ad708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005ad70c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1 0x005ad710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER4 0x005ad714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER5 0x005ad718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER6 0x005ad71c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER7 0x005ad720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER0_S0 0x005ad724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER1_S0 0x005ad728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER2_S0 0x005ad72c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER3_S0 0x005ad730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER0_S1 0x005ad734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER1_S1 0x005ad738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER2_S1 0x005ad73c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER3_S1 0x005ad740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER0_S2 0x005ad744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER1_S2 0x005ad748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER2_S2 0x005ad74c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER3_S2 0x005ad750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER0_S3 0x005ad754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER1_S3 0x005ad758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER2_S3 0x005ad75c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER3_S3 0x005ad760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005ad764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005ad768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005ad76c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005ad770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005ad774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005ad778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005ad77c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005ad780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005ad784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005ad788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005ad78c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005ad790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005ad794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005ad798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005ad79c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005ad7a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005ad7a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005ad7a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005ad7ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005ad7b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005ad7b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005ad7b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005ad7bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005ad7c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005ad7c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3 0x005ad800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005ada00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005ada04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0 0x005ada08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5 0x005ada0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1 0x005ada10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2 0x005ada14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3 0x005ada18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4 0x005ada1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL 0x005ada20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL 0x005ada24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL 0x005ada28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL 0x005ada2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL 0x005ada30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL 0x005ada34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL 0x005ada38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL 0x005ada3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005ada40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005ada44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL 0x005ada48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005adb00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005adb04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005adb08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005adb0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1 0x005adb10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER4 0x005adb14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER5 0x005adb18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER6 0x005adb1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER7 0x005adb20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER0_S0 0x005adb24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER1_S0 0x005adb28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER2_S0 0x005adb2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER3_S0 0x005adb30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER0_S1 0x005adb34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER1_S1 0x005adb38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER2_S1 0x005adb3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER3_S1 0x005adb40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER0_S2 0x005adb44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER1_S2 0x005adb48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER2_S2 0x005adb4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER3_S2 0x005adb50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER0_S3 0x005adb54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER1_S3 0x005adb58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER2_S3 0x005adb5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER3_S3 0x005adb60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005adb64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005adb68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005adb6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005adb70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005adb74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005adb78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005adb7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005adb80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005adb84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005adb88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005adb8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005adb90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005adb94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005adb98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005adb9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005adba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005adba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005adba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005adbac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005adbb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005adbb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005adbb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005adbbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005adbc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005adbc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005ade00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005ade04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005ade08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005ade0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1 0x005ade10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER4 0x005ade14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER5 0x005ade18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER6 0x005ade1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER7 0x005ade20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER0_S0 0x005ade24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER1_S0 0x005ade28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER2_S0 0x005ade2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER3_S0 0x005ade30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER0_S1 0x005ade34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER1_S1 0x005ade38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER2_S1 0x005ade3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER3_S1 0x005ade40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER0_S2 0x005ade44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER1_S2 0x005ade48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER2_S2 0x005ade4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER3_S2 0x005ade50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER0_S3 0x005ade54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER1_S3 0x005ade58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER2_S3 0x005ade5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER3_S3 0x005ade60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005ade64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005ade68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005ade6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005ade70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005ade74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005ade78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005ade7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005ade80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005ade84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005ade88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005ade8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005ade90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005ade94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005ade98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005ade9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005adea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005adea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005adea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005adeac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005adeb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005adeb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005adeb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005adebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005adec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005adec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005adf00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005adf04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005adf08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005adf0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1 0x005adf10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER4 0x005adf14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER5 0x005adf18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER6 0x005adf1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER7 0x005adf20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER0_S0 0x005adf24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER1_S0 0x005adf28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER2_S0 0x005adf2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER3_S0 0x005adf30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER0_S1 0x005adf34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER1_S1 0x005adf38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER2_S1 0x005adf3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER3_S1 0x005adf40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER0_S2 0x005adf44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER1_S2 0x005adf48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER2_S2 0x005adf4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER3_S2 0x005adf50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER0_S3 0x005adf54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER1_S3 0x005adf58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER2_S3 0x005adf5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER3_S3 0x005adf60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005adf64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005adf68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005adf6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005adf70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005adf74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005adf78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005adf7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005adf80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005adf84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005adf88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005adf8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005adf90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005adf94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005adf98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005adf9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005adfa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005adfa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005adfa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005adfac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005adfb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005adfb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005adfb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005adfbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005adfc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005adfc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4 0x005ae000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005ae200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005ae204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0 0x005ae208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5 0x005ae20c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1 0x005ae210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2 0x005ae214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3 0x005ae218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4 0x005ae21c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL 0x005ae220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL 0x005ae224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL 0x005ae228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL 0x005ae22c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL 0x005ae230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL 0x005ae234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL 0x005ae238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL 0x005ae23c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005ae240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005ae244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL 0x005ae248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005ae300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005ae304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005ae308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005ae30c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1 0x005ae310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER4 0x005ae314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER5 0x005ae318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER6 0x005ae31c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER7 0x005ae320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER0_S0 0x005ae324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER1_S0 0x005ae328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER2_S0 0x005ae32c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER3_S0 0x005ae330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER0_S1 0x005ae334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER1_S1 0x005ae338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER2_S1 0x005ae33c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER3_S1 0x005ae340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER0_S2 0x005ae344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER1_S2 0x005ae348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER2_S2 0x005ae34c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER3_S2 0x005ae350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER0_S3 0x005ae354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER1_S3 0x005ae358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER2_S3 0x005ae35c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER3_S3 0x005ae360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005ae364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005ae368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005ae36c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005ae370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005ae374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005ae378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005ae37c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005ae380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005ae384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005ae388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005ae38c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005ae390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005ae394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005ae398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005ae39c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005ae3a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005ae3a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005ae3a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005ae3ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005ae3b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005ae3b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005ae3b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005ae3bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005ae3c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005ae3c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005ae600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005ae604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005ae608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005ae60c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1 0x005ae610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER4 0x005ae614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER5 0x005ae618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER6 0x005ae61c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER7 0x005ae620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER0_S0 0x005ae624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER1_S0 0x005ae628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER2_S0 0x005ae62c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER3_S0 0x005ae630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER0_S1 0x005ae634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER1_S1 0x005ae638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER2_S1 0x005ae63c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER3_S1 0x005ae640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER0_S2 0x005ae644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER1_S2 0x005ae648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER2_S2 0x005ae64c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER3_S2 0x005ae650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER0_S3 0x005ae654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER1_S3 0x005ae658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER2_S3 0x005ae65c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER3_S3 0x005ae660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005ae664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005ae668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005ae66c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005ae670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005ae674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005ae678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005ae67c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005ae680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005ae684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005ae688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005ae68c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005ae690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005ae694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005ae698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005ae69c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005ae6a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005ae6a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005ae6a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005ae6ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005ae6b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005ae6b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005ae6b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005ae6bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005ae6c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005ae6c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005ae700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005ae704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005ae708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005ae70c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1 0x005ae710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER4 0x005ae714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER5 0x005ae718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER6 0x005ae71c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER7 0x005ae720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER0_S0 0x005ae724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER1_S0 0x005ae728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER2_S0 0x005ae72c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER3_S0 0x005ae730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER0_S1 0x005ae734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER1_S1 0x005ae738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER2_S1 0x005ae73c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER3_S1 0x005ae740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER0_S2 0x005ae744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER1_S2 0x005ae748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER2_S2 0x005ae74c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER3_S2 0x005ae750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER0_S3 0x005ae754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER1_S3 0x005ae758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER2_S3 0x005ae75c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER3_S3 0x005ae760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005ae764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005ae768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005ae76c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005ae770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005ae774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005ae778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005ae77c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005ae780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005ae784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005ae788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005ae78c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005ae790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005ae794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005ae798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005ae79c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005ae7a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005ae7a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005ae7a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005ae7ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005ae7b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005ae7b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005ae7b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005ae7bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005ae7c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005ae7c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5 0x005ae800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005aea00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005aea04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0 0x005aea08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5 0x005aea0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1 0x005aea10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2 0x005aea14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3 0x005aea18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4 0x005aea1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL 0x005aea20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL 0x005aea24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL 0x005aea28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL 0x005aea2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL 0x005aea30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL 0x005aea34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL 0x005aea38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL 0x005aea3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005aea40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005aea44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL 0x005aea48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005aeb00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005aeb04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005aeb08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005aeb0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1 0x005aeb10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER4 0x005aeb14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER5 0x005aeb18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER6 0x005aeb1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER7 0x005aeb20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER0_S0 0x005aeb24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER1_S0 0x005aeb28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER2_S0 0x005aeb2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER3_S0 0x005aeb30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER0_S1 0x005aeb34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER1_S1 0x005aeb38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER2_S1 0x005aeb3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER3_S1 0x005aeb40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER0_S2 0x005aeb44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER1_S2 0x005aeb48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER2_S2 0x005aeb4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER3_S2 0x005aeb50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER0_S3 0x005aeb54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER1_S3 0x005aeb58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER2_S3 0x005aeb5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER3_S3 0x005aeb60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005aeb64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005aeb68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005aeb6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005aeb70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005aeb74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005aeb78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005aeb7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005aeb80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005aeb84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005aeb88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005aeb8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005aeb90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005aeb94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005aeb98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005aeb9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005aeba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005aeba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005aeba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005aebac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005aebb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005aebb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005aebb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005aebbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005aebc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005aebc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005aee00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005aee04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005aee08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005aee0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1 0x005aee10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER4 0x005aee14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER5 0x005aee18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER6 0x005aee1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER7 0x005aee20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER0_S0 0x005aee24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER1_S0 0x005aee28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER2_S0 0x005aee2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER3_S0 0x005aee30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER0_S1 0x005aee34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER1_S1 0x005aee38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER2_S1 0x005aee3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER3_S1 0x005aee40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER0_S2 0x005aee44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER1_S2 0x005aee48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER2_S2 0x005aee4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER3_S2 0x005aee50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER0_S3 0x005aee54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER1_S3 0x005aee58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER2_S3 0x005aee5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER3_S3 0x005aee60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005aee64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005aee68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005aee6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005aee70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005aee74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005aee78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005aee7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005aee80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005aee84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005aee88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005aee8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005aee90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005aee94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005aee98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005aee9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005aeea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005aeea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005aeea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005aeeac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005aeeb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005aeeb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005aeeb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005aeebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005aeec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005aeec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005aef00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005aef04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005aef08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005aef0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1 0x005aef10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER4 0x005aef14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER5 0x005aef18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER6 0x005aef1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER7 0x005aef20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER0_S0 0x005aef24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER1_S0 0x005aef28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER2_S0 0x005aef2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER3_S0 0x005aef30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER0_S1 0x005aef34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER1_S1 0x005aef38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER2_S1 0x005aef3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER3_S1 0x005aef40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER0_S2 0x005aef44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER1_S2 0x005aef48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER2_S2 0x005aef4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER3_S2 0x005aef50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER0_S3 0x005aef54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER1_S3 0x005aef58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER2_S3 0x005aef5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER3_S3 0x005aef60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005aef64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005aef68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005aef6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005aef70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005aef74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005aef78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005aef7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005aef80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005aef84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005aef88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005aef8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005aef90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005aef94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005aef98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005aef9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005aefa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005aefa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005aefa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005aefac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005aefb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005aefb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005aefb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005aefbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005aefc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005aefc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS 0x005a9800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005a9a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005a9a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0 0x005a9a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5 0x005a9a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1 0x005a9a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2 0x005a9a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3 0x005a9a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4 0x005a9a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL 0x005a9a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL 0x005a9a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL 0x005a9a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL 0x005a9a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL 0x005a9a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL 0x005a9a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL 0x005a9a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL 0x005a9a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005a9a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005a9a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL 0x005a9a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005a9b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005a9b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005a9b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005a9b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1 0x005a9b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER4 0x005a9b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER5 0x005a9b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER6 0x005a9b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER7 0x005a9b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER0_S0 0x005a9b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER1_S0 0x005a9b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER2_S0 0x005a9b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER3_S0 0x005a9b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER0_S1 0x005a9b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER1_S1 0x005a9b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER2_S1 0x005a9b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER3_S1 0x005a9b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER0_S2 0x005a9b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER1_S2 0x005a9b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER2_S2 0x005a9b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER3_S2 0x005a9b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER0_S3 0x005a9b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER1_S3 0x005a9b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER2_S3 0x005a9b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER3_S3 0x005a9b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a9b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a9b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a9b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a9b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a9b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005a9b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005a9b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005a9b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005a9b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a9b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a9b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a9b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a9b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a9b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a9b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a9ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a9ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a9ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a9bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a9bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a9bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a9bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a9bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a9bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a9bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005a9e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005a9e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005a9e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005a9e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1 0x005a9e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER4 0x005a9e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER5 0x005a9e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER6 0x005a9e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER7 0x005a9e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER0_S0 0x005a9e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER1_S0 0x005a9e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER2_S0 0x005a9e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER3_S0 0x005a9e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER0_S1 0x005a9e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER1_S1 0x005a9e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER2_S1 0x005a9e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER3_S1 0x005a9e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER0_S2 0x005a9e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER1_S2 0x005a9e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER2_S2 0x005a9e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER3_S2 0x005a9e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER0_S3 0x005a9e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER1_S3 0x005a9e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER2_S3 0x005a9e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER3_S3 0x005a9e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a9e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a9e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a9e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a9e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a9e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005a9e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005a9e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005a9e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005a9e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a9e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a9e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a9e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a9e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a9e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a9e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a9ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a9ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a9ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a9eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a9eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a9eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a9eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a9ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a9ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a9ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005a9f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005a9f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005a9f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005a9f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1 0x005a9f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER4 0x005a9f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER5 0x005a9f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER6 0x005a9f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER7 0x005a9f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER0_S0 0x005a9f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER1_S0 0x005a9f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER2_S0 0x005a9f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER3_S0 0x005a9f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER0_S1 0x005a9f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER1_S1 0x005a9f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER2_S1 0x005a9f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER3_S1 0x005a9f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER0_S2 0x005a9f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER1_S2 0x005a9f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER2_S2 0x005a9f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER3_S2 0x005a9f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER0_S3 0x005a9f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER1_S3 0x005a9f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER2_S3 0x005a9f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER3_S3 0x005a9f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005a9f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005a9f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005a9f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005a9f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005a9f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005a9f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005a9f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005a9f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005a9f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005a9f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005a9f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005a9f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005a9f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005a9f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005a9f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005a9fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005a9fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005a9fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005a9fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005a9fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005a9fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005a9fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005a9fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005a9fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005a9fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC5_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6 0x005b0000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC6_ETPC0 0x005b4000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005b4200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005b4204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x005b4208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x005b420c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x005b4210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x005b4214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x005b4218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x005b421c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x005b4220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x005b4224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x005b4228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x005b422c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x005b4230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x005b4234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x005b4238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x005b423c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005b4240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005b4244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL 0x005b4248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005b4300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005b4304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005b4308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005b430c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1 0x005b4310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER4 0x005b4314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER5 0x005b4318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER6 0x005b431c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER7 0x005b4320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER0_S0 0x005b4324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER1_S0 0x005b4328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER2_S0 0x005b432c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER3_S0 0x005b4330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER0_S1 0x005b4334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER1_S1 0x005b4338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER2_S1 0x005b433c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER3_S1 0x005b4340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER0_S2 0x005b4344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER1_S2 0x005b4348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER2_S2 0x005b434c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER3_S2 0x005b4350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER0_S3 0x005b4354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER1_S3 0x005b4358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER2_S3 0x005b435c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER3_S3 0x005b4360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b4364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b4368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b436c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b4370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b4374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005b4378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005b437c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005b4380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005b4384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b4388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b438c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b4390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b4394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b4398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b439c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b43a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b43a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b43a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b43ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b43b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b43b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b43b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b43bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b43c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b43c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005b4600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005b4604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005b4608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005b460c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1 0x005b4610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER4 0x005b4614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER5 0x005b4618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER6 0x005b461c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER7 0x005b4620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER0_S0 0x005b4624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER1_S0 0x005b4628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER2_S0 0x005b462c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER3_S0 0x005b4630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER0_S1 0x005b4634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER1_S1 0x005b4638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER2_S1 0x005b463c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER3_S1 0x005b4640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER0_S2 0x005b4644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER1_S2 0x005b4648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER2_S2 0x005b464c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER3_S2 0x005b4650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER0_S3 0x005b4654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER1_S3 0x005b4658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER2_S3 0x005b465c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER3_S3 0x005b4660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b4664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b4668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b466c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b4670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b4674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005b4678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005b467c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005b4680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005b4684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b4688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b468c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b4690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b4694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b4698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b469c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b46a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b46a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b46a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b46ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b46b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b46b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b46b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b46bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b46c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b46c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005b4700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005b4704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005b4708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005b470c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1 0x005b4710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER4 0x005b4714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER5 0x005b4718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER6 0x005b471c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER7 0x005b4720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER0_S0 0x005b4724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER1_S0 0x005b4728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER2_S0 0x005b472c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER3_S0 0x005b4730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER0_S1 0x005b4734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER1_S1 0x005b4738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER2_S1 0x005b473c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER3_S1 0x005b4740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER0_S2 0x005b4744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER1_S2 0x005b4748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER2_S2 0x005b474c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER3_S2 0x005b4750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER0_S3 0x005b4754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER1_S3 0x005b4758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER2_S3 0x005b475c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER3_S3 0x005b4760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b4764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b4768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b476c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b4770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b4774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005b4778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005b477c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005b4780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005b4784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b4788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b478c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b4790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b4794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b4798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b479c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b47a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b47a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b47a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b47ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b47b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b47b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b47b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b47bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b47c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b47c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1 0x005b4800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005b4a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005b4a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0 0x005b4a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5 0x005b4a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1 0x005b4a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2 0x005b4a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3 0x005b4a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4 0x005b4a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL 0x005b4a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL 0x005b4a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL 0x005b4a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL 0x005b4a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL 0x005b4a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL 0x005b4a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL 0x005b4a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL 0x005b4a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005b4a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005b4a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL 0x005b4a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005b4b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005b4b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005b4b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005b4b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1 0x005b4b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER4 0x005b4b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER5 0x005b4b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER6 0x005b4b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER7 0x005b4b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER0_S0 0x005b4b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER1_S0 0x005b4b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER2_S0 0x005b4b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER3_S0 0x005b4b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER0_S1 0x005b4b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER1_S1 0x005b4b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER2_S1 0x005b4b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER3_S1 0x005b4b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER0_S2 0x005b4b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER1_S2 0x005b4b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER2_S2 0x005b4b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER3_S2 0x005b4b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER0_S3 0x005b4b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER1_S3 0x005b4b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER2_S3 0x005b4b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER3_S3 0x005b4b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b4b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b4b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b4b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b4b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b4b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005b4b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005b4b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005b4b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005b4b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b4b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b4b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b4b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b4b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b4b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b4b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b4ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b4ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b4ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b4bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b4bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b4bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b4bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b4bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b4bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b4bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005b4e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005b4e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005b4e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005b4e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1 0x005b4e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER4 0x005b4e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER5 0x005b4e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER6 0x005b4e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER7 0x005b4e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER0_S0 0x005b4e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER1_S0 0x005b4e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER2_S0 0x005b4e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER3_S0 0x005b4e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER0_S1 0x005b4e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER1_S1 0x005b4e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER2_S1 0x005b4e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER3_S1 0x005b4e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER0_S2 0x005b4e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER1_S2 0x005b4e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER2_S2 0x005b4e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER3_S2 0x005b4e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER0_S3 0x005b4e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER1_S3 0x005b4e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER2_S3 0x005b4e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER3_S3 0x005b4e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b4e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b4e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b4e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b4e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b4e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005b4e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005b4e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005b4e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005b4e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b4e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b4e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b4e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b4e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b4e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b4e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b4ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b4ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b4ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b4eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b4eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b4eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b4eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b4ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b4ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b4ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005b4f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005b4f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005b4f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005b4f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1 0x005b4f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER4 0x005b4f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER5 0x005b4f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER6 0x005b4f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER7 0x005b4f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER0_S0 0x005b4f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER1_S0 0x005b4f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER2_S0 0x005b4f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER3_S0 0x005b4f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER0_S1 0x005b4f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER1_S1 0x005b4f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER2_S1 0x005b4f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER3_S1 0x005b4f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER0_S2 0x005b4f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER1_S2 0x005b4f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER2_S2 0x005b4f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER3_S2 0x005b4f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER0_S3 0x005b4f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER1_S3 0x005b4f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER2_S3 0x005b4f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER3_S3 0x005b4f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b4f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b4f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b4f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b4f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b4f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005b4f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005b4f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005b4f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005b4f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b4f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b4f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b4f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b4f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b4f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b4f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b4fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b4fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b4fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b4fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b4fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b4fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b4fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b4fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b4fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b4fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2 0x005b5000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005b5200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005b5204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0 0x005b5208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5 0x005b520c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1 0x005b5210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2 0x005b5214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3 0x005b5218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4 0x005b521c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL 0x005b5220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL 0x005b5224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL 0x005b5228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL 0x005b522c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL 0x005b5230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL 0x005b5234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL 0x005b5238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL 0x005b523c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005b5240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005b5244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL 0x005b5248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005b5300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005b5304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005b5308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005b530c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1 0x005b5310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER4 0x005b5314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER5 0x005b5318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER6 0x005b531c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER7 0x005b5320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER0_S0 0x005b5324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER1_S0 0x005b5328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER2_S0 0x005b532c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER3_S0 0x005b5330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER0_S1 0x005b5334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER1_S1 0x005b5338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER2_S1 0x005b533c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER3_S1 0x005b5340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER0_S2 0x005b5344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER1_S2 0x005b5348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER2_S2 0x005b534c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER3_S2 0x005b5350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER0_S3 0x005b5354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER1_S3 0x005b5358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER2_S3 0x005b535c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER3_S3 0x005b5360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b5364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b5368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b536c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b5370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b5374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005b5378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005b537c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005b5380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005b5384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b5388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b538c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b5390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b5394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b5398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b539c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b53a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b53a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b53a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b53ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b53b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b53b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b53b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b53bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b53c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b53c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005b5600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005b5604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005b5608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005b560c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1 0x005b5610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER4 0x005b5614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER5 0x005b5618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER6 0x005b561c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER7 0x005b5620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER0_S0 0x005b5624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER1_S0 0x005b5628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER2_S0 0x005b562c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER3_S0 0x005b5630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER0_S1 0x005b5634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER1_S1 0x005b5638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER2_S1 0x005b563c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER3_S1 0x005b5640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER0_S2 0x005b5644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER1_S2 0x005b5648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER2_S2 0x005b564c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER3_S2 0x005b5650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER0_S3 0x005b5654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER1_S3 0x005b5658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER2_S3 0x005b565c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER3_S3 0x005b5660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b5664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b5668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b566c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b5670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b5674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005b5678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005b567c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005b5680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005b5684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b5688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b568c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b5690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b5694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b5698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b569c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b56a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b56a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b56a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b56ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b56b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b56b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b56b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b56bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b56c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b56c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005b5700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005b5704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005b5708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005b570c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1 0x005b5710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER4 0x005b5714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER5 0x005b5718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER6 0x005b571c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER7 0x005b5720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER0_S0 0x005b5724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER1_S0 0x005b5728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER2_S0 0x005b572c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER3_S0 0x005b5730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER0_S1 0x005b5734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER1_S1 0x005b5738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER2_S1 0x005b573c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER3_S1 0x005b5740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER0_S2 0x005b5744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER1_S2 0x005b5748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER2_S2 0x005b574c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER3_S2 0x005b5750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER0_S3 0x005b5754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER1_S3 0x005b5758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER2_S3 0x005b575c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER3_S3 0x005b5760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b5764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b5768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b576c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b5770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b5774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005b5778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005b577c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005b5780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005b5784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b5788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b578c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b5790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b5794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b5798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b579c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b57a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b57a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b57a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b57ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b57b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b57b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b57b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b57bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b57c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b57c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3 0x005b5800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005b5a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005b5a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0 0x005b5a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5 0x005b5a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1 0x005b5a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2 0x005b5a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3 0x005b5a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4 0x005b5a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL 0x005b5a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL 0x005b5a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL 0x005b5a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL 0x005b5a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL 0x005b5a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL 0x005b5a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL 0x005b5a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL 0x005b5a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005b5a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005b5a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL 0x005b5a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005b5b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005b5b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005b5b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005b5b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1 0x005b5b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER4 0x005b5b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER5 0x005b5b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER6 0x005b5b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER7 0x005b5b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER0_S0 0x005b5b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER1_S0 0x005b5b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER2_S0 0x005b5b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER3_S0 0x005b5b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER0_S1 0x005b5b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER1_S1 0x005b5b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER2_S1 0x005b5b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER3_S1 0x005b5b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER0_S2 0x005b5b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER1_S2 0x005b5b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER2_S2 0x005b5b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER3_S2 0x005b5b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER0_S3 0x005b5b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER1_S3 0x005b5b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER2_S3 0x005b5b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER3_S3 0x005b5b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b5b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b5b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b5b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b5b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b5b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005b5b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005b5b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005b5b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005b5b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b5b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b5b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b5b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b5b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b5b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b5b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b5ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b5ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b5ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b5bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b5bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b5bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b5bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b5bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b5bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b5bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005b5e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005b5e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005b5e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005b5e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1 0x005b5e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER4 0x005b5e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER5 0x005b5e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER6 0x005b5e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER7 0x005b5e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER0_S0 0x005b5e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER1_S0 0x005b5e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER2_S0 0x005b5e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER3_S0 0x005b5e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER0_S1 0x005b5e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER1_S1 0x005b5e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER2_S1 0x005b5e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER3_S1 0x005b5e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER0_S2 0x005b5e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER1_S2 0x005b5e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER2_S2 0x005b5e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER3_S2 0x005b5e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER0_S3 0x005b5e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER1_S3 0x005b5e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER2_S3 0x005b5e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER3_S3 0x005b5e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b5e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b5e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b5e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b5e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b5e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005b5e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005b5e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005b5e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005b5e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b5e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b5e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b5e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b5e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b5e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b5e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b5ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b5ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b5ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b5eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b5eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b5eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b5eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b5ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b5ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b5ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005b5f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005b5f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005b5f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005b5f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1 0x005b5f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER4 0x005b5f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER5 0x005b5f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER6 0x005b5f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER7 0x005b5f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER0_S0 0x005b5f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER1_S0 0x005b5f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER2_S0 0x005b5f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER3_S0 0x005b5f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER0_S1 0x005b5f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER1_S1 0x005b5f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER2_S1 0x005b5f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER3_S1 0x005b5f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER0_S2 0x005b5f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER1_S2 0x005b5f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER2_S2 0x005b5f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER3_S2 0x005b5f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER0_S3 0x005b5f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER1_S3 0x005b5f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER2_S3 0x005b5f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER3_S3 0x005b5f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b5f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b5f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b5f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b5f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b5f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005b5f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005b5f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005b5f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005b5f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b5f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b5f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b5f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b5f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b5f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b5f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b5fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b5fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b5fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b5fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b5fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b5fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b5fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b5fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b5fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b5fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4 0x005b6000 /* RW--L */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005b6200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005b6204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0 0x005b6208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5 0x005b620c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1 0x005b6210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2 0x005b6214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3 0x005b6218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4 0x005b621c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL 0x005b6220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL 0x005b6224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL 0x005b6228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL 0x005b622c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL 0x005b6230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL 0x005b6234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL 0x005b6238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL 0x005b623c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005b6240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005b6244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL 0x005b6248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005b6300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005b6304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005b6308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005b630c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1 0x005b6310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER4 0x005b6314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER5 0x005b6318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER6 0x005b631c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER7 0x005b6320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER0_S0 0x005b6324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER1_S0 0x005b6328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER2_S0 0x005b632c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER3_S0 0x005b6330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER0_S1 0x005b6334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER1_S1 0x005b6338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER2_S1 0x005b633c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER3_S1 0x005b6340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER0_S2 0x005b6344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER1_S2 0x005b6348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER2_S2 0x005b634c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER3_S2 0x005b6350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER0_S3 0x005b6354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER1_S3 0x005b6358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER2_S3 0x005b635c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER3_S3 0x005b6360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b6364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b6368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b636c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b6370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b6374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005b6378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005b637c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005b6380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005b6384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b6388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b638c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b6390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b6394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b6398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b639c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b63a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b63a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b63a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b63ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b63b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b63b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b63b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b63bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b63c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b63c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005b6600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005b6604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005b6608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005b660c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1 0x005b6610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER4 0x005b6614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER5 0x005b6618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER6 0x005b661c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER7 0x005b6620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER0_S0 0x005b6624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER1_S0 0x005b6628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER2_S0 0x005b662c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER3_S0 0x005b6630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER0_S1 0x005b6634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER1_S1 0x005b6638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER2_S1 0x005b663c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER3_S1 0x005b6640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER0_S2 0x005b6644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER1_S2 0x005b6648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER2_S2 0x005b664c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER3_S2 0x005b6650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER0_S3 0x005b6654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER1_S3 0x005b6658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER2_S3 0x005b665c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER3_S3 0x005b6660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b6664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b6668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b666c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b6670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b6674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005b6678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005b667c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005b6680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005b6684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b6688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b668c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b6690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b6694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b6698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b669c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b66a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b66a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b66a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b66ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b66b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b66b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b66b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b66bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b66c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b66c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005b6700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005b6704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005b6708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005b670c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1 0x005b6710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER4 0x005b6714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER5 0x005b6718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER6 0x005b671c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER7 0x005b6720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER0_S0 0x005b6724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER1_S0 0x005b6728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER2_S0 0x005b672c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER3_S0 0x005b6730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER0_S1 0x005b6734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER1_S1 0x005b6738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER2_S1 0x005b673c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER3_S1 0x005b6740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER0_S2 0x005b6744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER1_S2 0x005b6748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER2_S2 0x005b674c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER3_S2 0x005b6750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER0_S3 0x005b6754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER1_S3 0x005b6758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER2_S3 0x005b675c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER3_S3 0x005b6760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b6764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b6768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b676c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b6770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b6774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005b6778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005b677c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005b6780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005b6784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b6788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b678c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b6790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b6794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b6798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b679c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b67a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b67a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b67a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b67ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b67b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b67b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b67b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b67bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b67c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b67c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5 0x005b6800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005b6a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005b6a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0 0x005b6a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5 0x005b6a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1 0x005b6a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2 0x005b6a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3 0x005b6a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4 0x005b6a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL 0x005b6a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL 0x005b6a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL 0x005b6a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL 0x005b6a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL 0x005b6a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL 0x005b6a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL 0x005b6a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL 0x005b6a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005b6a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005b6a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL 0x005b6a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005b6b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005b6b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005b6b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005b6b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1 0x005b6b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER4 0x005b6b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER5 0x005b6b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER6 0x005b6b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER7 0x005b6b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER0_S0 0x005b6b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER1_S0 0x005b6b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER2_S0 0x005b6b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER3_S0 0x005b6b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER0_S1 0x005b6b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER1_S1 0x005b6b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER2_S1 0x005b6b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER3_S1 0x005b6b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER0_S2 0x005b6b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER1_S2 0x005b6b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER2_S2 0x005b6b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER3_S2 0x005b6b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER0_S3 0x005b6b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER1_S3 0x005b6b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER2_S3 0x005b6b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER3_S3 0x005b6b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b6b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b6b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b6b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b6b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b6b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005b6b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005b6b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005b6b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005b6b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b6b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b6b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b6b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b6b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b6b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b6b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b6ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b6ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b6ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b6bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b6bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b6bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b6bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b6bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b6bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b6bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005b6e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005b6e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005b6e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005b6e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1 0x005b6e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER4 0x005b6e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER5 0x005b6e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER6 0x005b6e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER7 0x005b6e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER0_S0 0x005b6e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER1_S0 0x005b6e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER2_S0 0x005b6e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER3_S0 0x005b6e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER0_S1 0x005b6e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER1_S1 0x005b6e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER2_S1 0x005b6e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER3_S1 0x005b6e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER0_S2 0x005b6e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER1_S2 0x005b6e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER2_S2 0x005b6e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER3_S2 0x005b6e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER0_S3 0x005b6e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER1_S3 0x005b6e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER2_S3 0x005b6e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER3_S3 0x005b6e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b6e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b6e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b6e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b6e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b6e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005b6e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005b6e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005b6e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005b6e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b6e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b6e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b6e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b6e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b6e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b6e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b6ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b6ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b6ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b6eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b6eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b6eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b6eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b6ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b6ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b6ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005b6f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005b6f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005b6f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005b6f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1 0x005b6f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER4 0x005b6f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER5 0x005b6f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER6 0x005b6f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER7 0x005b6f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER0_S0 0x005b6f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER1_S0 0x005b6f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER2_S0 0x005b6f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER3_S0 0x005b6f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER0_S1 0x005b6f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER1_S1 0x005b6f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER2_S1 0x005b6f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER3_S1 0x005b6f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER0_S2 0x005b6f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER1_S2 0x005b6f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER2_S2 0x005b6f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER3_S2 0x005b6f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER0_S3 0x005b6f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER1_S3 0x005b6f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER2_S3 0x005b6f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER3_S3 0x005b6f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b6f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b6f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b6f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b6f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b6f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005b6f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005b6f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005b6f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005b6f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b6f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b6f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b6f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b6f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b6f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b6f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b6fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b6fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b6fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b6fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b6fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b6fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b6fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b6fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b6fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b6fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS 0x005b1800 /* RW--L */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x005b1a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x005b1a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0 0x005b1a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5 0x005b1a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1 0x005b1a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2 0x005b1a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3 0x005b1a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4 0x005b1a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL 0x005b1a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL 0x005b1a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL 0x005b1a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL 0x005b1a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL 0x005b1a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL 0x005b1a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL 0x005b1a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL 0x005b1a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x005b1a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x005b1a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL 0x005b1a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0 0x005b1b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1 0x005b1b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2 0x005b1b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3 0x005b1b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1 0x005b1b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER4 0x005b1b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER5 0x005b1b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER6 0x005b1b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER7 0x005b1b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER0_S0 0x005b1b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER1_S0 0x005b1b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER2_S0 0x005b1b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER3_S0 0x005b1b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER0_S1 0x005b1b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER1_S1 0x005b1b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER2_S1 0x005b1b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER3_S1 0x005b1b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER0_S2 0x005b1b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER1_S2 0x005b1b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER2_S2 0x005b1b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER3_S2 0x005b1b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER0_S3 0x005b1b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER1_S3 0x005b1b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER2_S3 0x005b1b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER3_S3 0x005b1b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b1b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b1b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b1b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b1b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b1b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x005b1b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x005b1b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x005b1b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x005b1b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b1b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b1b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b1b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b1b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b1b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b1b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b1ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b1ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b1ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b1bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b1bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b1bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b1bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b1bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b1bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b1bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0 0x005b1e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1 0x005b1e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2 0x005b1e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3 0x005b1e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1 0x005b1e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER4 0x005b1e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER5 0x005b1e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER6 0x005b1e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER7 0x005b1e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER0_S0 0x005b1e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER1_S0 0x005b1e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER2_S0 0x005b1e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER3_S0 0x005b1e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER0_S1 0x005b1e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER1_S1 0x005b1e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER2_S1 0x005b1e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER3_S1 0x005b1e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER0_S2 0x005b1e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER1_S2 0x005b1e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER2_S2 0x005b1e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER3_S2 0x005b1e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER0_S3 0x005b1e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER1_S3 0x005b1e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER2_S3 0x005b1e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER3_S3 0x005b1e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b1e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b1e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b1e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b1e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b1e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x005b1e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x005b1e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x005b1e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x005b1e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b1e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b1e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b1e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b1e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b1e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b1e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b1ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b1ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b1ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b1eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b1eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b1eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b1eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b1ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b1ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b1ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0 0x005b1f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1 0x005b1f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2 0x005b1f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3 0x005b1f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1 0x005b1f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER4 0x005b1f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER5 0x005b1f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER6 0x005b1f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER7 0x005b1f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER0_S0 0x005b1f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER1_S0 0x005b1f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER2_S0 0x005b1f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER3_S0 0x005b1f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER0_S1 0x005b1f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER1_S1 0x005b1f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER2_S1 0x005b1f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER3_S1 0x005b1f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER0_S2 0x005b1f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER1_S2 0x005b1f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER2_S2 0x005b1f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER3_S2 0x005b1f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER0_S3 0x005b1f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER1_S3 0x005b1f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER2_S3 0x005b1f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER3_S3 0x005b1f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x005b1f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x005b1f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x005b1f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x005b1f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x005b1f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x005b1f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x005b1f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x005b1f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x005b1f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x005b1f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x005b1f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x005b1f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x005b1f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x005b1f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x005b1f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x005b1fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x005b1fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x005b1fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x005b1fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x005b1fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x005b1fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x005b1fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x005b1fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x005b1fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x005b1fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPC6_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS 0x00480000 /* RW--L */ #define NV_PGRAPH_PRI_EGPCS_ETPC0 0x00484000 /* RW--L */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00484200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00484204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x00484208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x0048420c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x00484210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x00484214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x00484218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x0048421c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x00484220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x00484224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x00484228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x0048422c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x00484230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x00484234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x00484238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x0048423c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00484240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00484244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL 0x00484248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00484300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00484304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00484308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0048430c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1 0x00484310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER4 0x00484314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER5 0x00484318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER6 0x0048431c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER7 0x00484320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER0_S0 0x00484324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER1_S0 0x00484328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER2_S0 0x0048432c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER3_S0 0x00484330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER0_S1 0x00484334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER1_S1 0x00484338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER2_S1 0x0048433c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER3_S1 0x00484340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER0_S2 0x00484344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER1_S2 0x00484348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER2_S2 0x0048434c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER3_S2 0x00484350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER0_S3 0x00484354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER1_S3 0x00484358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER2_S3 0x0048435c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER3_S3 0x00484360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00484364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00484368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0048436c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00484370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00484374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00484378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0048437c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00484380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00484384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00484388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0048438c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00484390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00484394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00484398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0048439c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x004843a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x004843a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x004843a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x004843ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x004843b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x004843b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x004843b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x004843bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x004843c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x004843c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00484600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00484604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00484608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0048460c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1 0x00484610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER4 0x00484614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER5 0x00484618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER6 0x0048461c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER7 0x00484620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER0_S0 0x00484624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER1_S0 0x00484628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER2_S0 0x0048462c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER3_S0 0x00484630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER0_S1 0x00484634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER1_S1 0x00484638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER2_S1 0x0048463c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER3_S1 0x00484640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER0_S2 0x00484644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER1_S2 0x00484648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER2_S2 0x0048464c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER3_S2 0x00484650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER0_S3 0x00484654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER1_S3 0x00484658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER2_S3 0x0048465c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER3_S3 0x00484660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00484664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00484668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0048466c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00484670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00484674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00484678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0048467c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00484680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00484684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00484688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0048468c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00484690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00484694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00484698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0048469c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x004846a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x004846a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x004846a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x004846ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x004846b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x004846b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x004846b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x004846bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x004846c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x004846c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00484700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00484704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00484708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0048470c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1 0x00484710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER4 0x00484714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER5 0x00484718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER6 0x0048471c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER7 0x00484720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER0_S0 0x00484724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER1_S0 0x00484728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER2_S0 0x0048472c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER3_S0 0x00484730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER0_S1 0x00484734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER1_S1 0x00484738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER2_S1 0x0048473c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER3_S1 0x00484740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER0_S2 0x00484744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER1_S2 0x00484748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER2_S2 0x0048474c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER3_S2 0x00484750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER0_S3 0x00484754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER1_S3 0x00484758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER2_S3 0x0048475c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER3_S3 0x00484760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00484764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00484768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0048476c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00484770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00484774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00484778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0048477c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00484780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00484784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00484788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0048478c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00484790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00484794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00484798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0048479c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x004847a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x004847a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x004847a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x004847ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x004847b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x004847b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x004847b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x004847bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x004847c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x004847c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC0_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1 0x00484800 /* RW--L */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00484a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00484a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0 0x00484a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5 0x00484a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1 0x00484a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2 0x00484a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3 0x00484a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4 0x00484a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL 0x00484a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL 0x00484a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL 0x00484a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL 0x00484a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL 0x00484a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL 0x00484a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL 0x00484a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL 0x00484a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00484a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00484a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL 0x00484a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00484b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00484b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00484b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00484b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1 0x00484b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER4 0x00484b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER5 0x00484b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER6 0x00484b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER7 0x00484b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER0_S0 0x00484b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER1_S0 0x00484b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER2_S0 0x00484b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER3_S0 0x00484b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER0_S1 0x00484b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER1_S1 0x00484b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER2_S1 0x00484b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER3_S1 0x00484b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER0_S2 0x00484b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER1_S2 0x00484b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER2_S2 0x00484b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER3_S2 0x00484b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER0_S3 0x00484b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER1_S3 0x00484b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER2_S3 0x00484b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER3_S3 0x00484b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00484b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00484b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00484b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00484b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00484b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00484b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00484b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00484b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00484b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00484b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00484b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00484b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00484b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00484b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00484b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00484ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00484ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00484ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00484bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00484bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00484bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00484bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00484bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00484bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00484bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00484e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00484e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00484e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00484e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1 0x00484e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER4 0x00484e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER5 0x00484e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER6 0x00484e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER7 0x00484e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER0_S0 0x00484e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER1_S0 0x00484e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER2_S0 0x00484e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER3_S0 0x00484e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER0_S1 0x00484e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER1_S1 0x00484e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER2_S1 0x00484e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER3_S1 0x00484e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER0_S2 0x00484e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER1_S2 0x00484e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER2_S2 0x00484e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER3_S2 0x00484e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER0_S3 0x00484e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER1_S3 0x00484e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER2_S3 0x00484e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER3_S3 0x00484e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00484e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00484e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00484e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00484e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00484e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00484e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00484e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00484e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00484e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00484e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00484e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00484e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00484e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00484e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00484e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00484ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00484ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00484ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00484eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00484eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00484eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00484eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00484ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00484ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00484ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00484f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00484f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00484f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00484f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1 0x00484f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER4 0x00484f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER5 0x00484f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER6 0x00484f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER7 0x00484f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER0_S0 0x00484f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER1_S0 0x00484f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER2_S0 0x00484f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER3_S0 0x00484f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER0_S1 0x00484f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER1_S1 0x00484f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER2_S1 0x00484f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER3_S1 0x00484f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER0_S2 0x00484f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER1_S2 0x00484f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER2_S2 0x00484f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER3_S2 0x00484f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER0_S3 0x00484f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER1_S3 0x00484f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER2_S3 0x00484f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER3_S3 0x00484f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00484f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00484f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00484f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00484f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00484f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00484f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00484f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00484f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00484f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00484f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00484f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00484f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00484f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00484f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00484f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00484fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00484fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00484fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00484fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00484fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00484fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00484fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00484fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00484fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00484fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC1_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2 0x00485000 /* RW--L */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00485200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00485204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0 0x00485208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5 0x0048520c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1 0x00485210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2 0x00485214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3 0x00485218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4 0x0048521c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL 0x00485220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL 0x00485224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL 0x00485228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL 0x0048522c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL 0x00485230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL 0x00485234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL 0x00485238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL 0x0048523c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00485240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00485244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL 0x00485248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00485300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00485304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00485308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0048530c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1 0x00485310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER4 0x00485314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER5 0x00485318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER6 0x0048531c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER7 0x00485320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER0_S0 0x00485324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER1_S0 0x00485328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER2_S0 0x0048532c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER3_S0 0x00485330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER0_S1 0x00485334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER1_S1 0x00485338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER2_S1 0x0048533c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER3_S1 0x00485340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER0_S2 0x00485344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER1_S2 0x00485348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER2_S2 0x0048534c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER3_S2 0x00485350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER0_S3 0x00485354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER1_S3 0x00485358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER2_S3 0x0048535c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER3_S3 0x00485360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00485364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00485368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0048536c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00485370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00485374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00485378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0048537c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00485380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00485384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00485388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0048538c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00485390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00485394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00485398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0048539c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x004853a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x004853a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x004853a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x004853ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x004853b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x004853b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x004853b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x004853bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x004853c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x004853c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00485600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00485604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00485608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0048560c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1 0x00485610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER4 0x00485614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER5 0x00485618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER6 0x0048561c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER7 0x00485620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER0_S0 0x00485624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER1_S0 0x00485628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER2_S0 0x0048562c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER3_S0 0x00485630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER0_S1 0x00485634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER1_S1 0x00485638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER2_S1 0x0048563c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER3_S1 0x00485640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER0_S2 0x00485644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER1_S2 0x00485648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER2_S2 0x0048564c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER3_S2 0x00485650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER0_S3 0x00485654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER1_S3 0x00485658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER2_S3 0x0048565c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER3_S3 0x00485660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00485664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00485668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0048566c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00485670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00485674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00485678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0048567c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00485680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00485684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00485688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0048568c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00485690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00485694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00485698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0048569c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x004856a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x004856a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x004856a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x004856ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x004856b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x004856b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x004856b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x004856bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x004856c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x004856c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00485700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00485704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00485708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0048570c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1 0x00485710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER4 0x00485714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER5 0x00485718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER6 0x0048571c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER7 0x00485720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER0_S0 0x00485724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER1_S0 0x00485728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER2_S0 0x0048572c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER3_S0 0x00485730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER0_S1 0x00485734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER1_S1 0x00485738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER2_S1 0x0048573c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER3_S1 0x00485740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER0_S2 0x00485744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER1_S2 0x00485748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER2_S2 0x0048574c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER3_S2 0x00485750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER0_S3 0x00485754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER1_S3 0x00485758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER2_S3 0x0048575c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER3_S3 0x00485760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00485764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00485768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0048576c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00485770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00485774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00485778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0048577c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00485780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00485784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00485788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0048578c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00485790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00485794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00485798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0048579c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x004857a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x004857a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x004857a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x004857ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x004857b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x004857b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x004857b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x004857bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x004857c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x004857c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC2_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3 0x00485800 /* RW--L */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00485a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00485a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0 0x00485a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5 0x00485a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1 0x00485a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2 0x00485a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3 0x00485a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4 0x00485a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL 0x00485a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL 0x00485a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL 0x00485a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL 0x00485a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL 0x00485a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL 0x00485a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL 0x00485a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL 0x00485a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00485a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00485a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL 0x00485a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00485b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00485b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00485b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00485b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1 0x00485b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER4 0x00485b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER5 0x00485b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER6 0x00485b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER7 0x00485b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER0_S0 0x00485b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER1_S0 0x00485b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER2_S0 0x00485b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER3_S0 0x00485b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER0_S1 0x00485b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER1_S1 0x00485b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER2_S1 0x00485b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER3_S1 0x00485b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER0_S2 0x00485b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER1_S2 0x00485b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER2_S2 0x00485b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER3_S2 0x00485b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER0_S3 0x00485b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER1_S3 0x00485b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER2_S3 0x00485b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER3_S3 0x00485b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00485b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00485b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00485b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00485b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00485b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00485b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00485b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00485b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00485b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00485b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00485b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00485b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00485b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00485b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00485b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00485ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00485ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00485ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00485bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00485bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00485bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00485bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00485bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00485bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00485bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00485e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00485e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00485e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00485e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1 0x00485e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER4 0x00485e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER5 0x00485e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER6 0x00485e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER7 0x00485e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER0_S0 0x00485e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER1_S0 0x00485e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER2_S0 0x00485e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER3_S0 0x00485e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER0_S1 0x00485e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER1_S1 0x00485e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER2_S1 0x00485e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER3_S1 0x00485e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER0_S2 0x00485e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER1_S2 0x00485e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER2_S2 0x00485e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER3_S2 0x00485e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER0_S3 0x00485e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER1_S3 0x00485e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER2_S3 0x00485e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER3_S3 0x00485e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00485e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00485e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00485e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00485e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00485e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00485e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00485e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00485e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00485e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00485e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00485e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00485e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00485e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00485e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00485e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00485ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00485ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00485ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00485eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00485eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00485eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00485eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00485ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00485ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00485ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00485f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00485f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00485f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00485f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1 0x00485f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER4 0x00485f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER5 0x00485f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER6 0x00485f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER7 0x00485f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER0_S0 0x00485f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER1_S0 0x00485f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER2_S0 0x00485f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER3_S0 0x00485f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER0_S1 0x00485f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER1_S1 0x00485f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER2_S1 0x00485f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER3_S1 0x00485f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER0_S2 0x00485f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER1_S2 0x00485f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER2_S2 0x00485f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER3_S2 0x00485f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER0_S3 0x00485f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER1_S3 0x00485f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER2_S3 0x00485f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER3_S3 0x00485f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00485f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00485f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00485f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00485f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00485f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00485f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00485f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00485f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00485f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00485f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00485f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00485f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00485f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00485f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00485f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00485fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00485fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00485fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00485fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00485fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00485fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00485fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00485fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00485fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00485fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC3_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4 0x00486000 /* RW--L */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00486200 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00486204 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0 0x00486208 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5 0x0048620c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1 0x00486210 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2 0x00486214 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3 0x00486218 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4 0x0048621c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL 0x00486220 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL 0x00486224 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL 0x00486228 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL 0x0048622c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL 0x00486230 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL 0x00486234 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL 0x00486238 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL 0x0048623c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00486240 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00486244 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL 0x00486248 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00486300 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00486304 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00486308 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3 0x0048630c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1 0x00486310 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER4 0x00486314 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER5 0x00486318 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER6 0x0048631c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER7 0x00486320 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER0_S0 0x00486324 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER1_S0 0x00486328 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER2_S0 0x0048632c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER3_S0 0x00486330 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER0_S1 0x00486334 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER1_S1 0x00486338 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER2_S1 0x0048633c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER3_S1 0x00486340 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER0_S2 0x00486344 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER1_S2 0x00486348 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER2_S2 0x0048634c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER3_S2 0x00486350 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER0_S3 0x00486354 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER1_S3 0x00486358 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER2_S3 0x0048635c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER3_S3 0x00486360 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00486364 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00486368 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0048636c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00486370 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00486374 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00486378 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x0048637c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00486380 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00486384 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00486388 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0048638c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00486390 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00486394 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00486398 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0048639c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x004863a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x004863a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x004863a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x004863ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x004863b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x004863b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x004863b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x004863bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x004863c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x004863c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00486600 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00486604 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00486608 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3 0x0048660c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1 0x00486610 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER4 0x00486614 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER5 0x00486618 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER6 0x0048661c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER7 0x00486620 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER0_S0 0x00486624 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER1_S0 0x00486628 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER2_S0 0x0048662c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER3_S0 0x00486630 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER0_S1 0x00486634 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER1_S1 0x00486638 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER2_S1 0x0048663c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER3_S1 0x00486640 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER0_S2 0x00486644 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER1_S2 0x00486648 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER2_S2 0x0048664c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER3_S2 0x00486650 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER0_S3 0x00486654 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER1_S3 0x00486658 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER2_S3 0x0048665c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER3_S3 0x00486660 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00486664 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00486668 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0048666c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00486670 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00486674 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00486678 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x0048667c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00486680 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00486684 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00486688 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0048668c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00486690 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00486694 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00486698 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0048669c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x004866a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x004866a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x004866a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x004866ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x004866b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x004866b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x004866b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x004866bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x004866c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x004866c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00486700 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00486704 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00486708 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3 0x0048670c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1 0x00486710 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER4 0x00486714 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER5 0x00486718 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER6 0x0048671c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER7 0x00486720 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER0_S0 0x00486724 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER1_S0 0x00486728 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER2_S0 0x0048672c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER3_S0 0x00486730 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER0_S1 0x00486734 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER1_S1 0x00486738 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER2_S1 0x0048673c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER3_S1 0x00486740 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER0_S2 0x00486744 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER1_S2 0x00486748 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER2_S2 0x0048674c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER3_S2 0x00486750 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER0_S3 0x00486754 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER1_S3 0x00486758 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER2_S3 0x0048675c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER3_S3 0x00486760 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00486764 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00486768 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x0048676c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00486770 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00486774 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00486778 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x0048677c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00486780 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00486784 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00486788 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x0048678c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00486790 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00486794 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00486798 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x0048679c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x004867a0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x004867a4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x004867a8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x004867ac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x004867b0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x004867b4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x004867b8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x004867bc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x004867c0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x004867c4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC4_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5 0x00486800 /* RW--L */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00486a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00486a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0 0x00486a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5 0x00486a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1 0x00486a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2 0x00486a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3 0x00486a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4 0x00486a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL 0x00486a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL 0x00486a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL 0x00486a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL 0x00486a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL 0x00486a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL 0x00486a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL 0x00486a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL 0x00486a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00486a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00486a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL 0x00486a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00486b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00486b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00486b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00486b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1 0x00486b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER4 0x00486b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER5 0x00486b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER6 0x00486b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER7 0x00486b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER0_S0 0x00486b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER1_S0 0x00486b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER2_S0 0x00486b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER3_S0 0x00486b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER0_S1 0x00486b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER1_S1 0x00486b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER2_S1 0x00486b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER3_S1 0x00486b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER0_S2 0x00486b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER1_S2 0x00486b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER2_S2 0x00486b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER3_S2 0x00486b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER0_S3 0x00486b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER1_S3 0x00486b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER2_S3 0x00486b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER3_S3 0x00486b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00486b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00486b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00486b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00486b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00486b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00486b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00486b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00486b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00486b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00486b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00486b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00486b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00486b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00486b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00486b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00486ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00486ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00486ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00486bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00486bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00486bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00486bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00486bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00486bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00486bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00486e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00486e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00486e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00486e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1 0x00486e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER4 0x00486e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER5 0x00486e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER6 0x00486e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER7 0x00486e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER0_S0 0x00486e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER1_S0 0x00486e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER2_S0 0x00486e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER3_S0 0x00486e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER0_S1 0x00486e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER1_S1 0x00486e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER2_S1 0x00486e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER3_S1 0x00486e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER0_S2 0x00486e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER1_S2 0x00486e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER2_S2 0x00486e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER3_S2 0x00486e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER0_S3 0x00486e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER1_S3 0x00486e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER2_S3 0x00486e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER3_S3 0x00486e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00486e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00486e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00486e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00486e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00486e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00486e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00486e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00486e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00486e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00486e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00486e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00486e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00486e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00486e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00486e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00486ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00486ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00486ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00486eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00486eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00486eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00486eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00486ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00486ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00486ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00486f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00486f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00486f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00486f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1 0x00486f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER4 0x00486f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER5 0x00486f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER6 0x00486f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER7 0x00486f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER0_S0 0x00486f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER1_S0 0x00486f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER2_S0 0x00486f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER3_S0 0x00486f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER0_S1 0x00486f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER1_S1 0x00486f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER2_S1 0x00486f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER3_S1 0x00486f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER0_S2 0x00486f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER1_S2 0x00486f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER2_S2 0x00486f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER3_S2 0x00486f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER0_S3 0x00486f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER1_S3 0x00486f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER2_S3 0x00486f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER3_S3 0x00486f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00486f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00486f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00486f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00486f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00486f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00486f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00486f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00486f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00486f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00486f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00486f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00486f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00486f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00486f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00486f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00486fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00486fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00486fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00486fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00486fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00486fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00486fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00486fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00486fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00486fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPC5_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS 0x00481800 /* RW--L */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00481a00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL0_GRP3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00481a04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SEL1_GRP7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0 0x00481a08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_EDGE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_MODE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_WINDOWED3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL0_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5 0x00481a0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4 2:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5 7:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6 8:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6 10:9 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6 11:11 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7 12:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_EDGE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7 14:13 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_LUT 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_COUNT 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_PASS 0x2 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_MODE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7 15:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_WINDOWED7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL5_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1 0x00481a10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC0_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL1_FUNC1_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2 0x00481a14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC2_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL2_FUNC3_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3 0x00481a18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC4_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL3_FUNC5_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4 0x00481a1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC6_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7 31:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL4_FUNC7_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL 0x00481a20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER0_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL 0x00481a24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER1_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL 0x00481a28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER2_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL 0x00481a2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER3_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL 0x00481a30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER4_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL 0x00481a34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER5_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL 0x00481a38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER6_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL 0x00481a3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT0_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP 6:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG 9:7 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT1_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP 11:10 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG 14:12 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT2_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP 16:15 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG 19:17 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT3_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP 21:20 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG 24:22 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT4_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP 26:25 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG 29:27 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER7_CONTROL_BIT5_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL 0x00481a40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE0_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE1_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE2_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER0_CONTROL_ENABLE3_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL 0x00481a44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP 1:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_GRP_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG 4:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_SIG_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4 28:28 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE4_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE5_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE6_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_FILTER4_CONTROL_ENABLE7_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL 0x00481a48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT 0:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAPSHOT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT 1:1 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_STREAMOUT_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW 2:2 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE 3:3 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_RESPECT_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE 4:4 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_ENABLE 0x1 /* RW--V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_SNAP_IN_FREEZE_INIT 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL 28:5 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM_DSM_PERF_COUNTER_CONTROL_OVERFLOW_VAL_INIT 0xffffff /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0 0x00481b00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1 0x00481b04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2 0x00481b08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3 0x00481b0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1 0x00481b10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER4 0x00481b14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER5 0x00481b18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER6 0x00481b1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER7 0x00481b20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER0_S0 0x00481b24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER1_S0 0x00481b28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER2_S0 0x00481b2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER3_S0 0x00481b30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER0_S1 0x00481b34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER1_S1 0x00481b38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER2_S1 0x00481b3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER3_S1 0x00481b40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER0_S2 0x00481b44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER1_S2 0x00481b48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER2_S2 0x00481b4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER3_S2 0x00481b50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER0_S3 0x00481b54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER1_S3 0x00481b58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER2_S3 0x00481b5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER3_S3 0x00481b60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00481b64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00481b68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00481b6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00481b70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00481b74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4 0x00481b78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5 0x00481b7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6 0x00481b80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7 0x00481b84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00481b88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00481b8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00481b90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00481b94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00481b98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00481b9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00481ba0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00481ba4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00481ba8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00481bac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00481bb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00481bb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00481bb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00481bbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00481bc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00481bc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SMS_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0 0x00481e00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1 0x00481e04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2 0x00481e08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3 0x00481e0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1 0x00481e10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER4 0x00481e14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER5 0x00481e18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER6 0x00481e1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER7 0x00481e20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER0_S0 0x00481e24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER1_S0 0x00481e28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER2_S0 0x00481e2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER3_S0 0x00481e30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER0_S1 0x00481e34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER1_S1 0x00481e38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER2_S1 0x00481e3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER3_S1 0x00481e40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER0_S2 0x00481e44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER1_S2 0x00481e48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER2_S2 0x00481e4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER3_S2 0x00481e50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER0_S3 0x00481e54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER1_S3 0x00481e58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER2_S3 0x00481e5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER3_S3 0x00481e60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00481e64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00481e68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00481e6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00481e70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00481e74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4 0x00481e78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5 0x00481e7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6 0x00481e80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7 0x00481e84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00481e88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00481e8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00481e90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00481e94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00481e98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00481e9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00481ea0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00481ea4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00481ea8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00481eac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00481eb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00481eb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00481eb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00481ebc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00481ec0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00481ec4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM0_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0 0x00481f00 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1 0x00481f04 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2 0x00481f08 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3 0x00481f0c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1 0x00481f10 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER4 0x00481f14 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER5 0x00481f18 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER6 0x00481f1c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER7 0x00481f20 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER0_S0 0x00481f24 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER1_S0 0x00481f28 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER2_S0 0x00481f2c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER3_S0 0x00481f30 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER0_S1 0x00481f34 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER1_S1 0x00481f38 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER2_S1 0x00481f3c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER3_S1 0x00481f40 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER0_S2 0x00481f44 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER1_S2 0x00481f48 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER2_S2 0x00481f4c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER3_S2 0x00481f50 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER0_S3 0x00481f54 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER1_S3 0x00481f58 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER2_S3 0x00481f5c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER3_S3 0x00481f60 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0 0x00481f64 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S0_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1 0x00481f68 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S1_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2 0x00481f6c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S2_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3 0x00481f70 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW0_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW1_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW2_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS_S3_OVERFLOW3_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1 0x00481f74 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4 7:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW4_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5 15:8 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW5_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6 23:16 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW6_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7 31:24 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT_STATUS1_OVERFLOW7_INIT 0x00 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4 0x00481f78 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT4_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5 0x00481f7c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT5_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6 0x00481f80 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT6_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7 0x00481f84 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT7_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0 0x00481f88 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0 0x00481f8c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0 0x00481f90 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0 0x00481f94 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S0_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1 0x00481f98 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1 0x00481f9c /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1 0x00481fa0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1 0x00481fa4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2 0x00481fa8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2 0x00481fac /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2 0x00481fb0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2 0x00481fb4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3 0x00481fb8 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT0_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3 0x00481fbc /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT1_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3 0x00481fc0 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT2_S3_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3 0x00481fc4 /* RW-4R */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_EGPCS_ETPCS_SM1_DSM_PERF_COUNTER_SNAPSHOT3_S3_VALUE_INIT 0x00000000 /* RWE-V */ #endif // __ga102_dev_graphics_nobundle_h__